2 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/regs-pinctrl.h>
25 #include <asm/arch/pinctrl.h>
26 #include <asm/arch/regs-clkctrl.h>
27 #include <asm/arch/regs-ocotp.h>
30 #include <imx_ssp_mmc.h>
32 /* This should be removed after it's added into mach-types.h */
33 #ifndef MACH_TYPE_MX28EVK
34 #define MACH_TYPE_MX28EVK 2531
37 DECLARE_GLOBAL_DATA_PTR;
39 #ifdef CONFIG_IMX_SSP_MMC
42 static struct pin_desc mmc0_pins_desc[] = {
43 { PINID_SSP0_DATA0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
44 { PINID_SSP0_DATA1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
45 { PINID_SSP0_DATA2, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
46 { PINID_SSP0_DATA3, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
47 { PINID_SSP0_DATA4, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
48 { PINID_SSP0_DATA5, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
49 { PINID_SSP0_DATA6, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
50 { PINID_SSP0_DATA7, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
51 { PINID_SSP0_CMD, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
52 { PINID_SSP0_DETECT, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
53 { PINID_SSP0_SCK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
56 static struct pin_desc mmc1_pins_desc[] = {
57 { PINID_GPMI_D00, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
58 { PINID_GPMI_D01, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
59 { PINID_GPMI_D02, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
60 { PINID_GPMI_D03, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
61 { PINID_GPMI_D04, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
62 { PINID_GPMI_D05, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
63 { PINID_GPMI_D06, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
64 { PINID_GPMI_D07, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
65 { PINID_GPMI_RDY1, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
66 { PINID_GPMI_RDY0, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
67 { PINID_GPMI_WRN, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }
70 static struct pin_group mmc0_pins = {
71 .pins = mmc0_pins_desc,
72 .nr_pins = ARRAY_SIZE(mmc0_pins_desc)
75 static struct pin_group mmc1_pins = {
76 .pins = mmc1_pins_desc,
77 .nr_pins = ARRAY_SIZE(mmc1_pins_desc)
80 struct imx_ssp_mmc_cfg ssp_mmc_cfg[2] = {
81 {REGS_SSP0_BASE, HW_CLKCTRL_SSP0, BM_CLKCTRL_CLKSEQ_BYPASS_SSP0},
82 {REGS_SSP1_BASE, HW_CLKCTRL_SSP1, BM_CLKCTRL_CLKSEQ_BYPASS_SSP1},
87 static struct pin_desc enet_pins_desc[] = {
88 { PINID_ENET0_MDC, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
89 { PINID_ENET0_MDIO, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
90 { PINID_ENET0_RX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
91 { PINID_ENET0_RXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
92 { PINID_ENET0_RXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
93 { PINID_ENET0_TX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
94 { PINID_ENET0_TXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
95 { PINID_ENET0_TXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
96 { PINID_ENET_CLK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }
99 static struct pin_group enet_pins = {
100 .pins = enet_pins_desc,
101 .nr_pins = ARRAY_SIZE(enet_pins_desc)
109 /* Will change it for MX28 EVK later */
110 gd->bd->bi_arch_number = MACH_TYPE_MX28EVK;
111 /* Adress of boot parameters */
112 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
119 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
120 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
125 #ifdef CONFIG_IMX_SSP_MMC
127 #ifdef CONFIG_DYNAMIC_MMC_DEVNO
128 int get_mmc_env_devno()
130 unsigned long global_boot_mode;
132 global_boot_mode = REG_RD_ADDR(GLOBAL_BOOT_MODE_ADDR);
133 return ((global_boot_mode & 0xf) == BOOT_MODE_SD1) ? 1 : 0;
137 #define PINID_SSP0_GPIO_WP PINID_SSP1_SCK
138 #define PINID_SSP1_GPIO_WP PINID_GPMI_RESETN
140 u32 ssp_mmc_is_wp(struct mmc *mmc)
142 return (mmc->block_dev.dev == 0) ?
143 pin_gpio_get(PINID_SSP0_GPIO_WP) :
144 pin_gpio_get(PINID_SSP1_GPIO_WP);
147 int ssp_mmc_gpio_init(bd_t *bis)
152 for (index = 0; index < CONFIG_SYS_SSP_MMC_NUM;
156 /* Set up MMC pins */
157 pin_set_group(&mmc0_pins);
159 /* Power on the card slot 0 */
160 pin_set_type(PINID_PWM3, PIN_GPIO);
161 pin_gpio_direction(PINID_PWM3, 1);
162 pin_gpio_set(PINID_PWM3, 0);
164 /* Wait 10 ms for card ramping up */
167 /* Set up SD0 WP pin */
168 pin_set_type(PINID_SSP0_GPIO_WP, PIN_GPIO);
169 pin_gpio_direction(PINID_SSP0_GPIO_WP, 0);
173 /* Set up MMC pins */
174 pin_set_group(&mmc1_pins);
176 /* Power on the card slot 1 */
177 pin_set_type(PINID_PWM4, PIN_GPIO);
178 pin_gpio_direction(PINID_PWM4, 1);
179 pin_gpio_set(PINID_PWM4, 0);
181 /* Wait 10 ms for card ramping up */
184 /* Set up SD1 WP pin */
185 pin_set_type(PINID_SSP1_GPIO_WP, PIN_GPIO);
186 pin_gpio_direction(PINID_SSP1_GPIO_WP, 0);
190 printf("Warning: you configured more ssp mmc controller"
191 "(%d) as supported by the board(2)\n",
192 CONFIG_SYS_SSP_MMC_NUM);
195 status |= imx_ssp_mmc_initialize(bis, &ssp_mmc_cfg[index]);
201 int board_mmc_init(bd_t *bis)
203 if (!ssp_mmc_gpio_init(bis))
211 #ifdef CONFIG_MXC_FEC
212 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
213 int fec_get_mac_addr(unsigned char *mac)
217 /*set this bit to open the OTP banks for reading*/
218 REG_WR(REGS_OCOTP_BASE, HW_OCOTP_CTRL_SET,
219 BM_OCOTP_CTRL_RD_BANK_OPEN);
221 /*wait until OTP contents are readable*/
222 while (BM_OCOTP_CTRL_BUSY & REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CTRL))
227 val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(0));
228 mac[2] = (val >> 24) & 0xFF;
229 mac[3] = (val >> 16) & 0xFF;
230 mac[4] = (val >> 8) & 0xFF;
231 mac[5] = (val >> 0) & 0xFF;
237 void enet_board_init(void)
239 /* Set up ENET pins */
240 pin_set_group(&enet_pins);
242 /* Power on the external phy */
243 pin_set_type(PINID_SSP1_DATA3, PIN_GPIO);
244 pin_gpio_direction(PINID_SSP1_DATA3, 1);
245 pin_gpio_set(PINID_SSP1_DATA3, 0);
247 /* Reset the external phy */
248 pin_set_type(PINID_ENET0_RX_CLK, PIN_GPIO);
249 pin_gpio_direction(PINID_ENET0_RX_CLK, 1);
250 pin_gpio_set(PINID_ENET0_RX_CLK, 0);
252 pin_gpio_set(PINID_ENET0_RX_CLK, 1);