2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/mx35.h>
24 #include "board-mx35_3stack.h"
32 .macro check_soc_version ret, tmp
33 ldr \tmp, =IIM_BASE_ADDR
34 ldr \ret, [\tmp, #IIM_SREV]
36 moveq \tmp, #ROMPATCH_REV
38 moveq \ret, \ret, lsl #4
39 addne \ret, \ret, #0x10
43 * L2CC Cache setup/invalidation/disable
46 /* Disable L2 cache first */
47 mov r0, #L2CC_BASE_ADDR
48 ldr r1, [r0, #L2_CACHE_CTL_REG]
50 str r1, [r0, #L2_CACHE_CTL_REG]
54 * - 128k size(16k way)
55 * - 8-way associativity
56 * - 0 ws TAG/VALID/DIRTY
59 ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
60 and r1, r1, #0xFE000000
61 ldr r2, =L2CC_AUX_CTL_CONFIG
63 str r1, [r0, #L2_CACHE_AUX_CTL_REG]
65 /* Workaournd for TO1 DDR issue:WT*/
66 check_soc_version r1, r2
68 ldrlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
70 strlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
74 str r1, [r0, #L2_CACHE_INV_WAY_REG]
76 /* Poll Invalidate By Way register */
77 ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
82 /* AIPS setup - Only setup MPROTx registers.
83 * The PACR default values are good.*/
86 * Set all MPROTx to be non-bufferable, trusted for R/W,
87 * not forced to user-mode.
89 ldr r0, =AIPS1_BASE_ADDR
90 ldr r1, =AIPS_MPR_CONFIG
93 ldr r0, =AIPS2_BASE_ADDR
98 * Clear the on and off peripheral modules Supervisor Protect bit
99 * for SDMA to access them. Did not change the AIPS control registers
100 * (offset 0x20) access type
102 ldr r0, =AIPS1_BASE_ADDR
103 ldr r1, =AIPS_OPACR_CONFIG
109 ldr r0, =AIPS2_BASE_ADDR
115 .endm /* init_aips */
117 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
119 ldr r0, =MAX_BASE_ADDR
120 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
121 ldr r1, =MAX_MPR_CONFIG
122 str r1, [r0, #0x000] /* for S0 */
123 str r1, [r0, #0x100] /* for S1 */
124 str r1, [r0, #0x200] /* for S2 */
125 str r1, [r0, #0x300] /* for S3 */
126 str r1, [r0, #0x400] /* for S4 */
127 /* SGPCR - always park on last master */
128 ldr r1, =MAX_SGPCR_CONFIG
129 str r1, [r0, #0x010] /* for S0 */
130 str r1, [r0, #0x110] /* for S1 */
131 str r1, [r0, #0x210] /* for S2 */
132 str r1, [r0, #0x310] /* for S3 */
133 str r1, [r0, #0x410] /* for S4 */
134 /* MGPCR - restore default values */
135 ldr r1, =MAX_MGPCR_CONFIG
136 str r1, [r0, #0x800] /* for M0 */
137 str r1, [r0, #0x900] /* for M1 */
138 str r1, [r0, #0xA00] /* for M2 */
139 str r1, [r0, #0xB00] /* for M3 */
140 str r1, [r0, #0xC00] /* for M4 */
141 str r1, [r0, #0xD00] /* for M5 */
146 /* Configure M3IF registers */
147 ldr r1, =M3IF_BASE_ADDR
149 * M3IF Control Register (M3IFCTL)
150 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
151 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
152 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
153 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
154 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
155 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
156 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
157 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
162 str r0, [r1] /* M3IF control reg */
163 .endm /* init_m3if */
165 /* To support 133MHz DDR */
166 .macro init_drive_strength
169 ldr r1, =IOMUXC_BASE_ADDR
171 add r2, r1, #0x4C8 - 0x368
176 .endm /* init_drive_strength */
178 /* CPLD on CS5 setup */
179 .macro init_debug_board
180 ldr r0, =DBG_BASE_ADDR
181 ldr r1, =DBG_CSCR_U_CONFIG
183 ldr r1, =DBG_CSCR_L_CONFIG
185 ldr r1, =DBG_CSCR_A_CONFIG
187 .endm /* init_debug_board */
191 ldr r0, =CCM_BASE_ADDR
193 /* default CLKO to 1/32 of the ARM core*/
194 ldr r1, [r0, #CLKCTL_COSR]
195 bic r1, r1, #0x00000FF00
196 bic r1, r1, #0x0000000FF
200 str r1, [r0, #CLKCTL_COSR]
202 ldr r2, =CCM_CCMR_CONFIG
203 str r2, [r0, #CLKCTL_CCMR]
205 check_soc_version r1, r2
206 cmp r1, #CHIP_REV_2_0
207 ldrhs r3, =CCM_MPLL_532_HZ
209 ldr r2, [r0, #CLKCTL_PDR0]
210 tst r2, #CLKMODE_CONSUMER
211 ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
212 ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
214 str r3, [r0, #CLKCTL_MPCTL]
216 ldr r1, =CCM_PPLL_300_HZ
217 str r1, [r0, #CLKCTL_PPCTL]
219 ldr r1, =CCM_PDR0_CONFIG
220 bic r1, r1, #0x800000
221 str r1, [r0, #CLKCTL_PDR0]
223 ldr r1, [r0, #CLKCTL_CGR0]
224 orr r1, r1, #0x0C300000
225 str r1, [r0, #CLKCTL_CGR0]
227 ldr r1, [r0, #CLKCTL_CGR1]
228 orr r1, r1, #0x00000C00
229 orr r1, r1, #0x00000003
230 str r1, [r0, #CLKCTL_CGR1]
231 .endm /* init_clock */
234 ldr r0, =ESDCTL_BASE_ADDR
239 /*ip(r12) has used to save lr register in upper calling*/
244 mov r1, #CSD0_BASE_ADDR
249 blne setup_sdram_bank
253 check_soc_version r3, r4
254 cmp r1, #CHIP_REV_2_0
257 movne r3, #L2CC_BASE_ADDR
258 ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG]
259 orrne r4, r4, #0x1000
260 strne r4, [r3, #L2_CACHE_AUX_CTL_REG]
262 ldr r3, =ESDCTL_DELAY_LINE5
264 .endm /* setup_sdram */
266 .section ".text.init", "x"
270 /* Platform CHIP level init*/
271 #ifdef TURN_OFF_IMPRECISE_ABORT
277 mrc 15, 0, r1, c1, c0, 0
279 #ifndef BRANCH_PREDICTION_ENABLE
280 mrc 15, 0, r0, c1, c0, 1
282 mcr 15, 0, r0, c1, c0, 1
284 mrc 15, 0, r0, c1, c0, 1
286 mcr 15, 0, r0, c1, c0, 1
290 #ifdef UNALIGNED_ACCESS_ENABLE
294 #ifdef LOW_INT_LATENCY_ENABLE
297 mcr 15, 0, r1, c1, c0, 0
300 #ifdef BRANCH_PREDICTION_ENABLE
301 mcr 15, 0, r0, c15, c2, 4
303 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
304 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
305 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
307 /* initializes very early AIPS, what for?
308 * Then it also initializes Multi-Layer AHB Crossbar Switch,
310 /* Also setup the Peripheral Port Remap register inside the core */
311 ldr r0, =0x40000015 /* start from AIPS 2GB region */
312 mcr p15, 0, r0, c15, c2, 4
327 cmp pc, #PHYS_SDRAM_1
329 cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
336 mov r0, #NFC_BASE_ADDR
337 add r1, r0, #NFC_BUF_SIZE
342 /* return from mxc_nand_load */
343 /* r12 saved upper lr*/
347 * r0: ESDCTL control base, r1: sdram slot base
348 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
351 mov r3, #0xE /*0xA + 0x4*/
353 orreq r3, r3, #0x300 /*DDR2*/
364 ldreq r3, =ESDCTL_DDR2_CONFIG
365 ldrne r3, =ESDCTL_MDDR_CONFIG
366 cmp r1, #CSD1_BASE_ADDR
370 ldr r3, =ESDCTL_0x92220000
374 ldr r4, =ESDCTL_PRECHARGE
380 cmp r1, #CSD1_BASE_ADDR
381 ldr r3, =ESDCTL_0xB2220000
385 ldr r4, =ESDCTL_DDR2_EMR2
387 ldr r4, =ESDCTL_DDR2_EMR3
389 ldr r4, =ESDCTL_DDR2_EN_DLL
391 ldr r4, =ESDCTL_DDR2_RESET_DLL
394 ldr r3, =ESDCTL_0x92220000
398 ldr r4, =ESDCTL_PRECHARGE
402 cmp r1, #CSD1_BASE_ADDR
403 ldr r3, =ESDCTL_0xA2220000
410 ldr r3, =ESDCTL_0xB2220000
414 ldreq r4, =ESDCTL_DDR2_MR
415 ldrne r4, =ESDCTL_MDDR_MR
418 ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
420 ldreq r4, =ESDCTL_DDR2_EN_DLL
421 ldrne r4, =ESDCTL_MDDR_EMR
424 cmp r1, #CSD1_BASE_ADDR
425 ldr r3, =ESDCTL_0x82228080