2 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #include <asm/arch/mx50.h>
23 #ifdef CONFIG_FLASH_HEADER
24 #ifndef CONFIG_FLASH_HEADER_OFFSET
25 # error "Must define the offset of flash header"
28 .section ".text.flasheader", "x"
30 .org CONFIG_FLASH_HEADER_OFFSET
32 /* First IVT to copy the plugin that initializes the system into OCRAM */
33 ivt_header: .long 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
34 app_code_jump_v: .long 0xF8006458 /* Plugin entry point */
37 boot_data_ptr: .long 0xF8006420
38 self_ptr: .long 0xF8006400
39 app_code_csf: .long 0x0 /* reserve 4K for csf */
41 boot_data: .long 0xF8006000
42 image_len: .long 8*1024 /* Can copy upto 72K, OCRAM free space */
43 plugin: .long 0x1 /* Enable plugin flag */
45 /* Second IVT to give entry point into the bootloader copied to DDR */
46 ivt2_header: .long 0x402000D1 //Tag=0xD1, Len=0x0020, Ver=0x40
47 app2_code_jump_v: .long _start // Entry point for the bootloader
50 boot_data2_ptr: .long boot_data2
51 self_ptr2: .long ivt2_header
52 app_code_csf2: .long 0x0 // reserve 4K for csf
54 boot_data2: .long TEXT_BASE
55 image_len2: .long _end - TEXT_BASE
58 /*=============================================================================
59 * Here starts the plugin code
60 *===========================================================================*/
63 /* Save the return address and the function arguments */
66 /*=============================================================================
67 *init script for codex LPDDR1-200MHz CPU board
68 *===========================================================================*/
70 /* Setup PLL1 to be 800 MHz */
71 ldr r0, =CCM_BASE_ADDR
73 /* Switch ARM domain to be clocked from LP-APM */
75 str r1, [r0, #CLKCTL_CCSR]
77 ldr r0, =PLL1_BASE_ADDR
79 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
81 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
84 str r1, [r0, #PLL_DP_OP]
85 str r1, [r0, #PLL_DP_HFS_OP]
88 str r1, [r0, #PLL_DP_MFD]
89 str r1, [r0, #PLL_DP_HFS_MFD]
92 str r1, [r0, #PLL_DP_MFN]
93 str r1, [r0, #PLL_DP_HFS_MFN]
97 str r1, [r0, #PLL_DP_CTL]
99 ldr r1, [r0, #PLL_DP_CTL]
103 /* Switch ARM back to PLL1 */
104 ldr r0, =CCM_BASE_ADDR
106 str r1, [r0,#CLKCTL_CCSR]
108 /*=============================================================================
109 * Enable all clocks (they are disabled by ROM code)
110 *===========================================================================*/
122 #if defined(CONFIG_LPDDR2)
124 /* DDR clock setting -- Set DDR to be div 3 to get 266MHz */
125 /* setmem /32 0x53FD4098 = 0x80000003 */
129 /* poll to make sure DDR dividers take effect */
135 /*=============================================================================
137 *===========================================================================*/
159 /*=============================================================================
161 *===========================================================================*/
163 ldr r0, =DATABAHN_BASE_ADDR
164 /* setmem /32 0x14000000 = 0x00000500 */
167 /* setmem /32 0x14000004 = 0x00000000 */
170 /* setmem /32 0x14000008 = 0x0000001b */
173 /* setmem /32 0x1400000c = 0x0000d056 */
176 /* setmem /32 0x14000010 = 0x0000010b */
179 /* setmem /32 0x14000014 = 0x00000a6b */
182 /* setmem /32 0x14000018 = 0x02020d0c */
185 /* setmem /32 0x1400001c = 0x0c110302 */
188 /* setmem /32 0x14000020 = 0x05020503 */
191 /* setmem /32 0x14000024 = 0x00000105 */
194 /* setmem /32 0x14000028 = 0x01000403 */
197 /* setmem /32 0x1400002c = 0x09040501 */
200 /* setmem /32 0x14000030 = 0x02000000 */
203 /* setmem /32 0x14000034 = 0x00000e02 */
206 /* setmem /32 0x14000038 = 0x00000006 */
209 /* setmem /32 0x1400003c = 0x00002301 */
212 /* setmem /32 0x14000040 = 0x00050408 */
215 /* setmem /32 0x14000044 = 0x00000300 */
218 /* setmem /32 0x14000048 = 0x00260026 */
221 /* setmem /32 0x1400004c = 0x00010000 */
224 /* setmem /32 0x1400005c = 0x02000000 */
227 /* setmem /32 0x14000060 = 0x00000002 */
230 /* setmem /32 0x14000064 = 0x00000000 */
233 /* setmem /32 0x14000068 = 0x00000000 */
236 /* setmem /32 0x1400006c = 0x00040042 */
239 /* setmem /32 0x14000070 = 0x00000001 */
242 /* setmem /32 0x14000074 = 0x00000000 */
245 /* setmem /32 0x14000078 = 0x00040042 */
248 /* setmem /32 0x1400007c = 0x00000001 */
251 /* setmem /32 0x14000080 = 0x010b0000 */
254 /* setmem /32 0x14000084 = 0x00000060 */
257 /* setmem /32 0x14000088 = 0x02400018 */
260 /* setmem /32 0x1400008c = 0x01000e00 */
263 /* setmem /32 0x14000090 = 0x0a010101 */
266 /* setmem /32 0x14000094 = 0x01011f1f */
269 /* setmem /32 0x14000098 = 0x01010101 */
272 /* setmem /32 0x1400009c = 0x00030101 */
275 /* setmem /32 0x140000a0 = 0x00010000 */
278 /* setmem /32 0x140000a4 = 0x00010000 */
281 /* setmem /32 0x140000a8 = 0x00000000 */
284 /* setmem /32 0x140000ac = 0x0000ffff */
287 /* setmem /32 0x140000c8 = 0x02020101 */
290 /* setmem /32 0x140000cc = 0x01000000 */
293 /* setmem /32 0x140000d0 = 0x01000201 */
296 /* setmem /32 0x140000d4 = 0x00000200 */
299 /* setmem /32 0x140000d8 = 0x00000102 */
302 /* setmem /32 0x140000dc = 0x0000ffff */
305 /* setmem /32 0x140000e0 = 0x0000ffff */
308 /* setmem /32 0x140000e4 = 0x02020000 */
311 /* setmem /32 0x140000e8 = 0x02020202 */
314 /* setmem /32 0x140000ec = 0x00000202 */
317 /* setmem /32 0x140000f0 = 0x01010064 */
320 /* setmem /32 0x140000f4 = 0x01010101 */
323 /* setmem /32 0x140000f8 = 0x00010101 */
326 /* setmem /32 0x140000fc = 0x00000064 */
329 /* setmem /32 0x14000100 = 0x00000000 */
332 /* setmem /32 0x14000104 = 0x02000802 */
335 /* setmem /32 0x14000108 = 0x04080000 */
338 /* setmem /32 0x1400010c = 0x04080408 */
341 /* setmem /32 0x14000110 = 0x04080408 */
344 /* setmem /32 0x14000114 = 0x03060408 */
347 /* setmem /32 0x14000118 = 0x01010002 */
350 /* setmem /32 0x1400011c = 0x00000000 */
353 /* setmem /32 0x14000200 = 0x00000000 */
356 /* setmem /32 0x14000204 = 0x00000000 */
359 /* setmem /32 0x14000208 = 0xf5003a27 */
362 /* setmem /32 0x1400020c = 0x074002e1 */
365 /* setmem /32 0x14000210 = 0xf5003a27 */
368 /* setmem /32 0x14000214 = 0x074002e1 */
371 /* setmem /32 0x14000218 = 0xf5003a27 */
374 /* setmem /32 0x1400021c = 0x074002e1 */
377 /* setmem /32 0x14000220 = 0xf5003a27 */
380 /* setmem /32 0x14000224 = 0x074002e1 */
383 /* setmem /32 0x14000228 = 0xf5003a27 */
386 /* setmem /32 0x1400022c = 0x074002e1 */
389 /* setmem /32 0x14000230 = 0x00000000 */
392 /* setmem /32 0x14000234 = 0x00810006 */
395 /* setmem /32 0x14000238 = 0x20099414 */
398 /* setmem /32 0x1400023c = 0x000a1401 */
401 /* setmem /32 0x14000240 = 0x20099414 */
404 /* setmem /32 0x14000244 = 0x000a1401 */
407 /* setmem /32 0x14000248 = 0x20099414 */
410 /* setmem /32 0x1400024c = 0x000a1401 */
413 /* setmem /32 0x14000250 = 0x20099414 */
416 /* setmem /32 0x14000254 = 0x000a1401 */
419 /* setmem /32 0x14000258 = 0x20099414 */
422 /* setmem /32 0x1400025c = 0x000a1401 */
427 /* setmem /32 0x14000000 = 0x00000501 // bit[0]: start */
430 /* poll to make sure it is done */
437 /*==================================================================
439 *=================================================================*/
441 /* DDR clock setting -- Set DDR to be div 4 to get 200MHz */
442 /* setmem /32 0x53FD4098 = 0x80000004 */
446 /* poll to make sure DDR dividers take effect */
452 /*==================================================================
454 *=================================================================*/
482 /*==============================================================
484 *=============================================================*/
485 ldr r0, =DATABAHN_BASE_ADDR
486 /* setmem /32 0x14000000 = 0x00000100 */
489 /* setmem /32 0x14000008 = 0x00009c40 */
492 /* setmem /32 0x14000014 = 0x02000000 */
495 /* setmem /32 0x14000018 = 0x01010706 */
498 /* setmem /32 0x1400001c = 0x080b0201 */
501 /* setmem /32 0x14000020 = 0x02000303 */
504 /* setmem /32 0x14000024 = 0x0136b002 */
507 /* setmem /32 0x14000028 = 0x01000101 */
510 /* setmem /32 0x1400002c = 0x06030301 */
513 /* setmem /32 0x14000030 = 0x00000000 */
516 /* setmem /32 0x14000034 = 0x00000a02 */
519 /* setmem /32 0x14000038 = 0x00000003 */
522 /* setmem /32 0x1400003c = 0x00001401 */
525 /* setmem /32 0x14000040 = 0x0005030f */
528 /* setmem /32 0x14000044 = 0x00000200 */
531 /* setmem /32 0x14000048 = 0x00180018 */
534 /* setmem /32 0x1400004c = 0x00010000 */
537 /* setmem /32 0x1400005c = 0x01000000 */
540 /* setmem /32 0x14000060 = 0x00000001 */
543 /* setmem /32 0x14000064 = 0x00000000 */
546 /* setmem /32 0x14000068 = 0x00320000 */
549 /* setmem /32 0x1400006c = 0x00000000 */
552 /* setmem /32 0x14000070 = 0x00000000 */
555 /* setmem /32 0x14000074 = 0x00320000 */
558 /* setmem /32 0x14000080 = 0x02000000 */
561 /* setmem /32 0x14000084 = 0x00000100 */
564 /* setmem /32 0x14000088 = 0x02400040 */
567 /* setmem /32 0x1400008c = 0x01000000 */
570 /* setmem /32 0x14000090 = 0x0a000100 */
573 /* setmem /32 0x14000094 = 0x01011f1f */
576 /* setmem /32 0x14000098 = 0x01010101 */
579 /* setmem /32 0x1400009c = 0x00030101 */
582 /* setmem /32 0x140000a4 = 0x00010000 */
585 /* setmem /32 0x140000ac = 0x0000ffff */
588 /* setmem /32 0x140000c8 = 0x02020101 */
591 /* setmem /32 0x140000cc = 0x00000000 */
594 /* setmem /32 0x140000d0 = 0x01000202 */
597 /* setmem /32 0x140000d4 = 0x02030302 */
600 /* setmem /32 0x140000d8 = 0x00000001 */
603 /* setmem /32 0x140000dc = 0x0000ffff */
606 /* setmem /32 0x140000e0 = 0x0000ffff */
609 /* setmem /32 0x140000e4 = 0x02020000 */
612 /* setmem /32 0x140000e8 = 0x02020202 */
615 /* setmem /32 0x140000ec = 0x00000202 */
618 /* setmem /32 0x140000f0 = 0x01010064 */
621 /* setmem /32 0x140000f4 = 0x01010101 */
624 /* setmem /32 0x140000f8 = 0x00010101 */
627 /* setmem /32 0x140000fc = 0x00000064 */
630 /* setmem /32 0x14000104 = 0x02000602 */
632 str r1, [r0, #0x0104]
633 /* setmem /32 0x14000108 = 0x06120000 */
635 str r1, [r0, #0x0108]
636 /* setmem /32 0x1400010c = 0x06120612 */
638 str r1, [r0, #0x010c]
639 /* setmem /32 0x14000110 = 0x06120612 */
641 str r1, [r0, #0x0110]
642 /* setmem /32 0x14000114 = 0x01030612 */
644 str r1, [r0, #0x0114]
645 /* setmem /32 0x14000118 = 0x01010002 */
647 str r1, [r0, #0x0118]
649 /*=============================================================
651 *===========================================================*/
653 /* setmem /32 0x14000200 = 0x00000000 */
656 /* setmem /32 0x14000204 = 0x00000000 */
658 str r1, [r0, #0x0204]
660 /* setmem /32 0x14000208 = 0xf5002725 */
662 str r1, [r0, #0x0208]
663 /* setmem /32 0x14000210 = 0xf5002725 */
666 /* setmem /32 0x14000218 = 0xf5002725 */
669 /* setmem /32 0x14000220 = 0xf5002725 */
671 str r1, [r0, #0x0220]
672 /* setmem /32 0x14000228 = 0xf5002725 */
674 str r1, [r0, #0x0228]
676 /* setmem /32 0x1400020c = 0x070002d0 */
678 str r1, [r0, #0x020c]
680 /* setmem /32 0x14000214 = 0x074002d0 */
682 str r1, [r0, #0x0214]
684 /* setmem /32 0x1400021c = 0x074002d0 */
686 str r1, [r0, #0x021c]
688 /* setmem /32 0x14000224 = 0x074002d0 */
690 str r1, [r0, #0x0224]
692 /* setmem /32 0x1400022c = 0x074002d0 */
694 str r1, [r0, #0x022c]
695 /* setmem /32 0x14000230 = 0x00000000 */
697 str r1, [r0, #0x0230]
698 /* setmem /32 0x14000234 = 0x00800006 */
700 str r1, [r0, #0x0234]
702 /* setmem /32 0x14000238 = 0x200e1014 */
704 str r1, [r0, #0x0238]
705 /* setmem /32 0x14000240 = 0x200e1014 */
707 str r1, [r0, #0x0240]
708 /* setmem /32 0x14000248 = 0x200e1014 */
710 str r1, [r0, #0x0248]
711 /* setmem /32 0x14000250 = 0x200e1014 */
713 str r1, [r0, #0x0250]
714 /* setmem /32 0x14000258 = 0x200e1014 */
716 str r1, [r0, #0x0258]
718 /* setmem /32 0x1400023c = 0x000d9f01 */
720 str r1, [r0, #0x023c]
721 /* setmem /32 0x14000244 = 0x000d9f01 */
723 str r1, [r0, #0x0244]
724 /* setmem /32 0x1400024c = 0x000d9f01 */
726 str r1, [r0, #0x024c]
727 /* setmem /32 0x14000254 = 0x000d9f01 */
729 str r1, [r0, #0x0254]
730 /* setmem /32 0x1400025c = 0x000d9f01 */
732 str r1, [r0, #0x025c]
735 /* setmem /32 0x14000000 = 0x00000101 // bit[0]: start */
738 /* poll to make sure it is done */
747 * The following is to fill in those arguments for this ROM function
748 * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
750 * This function is used to copy data from the storage media into DDR.
752 * start - Initial (possibly partial) image load address on entry.
753 * Final image load address on exit.
754 * bytes - Initial (possibly partial) image size on entry.
755 * Final image size on exit.
756 * boot_data - Initial @ref ivt Boot Data load address.
758 adr r0, DDR_DEST_ADDR
762 before_calling_rom___pu_irom_hwcnfg_setup:
765 blx r4 // This address might change in future ROM versions
766 after_calling_rom___pu_irom_hwcnfg_setup:
769 /* To return to ROM from plugin, we need to fill in these argument.
770 * Here is what need to do:
771 * Need to construct the paramters for this function before return to ROM:
772 * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
775 ldr r3, DDR_DEST_ADDR
779 mov r3, #0x400 /* Point to the second IVT table at offset 0x42C */
783 bx lr /* return back to ROM code */
785 DDR_DEST_ADDR: .word 0x77800000
786 COPY_SIZE: .word 0x40000
787 BOOT_DATA: .word 0x77800000
788 .word 0x40000 /*data be copied by pu_irom_hwcnfg_setup()*/