board/freescale/mx50_arm2/mx50_arm2.c

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/mx50.h>
  28 #include <asm/arch/mx50_pins.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31
  32 #ifdef CONFIG_IMX_CSPI
  33 #include <imx_spi.h>
  34 #include <asm/arch/imx_spi_pmic.h>
  35 #endif
  36
  37 #if CONFIG_I2C_MXC
  38 #include <i2c.h>
  39 #endif
  40
  41 #ifdef CONFIG_CMD_MMC
  42 #include <mmc.h>
  43 #include <fsl_esdhc.h>
  44 #endif
  45
  46 #ifdef CONFIG_ARCH_MMU
  47 #include <asm/mmu.h>
  48 #include <asm/arch/mmu.h>
  49 #endif
  50
  51 #ifdef CONFIG_CMD_CLOCK
  52 #include <asm/clock.h>
  53 #endif
  54
  55 #ifdef CONFIG_MXC_EPDC
  56 #include <lcd.h>
  57 #endif
  58
  59 DECLARE_GLOBAL_DATA_PTR;
  60
  61 static u32 system_rev;
  62 static enum boot_device boot_dev;
  63 u32     mx51_io_base_addr;
  64
  65 static inline void setup_boot_device(void)
  66 {
  67         uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
  68         uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
  69         uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
  70
  71         switch (bt_mem_ctl) {
  72         case 0x0:
  73                 if (bt_mem_type)
  74                         boot_dev = ONE_NAND_BOOT;
  75                 else
  76                         boot_dev = WEIM_NOR_BOOT;
  77                 break;
  78         case 0x2:
  79                 if (bt_mem_type)
  80                         boot_dev = SATA_BOOT;
  81                 else
  82                         boot_dev = PATA_BOOT;
  83                 break;
  84         case 0x3:
  85                 if (bt_mem_type)
  86                         boot_dev = SPI_NOR_BOOT;
  87                 else
  88                         boot_dev = I2C_BOOT;
  89                 break;
  90         case 0x4:
  91         case 0x5:
  92                 boot_dev = SD_BOOT;
  93                 break;
  94         case 0x6:
  95         case 0x7:
  96                 boot_dev = MMC_BOOT;
  97                 break;
  98         case 0x8 ... 0xf:
  99                 boot_dev = NAND_BOOT;
 100                 break;
 101         default:
 102                 boot_dev = UNKNOWN_BOOT;
 103                 break;
 104         }
 105 }
 106
 107 enum boot_device get_boot_device(void)
 108 {
 109         return boot_dev;
 110 }
 111
 112 u32 get_board_rev(void)
 113 {
 114         return system_rev;
 115 }
 116
 117 static inline void setup_soc_rev(void)
 118 {
 119         system_rev = 0x50000 | CHIP_REV_1_0;
 120 }
 121
 122 static inline void setup_board_rev(int rev)
 123 {
 124         system_rev |= (rev & 0xF) << 8;
 125 }
 126
 127 inline int is_soc_rev(int rev)
 128 {
 129         return (system_rev & 0xFF) - rev;
 130 }
 131
 132 #ifdef CONFIG_ARCH_MMU
 133 void board_mmu_init(void)
 134 {
 135         unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
 136         unsigned long i;
 137
 138         /*
 139         * Set the TTB register
 140         */
 141         asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
 142
 143         /*
 144         * Set the Domain Access Control Register
 145         */
 146         i = ARM_ACCESS_DACR_DEFAULT;
 147         asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
 148
 149         /*
 150         * First clear all TT entries - ie Set them to Faulting
 151         */
 152         memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
 153         /* Actual   Virtual  Size   Attributes          Function */
 154         /* Base     Base     MB     cached? buffered?  access permissions */
 155         /* xxx00000 xxx00000 */
 156         X_ARM_MMU_SECTION(0x000, 0x000, 0x10,
 157                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 158                         ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */
 159         X_ARM_MMU_SECTION(0x070, 0x070, 0x010,
 160                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 161                         ARM_ACCESS_PERM_RW_RW); /* IRAM */
 162         X_ARM_MMU_SECTION(0x100, 0x100, 0x040,
 163                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 164                         ARM_ACCESS_PERM_RW_RW); /* SATA */
 165         X_ARM_MMU_SECTION(0x180, 0x180, 0x100,
 166                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 167                         ARM_ACCESS_PERM_RW_RW); /* IPUv3M */
 168         X_ARM_MMU_SECTION(0x200, 0x200, 0x200,
 169                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 170                         ARM_ACCESS_PERM_RW_RW); /* GPU */
 171         X_ARM_MMU_SECTION(0x400, 0x400, 0x300,
 172                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 173                         ARM_ACCESS_PERM_RW_RW); /* periperals */
 174         X_ARM_MMU_SECTION(0x700, 0x700, 0x400,
 175                         ARM_CACHEABLE, ARM_BUFFERABLE,
 176                         ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
 177         X_ARM_MMU_SECTION(0x700, 0xB00, 0x400,
 178                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 179                         ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
 180         X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100,
 181                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 182                         ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
 183         X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001,
 184                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 185                         ARM_ACCESS_PERM_RW_RW); /* iRam */
 186
 187         /* Workaround for arm errata #709718 */
 188         /* Setup PRRR so device is always mapped to non-shared */
 189         asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
 190         i &= (~(3 << 0x10));
 191         asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
 192
 193         /* Enable MMU */
 194         MMU_ON();
 195 }
 196 #endif
 197
 198 int dram_init(void)
 199 {
 200         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 201         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 202         return 0;
 203 }
 204
 205 static void setup_uart(void)
 206 {
 207
 208         /* UART1 RXD */
 209         mxc_request_iomux(MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
 210         mxc_iomux_set_pad(MX50_PIN_UART1_RXD, 0x1E4);
 211         mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
 212
 213         /* UART1 TXD */
 214         mxc_request_iomux(MX50_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
 215         mxc_iomux_set_pad(MX50_PIN_UART1_TXD, 0x1E4);
 216 }
 217
 218 #ifdef CONFIG_I2C_MXC
 219 static void setup_i2c(unsigned int module_base)
 220 {
 221         switch (module_base) {
 222         case I2C1_BASE_ADDR:
 223                 /* i2c1 SDA */
 224                 mxc_request_iomux(MX50_PIN_I2C1_SDA,
 225                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 226                 mxc_iomux_set_pad(MX50_PIN_I2C1_SDA, PAD_CTL_SRE_FAST |
 227                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 228                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 229                                 PAD_CTL_HYS_ENABLE);
 230                 /* i2c1 SCL */
 231                 mxc_request_iomux(MX50_PIN_I2C1_SCL,
 232                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 233                 mxc_iomux_set_pad(MX50_PIN_I2C1_SCL, PAD_CTL_SRE_FAST |
 234                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 235                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 236                                 PAD_CTL_HYS_ENABLE);
 237                 break;
 238         case I2C2_BASE_ADDR:
 239                 /* i2c2 SDA */
 240                 mxc_request_iomux(MX50_PIN_I2C2_SDA,
 241                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 242                 mxc_iomux_set_pad(MX50_PIN_I2C2_SDA,
 243                                 PAD_CTL_SRE_FAST |
 244                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 245                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 246                                 PAD_CTL_HYS_ENABLE);
 247
 248                 /* i2c2 SCL */
 249                 mxc_request_iomux(MX50_PIN_I2C2_SCL,
 250                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 251                 mxc_iomux_set_pad(MX50_PIN_I2C2_SCL,
 252                                 PAD_CTL_SRE_FAST |
 253                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 254                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 255                                 PAD_CTL_HYS_ENABLE);
 256                 break;
 257         case I2C3_BASE_ADDR:
 258                 /* i2c3 SDA */
 259                 mxc_request_iomux(MX50_PIN_I2C3_SDA,
 260                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 261                 mxc_iomux_set_pad(MX50_PIN_I2C3_SDA,
 262                                 PAD_CTL_SRE_FAST |
 263                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 264                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 265                                 PAD_CTL_HYS_ENABLE);
 266
 267                 /* i2c3 SCL */
 268                 mxc_request_iomux(MX50_PIN_I2C3_SCL,
 269                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 270                 mxc_iomux_set_pad(MX50_PIN_I2C3_SCL,
 271                                 PAD_CTL_SRE_FAST |
 272                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 273                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 274                                 PAD_CTL_HYS_ENABLE);
 275                 break;
 276         default:
 277                 printf("Invalid I2C base: 0x%x\n", module_base);
 278                 break;
 279         }
 280 }
 281
 282 #endif
 283
 284 #ifdef CONFIG_IMX_CSPI
 285 s32 spi_get_cfg(struct imx_spi_dev_t *dev)
 286 {
 287         switch (dev->slave.cs) {
 288         case 0:
 289                 /* PMIC */
 290                 dev->base = CSPI3_BASE_ADDR;
 291                 dev->freq = 25000000;
 292                 dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
 293                 dev->ss = 0;
 294                 dev->fifo_sz = 32;
 295                 dev->us_delay = 0;
 296                 break;
 297         case 1:
 298                 /* SPI-NOR */
 299                 dev->base = CSPI3_BASE_ADDR;
 300                 dev->freq = 25000000;
 301                 dev->ss_pol = IMX_SPI_ACTIVE_LOW;
 302                 dev->ss = 1;
 303                 dev->fifo_sz = 32;
 304                 dev->us_delay = 0;
 305                 break;
 306         default:
 307                 printf("Invalid Bus ID! \n");
 308         }
 309
 310         return 0;
 311 }
 312
 313 void spi_io_init(struct imx_spi_dev_t *dev)
 314 {
 315         switch (dev->base) {
 316         case CSPI3_BASE_ADDR:
 317                 mxc_request_iomux(MX50_PIN_CSPI_MOSI, IOMUX_CONFIG_ALT0);
 318                 mxc_iomux_set_pad(MX50_PIN_CSPI_MOSI, 0x4);
 319
 320                 mxc_request_iomux(MX50_PIN_CSPI_MISO, IOMUX_CONFIG_ALT0);
 321                 mxc_iomux_set_pad(MX50_PIN_CSPI_MISO, 0x4);
 322
 323                 if (dev->ss == 0) {
 324                         /* de-select SS1 of instance: cspi */
 325                         mxc_request_iomux(MX50_PIN_ECSPI1_MOSI,
 326                                                 IOMUX_CONFIG_ALT1);
 327
 328                         mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0);
 329                         mxc_iomux_set_pad(MX50_PIN_CSPI_SS0, 0xE4);
 330                 } else if (dev->ss == 1) {
 331                         /* de-select SS0 of instance: cspi */
 332                         mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT1);
 333
 334                         mxc_request_iomux(MX50_PIN_ECSPI1_MOSI,
 335                                                 IOMUX_CONFIG_ALT2);
 336                         mxc_iomux_set_pad(MX50_PIN_ECSPI1_MOSI, 0xE4);
 337                         mxc_iomux_set_input(
 338                         MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT, 0x1);
 339                 }
 340
 341                 mxc_request_iomux(MX50_PIN_CSPI_SCLK, IOMUX_CONFIG_ALT0);
 342                 mxc_iomux_set_pad(MX50_PIN_CSPI_SCLK, 0x4);
 343                 break;
 344         case CSPI2_BASE_ADDR:
 345         case CSPI1_BASE_ADDR:
 346                 /* ecspi1-2 fall through */
 347                 break;
 348         default:
 349                 break;
 350         }
 351 }
 352 #endif
 353
 354 #ifdef CONFIG_MXC_FEC
 355
 356 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
 357
 358 #define HW_OCOTP_MACn(n)        (0x00000250 + (n) * 0x10)
 359
 360 int fec_get_mac_addr(unsigned char *mac)
 361 {
 362         u32 *ocotp_mac_base =
 363                 (u32 *)(OCOTP_CTRL_BASE_ADDR + HW_OCOTP_MACn(0));
 364         int i;
 365
 366         for (i = 0; i < 6; ++i, ++ocotp_mac_base)
 367                 mac[6 - 1 - i] = readl(++ocotp_mac_base);
 368
 369         return 0;
 370 }
 371 #endif
 372
 373 static void setup_fec(void)
 374 {
 375         volatile unsigned int reg;
 376
 377         /*FEC_MDIO*/
 378         mxc_request_iomux(MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6);
 379         mxc_iomux_set_pad(MX50_PIN_SSI_RXC, 0xC);
 380         mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 381
 382         /*FEC_MDC*/
 383         mxc_request_iomux(MX50_PIN_SSI_RXFS, IOMUX_CONFIG_ALT6);
 384         mxc_iomux_set_pad(MX50_PIN_SSI_RXFS, 0x004);
 385
 386         /* FEC RXD1 */
 387         mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2);
 388         mxc_iomux_set_pad(MX50_PIN_DISP_D3, 0x0);
 389         mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, 0x0);
 390
 391         /* FEC RXD0 */
 392         mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2);
 393         mxc_iomux_set_pad(MX50_PIN_DISP_D4, 0x0);
 394         mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, 0x0);
 395
 396          /* FEC TXD1 */
 397         mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2);
 398         mxc_iomux_set_pad(MX50_PIN_DISP_D6, 0x004);
 399
 400         /* FEC TXD0 */
 401         mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2);
 402         mxc_iomux_set_pad(MX50_PIN_DISP_D7, 0x004);
 403
 404         /* FEC TX_EN */
 405         mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2);
 406         mxc_iomux_set_pad(MX50_PIN_DISP_D5, 0x004);
 407
 408         /* FEC TX_CLK */
 409         mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2);
 410         mxc_iomux_set_pad(MX50_PIN_DISP_D0, 0x0);
 411         mxc_iomux_set_input(MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, 0x0);
 412
 413         /* FEC RX_ER */
 414         mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2);
 415         mxc_iomux_set_pad(MX50_PIN_DISP_D1, 0x0);
 416         mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, 0);
 417
 418         /* FEC CRS */
 419         mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2);
 420         mxc_iomux_set_pad(MX50_PIN_DISP_D2, 0x0);
 421         mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, 0);
 422
 423         /* phy reset: gpio4-6 */
 424         mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT1);
 425
 426         reg = readl(GPIO4_BASE_ADDR + 0x0);
 427         reg &= ~0x40;
 428         writel(reg, GPIO4_BASE_ADDR + 0x0);
 429
 430         reg = readl(GPIO4_BASE_ADDR + 0x4);
 431         reg |= 0x40;
 432         writel(reg, GPIO4_BASE_ADDR + 0x4);
 433
 434         udelay(500);
 435
 436         reg = readl(GPIO4_BASE_ADDR + 0x0);
 437         reg |= 0x40;
 438         writel(reg, GPIO4_BASE_ADDR + 0x0);
 439 }
 440 #endif
 441
 442 #ifdef CONFIG_CMD_MMC
 443
 444 struct fsl_esdhc_cfg esdhc_cfg[3] = {
 445         {MMC_SDHC1_BASE_ADDR, 1, 1},
 446         {MMC_SDHC2_BASE_ADDR, 1, 1},
 447         {MMC_SDHC3_BASE_ADDR, 1, 1},
 448 };
 449
 450
 451 #ifdef CONFIG_DYNAMIC_MMC_DEVNO
 452 int get_mmc_env_devno()
 453 {
 454         uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
 455         int mmc_devno = 0;
 456
 457         switch (soc_sbmr & 0x00300000) {
 458         default:
 459         case 0x0:
 460                 mmc_devno = 0;
 461                 break;
 462         case 0x00100000:
 463                 mmc_devno = 1;
 464                 break;
 465         case 0x00200000:
 466                 mmc_devno = 2;
 467                 break;
 468         }
 469
 470         return mmc_devno;
 471 }
 472 #endif
 473
 474
 475 int esdhc_gpio_init(bd_t *bis)
 476 {
 477         s32 status = 0;
 478         u32 index = 0;
 479
 480         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 481                 ++index) {
 482                 switch (index) {
 483                 case 0:
 484                         mxc_request_iomux(MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 485                         mxc_request_iomux(MX50_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 486                         mxc_request_iomux(MX50_PIN_SD1_D0,  IOMUX_CONFIG_ALT0);
 487                         mxc_request_iomux(MX50_PIN_SD1_D1,  IOMUX_CONFIG_ALT0);
 488                         mxc_request_iomux(MX50_PIN_SD1_D2,  IOMUX_CONFIG_ALT0);
 489                         mxc_request_iomux(MX50_PIN_SD1_D3,  IOMUX_CONFIG_ALT0);
 490
 491                         mxc_iomux_set_pad(MX50_PIN_SD1_CMD, 0x1E4);
 492                         mxc_iomux_set_pad(MX50_PIN_SD1_CLK, 0xD4);
 493                         mxc_iomux_set_pad(MX50_PIN_SD1_D0,  0x1D4);
 494                         mxc_iomux_set_pad(MX50_PIN_SD1_D1,  0x1D4);
 495                         mxc_iomux_set_pad(MX50_PIN_SD1_D2,  0x1D4);
 496                         mxc_iomux_set_pad(MX50_PIN_SD1_D3,  0x1D4);
 497
 498                         break;
 499                 case 1:
 500                         mxc_request_iomux(MX50_PIN_SD2_CMD, IOMUX_CONFIG_ALT0);
 501                         mxc_request_iomux(MX50_PIN_SD2_CLK, IOMUX_CONFIG_ALT0);
 502                         mxc_request_iomux(MX50_PIN_SD2_D0,  IOMUX_CONFIG_ALT0);
 503                         mxc_request_iomux(MX50_PIN_SD2_D1,  IOMUX_CONFIG_ALT0);
 504                         mxc_request_iomux(MX50_PIN_SD2_D2,  IOMUX_CONFIG_ALT0);
 505                         mxc_request_iomux(MX50_PIN_SD2_D3,  IOMUX_CONFIG_ALT0);
 506                         mxc_request_iomux(MX50_PIN_SD2_D4,  IOMUX_CONFIG_ALT0);
 507                         mxc_request_iomux(MX50_PIN_SD2_D5,  IOMUX_CONFIG_ALT0);
 508                         mxc_request_iomux(MX50_PIN_SD2_D6,  IOMUX_CONFIG_ALT0);
 509                         mxc_request_iomux(MX50_PIN_SD2_D7,  IOMUX_CONFIG_ALT0);
 510
 511                         mxc_iomux_set_pad(MX50_PIN_SD2_CMD, 0x14);
 512                         mxc_iomux_set_pad(MX50_PIN_SD2_CLK, 0xD4);
 513                         mxc_iomux_set_pad(MX50_PIN_SD2_D0,  0x1D4);
 514                         mxc_iomux_set_pad(MX50_PIN_SD2_D1,  0x1D4);
 515                         mxc_iomux_set_pad(MX50_PIN_SD2_D2,  0x1D4);
 516                         mxc_iomux_set_pad(MX50_PIN_SD2_D3,  0x1D4);
 517                         mxc_iomux_set_pad(MX50_PIN_SD2_D4,  0x1D4);
 518                         mxc_iomux_set_pad(MX50_PIN_SD2_D5,  0x1D4);
 519                         mxc_iomux_set_pad(MX50_PIN_SD2_D6,  0x1D4);
 520                         mxc_iomux_set_pad(MX50_PIN_SD2_D7,  0x1D4);
 521
 522                         break;
 523                 case 2:
 524                         mxc_request_iomux(MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0);
 525                         mxc_request_iomux(MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0);
 526                         mxc_request_iomux(MX50_PIN_SD3_D0,  IOMUX_CONFIG_ALT0);
 527                         mxc_request_iomux(MX50_PIN_SD3_D1,  IOMUX_CONFIG_ALT0);
 528                         mxc_request_iomux(MX50_PIN_SD3_D2,  IOMUX_CONFIG_ALT0);
 529                         mxc_request_iomux(MX50_PIN_SD3_D3,  IOMUX_CONFIG_ALT0);
 530                         mxc_request_iomux(MX50_PIN_SD3_D4,  IOMUX_CONFIG_ALT0);
 531                         mxc_request_iomux(MX50_PIN_SD3_D5,  IOMUX_CONFIG_ALT0);
 532                         mxc_request_iomux(MX50_PIN_SD3_D6,  IOMUX_CONFIG_ALT0);
 533                         mxc_request_iomux(MX50_PIN_SD3_D7,  IOMUX_CONFIG_ALT0);
 534
 535                         mxc_iomux_set_pad(MX50_PIN_SD3_CMD, 0x1E4);
 536                         mxc_iomux_set_pad(MX50_PIN_SD3_CLK, 0xD4);
 537                         mxc_iomux_set_pad(MX50_PIN_SD3_D0,  0x1D4);
 538                         mxc_iomux_set_pad(MX50_PIN_SD3_D1,  0x1D4);
 539                         mxc_iomux_set_pad(MX50_PIN_SD3_D2,  0x1D4);
 540                         mxc_iomux_set_pad(MX50_PIN_SD3_D3,  0x1D4);
 541                         mxc_iomux_set_pad(MX50_PIN_SD3_D4,  0x1D4);
 542                         mxc_iomux_set_pad(MX50_PIN_SD3_D5,  0x1D4);
 543                         mxc_iomux_set_pad(MX50_PIN_SD3_D6,  0x1D4);
 544                         mxc_iomux_set_pad(MX50_PIN_SD3_D7,  0x1D4);
 545
 546                         break;
 547                 default:
 548                         printf("Warning: you configured more ESDHC controller"
 549                                 "(%d) as supported by the board(2)\n",
 550                                 CONFIG_SYS_FSL_ESDHC_NUM);
 551                         return status;
 552                         break;
 553                 }
 554                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 555         }
 556
 557         return status;
 558 }
 559
 560 int board_mmc_init(bd_t *bis)
 561 {
 562         if (!esdhc_gpio_init(bis))
 563                 return 0;
 564         else
 565                 return -1;
 566 }
 567
 568 #endif
 569
 570 #ifdef CONFIG_MXC_EPDC
 571 #ifdef CONFIG_SPLASH_SCREEN
 572 int setup_splash_img()
 573 {
 574 #ifdef CONFIG_SPLASH_IS_IN_MMC
 575         int mmc_dev = get_mmc_env_devno();
 576         ulong offset = CONFIG_SPLASH_IMG_OFFSET;
 577         ulong size = CONFIG_SPLASH_IMG_SIZE;
 578         ulong addr = 0;
 579         char *s = NULL;
 580         struct mmc *mmc = find_mmc_device(mmc_dev);
 581         uint blk_start, blk_cnt, n;
 582
 583         s = getenv("splashimage");
 584
 585         if (NULL == s) {
 586                 puts("env splashimage not found!\n");
 587                 return -1;
 588         }
 589         addr = simple_strtoul(s, NULL, 16);
 590
 591         if (!mmc) {
 592                 printf("MMC Device %d not found\n",
 593                         mmc_dev);
 594                 return -1;
 595         }
 596
 597         if (mmc_init(mmc)) {
 598                 puts("MMC init failed\n");
 599                 return  -1;
 600         }
 601
 602         blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
 603         blk_cnt   = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
 604         n = mmc->block_dev.block_read(mmc_dev, blk_start,
 605                                         blk_cnt, (u_char *)addr);
 606         flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
 607
 608         return (n == blk_cnt) ? 0 : -1;
 609 #endif
 610 }
 611 #endif
 612
 613 vidinfo_t panel_info = {
 614         .vl_refresh = 60,
 615         .vl_col = 800,
 616         .vl_row = 600,
 617         .vl_pixclock = 17700000,
 618         .vl_left_margin = 8,
 619         .vl_right_margin = 142,
 620         .vl_upper_margin = 4,
 621         .vl_lower_margin = 10,
 622         .vl_hsync = 20,
 623         .vl_vsync = 4,
 624         .vl_sync = 0,
 625         .vl_mode = 0,
 626         .vl_flag = 0,
 627         .vl_bpix = 3,
 628         cmap:0,
 629 };
 630
 631 static void setup_epdc_power()
 632 {
 633         unsigned int reg;
 634
 635         /* Setup epdc voltage */
 636
 637         /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
 638         mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
 639
 640         /* EPDC VCOM0 - GPIO4[21] for VCOM control */
 641         mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
 642         /* Set as output */
 643         reg = readl(GPIO4_BASE_ADDR + 0x4);
 644         reg |= (1 << 21);
 645         writel(reg, GPIO4_BASE_ADDR + 0x4);
 646
 647         /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
 648         mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
 649         /* Set as output */
 650         reg = readl(GPIO6_BASE_ADDR + 0x4);
 651         reg |= (1 << 16);
 652         writel(reg, GPIO6_BASE_ADDR + 0x4);
 653 }
 654
 655 void epdc_power_on()
 656 {
 657         unsigned int reg;
 658
 659         /* Set PMIC Wakeup to high - enable Display power */
 660         reg = readl(GPIO6_BASE_ADDR + 0x0);
 661         reg |= (1 << 16);
 662         writel(reg, GPIO6_BASE_ADDR + 0x0);
 663
 664         /* Wait for PWRGOOD == 1 */
 665         while (1) {
 666                 reg = readl(GPIO3_BASE_ADDR + 0x0);
 667                 if (!(reg & (1 << 28)))
 668                         break;
 669
 670                 udelay(100);
 671         }
 672
 673         /* Enable VCOM */
 674         reg = readl(GPIO4_BASE_ADDR + 0x0);
 675         reg |= (1 << 21);
 676         writel(reg, GPIO4_BASE_ADDR + 0x0);
 677
 678         reg = readl(GPIO4_BASE_ADDR + 0x0);
 679
 680         udelay(500);
 681 }
 682
 683 void  epdc_power_off()
 684 {
 685         unsigned int reg;
 686         /* Set PMIC Wakeup to low - disable Display power */
 687         reg = readl(GPIO6_BASE_ADDR + 0x0);
 688         reg |= 0 << 16;
 689         writel(reg, GPIO6_BASE_ADDR + 0x0);
 690
 691         /* Disable VCOM */
 692         reg = readl(GPIO4_BASE_ADDR + 0x0);
 693         reg |= 0 << 21;
 694         writel(reg, GPIO4_BASE_ADDR + 0x0);
 695 }
 696
 697 int setup_waveform_file()
 698 {
 699 #ifdef CONFIG_WAVEFORM_FILE_IN_MMC
 700         int mmc_dev = get_mmc_env_devno();
 701         ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
 702         ulong size = CONFIG_WAVEFORM_FILE_SIZE;
 703         ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
 704         char *s = NULL;
 705         struct mmc *mmc = find_mmc_device(mmc_dev);
 706         uint blk_start, blk_cnt, n;
 707
 708         if (!mmc) {
 709                 printf("MMC Device %d not found\n",
 710                         mmc_dev);
 711                 return -1;
 712         }
 713
 714         if (mmc_init(mmc)) {
 715                 puts("MMC init failed\n");
 716                 return -1;
 717         }
 718
 719         blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
 720         blk_cnt   = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
 721         n = mmc->block_dev.block_read(mmc_dev, blk_start,
 722                 blk_cnt, (u_char *)addr);
 723         flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
 724
 725         return (n == blk_cnt) ? 0 : -1;
 726 #else
 727         return -1;
 728 #endif
 729 }
 730
 731 static void setup_epdc()
 732 {
 733         unsigned int reg;
 734
 735         /* epdc iomux settings */
 736         mxc_request_iomux(MX50_PIN_EPDC_D0, IOMUX_CONFIG_ALT0);
 737         mxc_request_iomux(MX50_PIN_EPDC_D1, IOMUX_CONFIG_ALT0);
 738         mxc_request_iomux(MX50_PIN_EPDC_D2, IOMUX_CONFIG_ALT0);
 739         mxc_request_iomux(MX50_PIN_EPDC_D3, IOMUX_CONFIG_ALT0);
 740         mxc_request_iomux(MX50_PIN_EPDC_D4, IOMUX_CONFIG_ALT0);
 741         mxc_request_iomux(MX50_PIN_EPDC_D5, IOMUX_CONFIG_ALT0);
 742         mxc_request_iomux(MX50_PIN_EPDC_D6, IOMUX_CONFIG_ALT0);
 743         mxc_request_iomux(MX50_PIN_EPDC_D7, IOMUX_CONFIG_ALT0);
 744         mxc_request_iomux(MX50_PIN_EPDC_GDCLK, IOMUX_CONFIG_ALT0);
 745         mxc_request_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0);
 746         mxc_request_iomux(MX50_PIN_EPDC_GDOE, IOMUX_CONFIG_ALT0);
 747         mxc_request_iomux(MX50_PIN_EPDC_GDRL, IOMUX_CONFIG_ALT0);
 748         mxc_request_iomux(MX50_PIN_EPDC_SDCLK, IOMUX_CONFIG_ALT0);
 749         mxc_request_iomux(MX50_PIN_EPDC_SDOE, IOMUX_CONFIG_ALT0);
 750         mxc_request_iomux(MX50_PIN_EPDC_SDLE, IOMUX_CONFIG_ALT0);
 751         mxc_request_iomux(MX50_PIN_EPDC_SDSHR, IOMUX_CONFIG_ALT0);
 752         mxc_request_iomux(MX50_PIN_EPDC_BDR0, IOMUX_CONFIG_ALT0);
 753         mxc_request_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0);
 754         mxc_request_iomux(MX50_PIN_EPDC_SDCE1, IOMUX_CONFIG_ALT0);
 755         mxc_request_iomux(MX50_PIN_EPDC_SDCE2, IOMUX_CONFIG_ALT0);
 756
 757
 758         /*** epdc Maxim PMIC settings ***/
 759
 760         /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
 761         mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
 762
 763         /* EPDC VCOM0 - GPIO4[21] for VCOM control */
 764         mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
 765
 766         /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
 767         mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
 768
 769
 770         /*** Set pixel clock rates for EPDC ***/
 771
 772         /* EPDC AXI clk and EPDC PIX clk from PLL1 */
 773         reg = readl(CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
 774         reg &= ~(0x3 << 4);
 775         reg |= (0x2 << 4) | (0x2 << 12);
 776         writel(reg, CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
 777
 778         /* EPDC AXI clk enable and set to 200MHz (800/4) */
 779         reg = readl(CCM_BASE_ADDR + 0xA8);
 780         reg &= ~((0x3 << 30) | 0x3F);
 781         reg |= (0x2 << 30) | 0x4;
 782         writel(reg, CCM_BASE_ADDR + 0xA8);
 783
 784         /* EPDC PIX clk enable and set to 20MHz (800/40) */
 785         reg = readl(CCM_BASE_ADDR + 0xA0);
 786         reg &= ~((0x3 << 30) | (0x3 << 12) | 0x3F);
 787         reg |= (0x2 << 30) | (0x1 << 12) | 0x2D;
 788         writel(reg, CCM_BASE_ADDR + 0xA0);
 789
 790         panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;
 791         panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;
 792
 793         panel_info.epdc_data.wv_modes.mode_init = 0;
 794         panel_info.epdc_data.wv_modes.mode_du = 1;
 795         panel_info.epdc_data.wv_modes.mode_gc4 = 3;
 796         panel_info.epdc_data.wv_modes.mode_gc8 = 2;
 797         panel_info.epdc_data.wv_modes.mode_gc16 = 2;
 798         panel_info.epdc_data.wv_modes.mode_gc32 = 2;
 799
 800         setup_epdc_power();
 801
 802         /* Assign fb_base */
 803         gd->fb_base = CONFIG_FB_BASE;
 804 }
 805 #endif
 806
 807 #ifdef CONFIG_IMX_CSPI
 808 static void setup_power(void)
 809 {
 810         struct spi_slave *slave;
 811         unsigned int val;
 812         unsigned int reg;
 813
 814         puts("PMIC Mode: SPI\n");
 815
 816         /* Enable VGEN1 to enable ethernet */
 817         slave = spi_pmic_probe();
 818
 819         val = pmic_reg(slave, 30, 0, 0);
 820         val |= 0x3;
 821         pmic_reg(slave, 30, val, 1);
 822
 823         val = pmic_reg(slave, 32, 0, 0);
 824         val |= 0x1;
 825         pmic_reg(slave, 32, val, 1);
 826
 827         /* Enable VCAM   */
 828         val = pmic_reg(slave, 33, 0, 0);
 829         val |= 0x40;
 830         pmic_reg(slave, 33, val, 1);
 831
 832         spi_pmic_free(slave);
 833 }
 834
 835 void setup_voltage_cpu(void)
 836 {
 837         /* Currently VDDGP 1.05v
 838          * no one tell me we need increase the core
 839          * voltage to let CPU run at 800Mhz, not do it
 840          */
 841
 842         /* Raise the core frequency to 800MHz */
 843         writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
 844
 845 }
 846 #endif
 847
 848 int board_init(void)
 849 {
 850 #ifdef CONFIG_MFG
 851 /* MFG firmware need reset usb to avoid host crash firstly */
 852 #define USBCMD 0x140
 853         int val = readl(OTG_BASE_ADDR + USBCMD);
 854         val &= ~0x1; /*RS bit*/
 855         writel(val, OTG_BASE_ADDR + USBCMD);
 856 #endif
 857         /* boot device */
 858         setup_boot_device();
 859
 860         /* soc rev */
 861         setup_soc_rev();
 862
 863         /* arch id for linux */
 864         gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2;
 865
 866         /* boot parameters */
 867         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 868
 869         /* iomux for uart */
 870         setup_uart();
 871
 872 #ifdef CONFIG_MXC_FEC
 873         /* iomux for fec */
 874         setup_fec();
 875 #endif
 876
 877 #ifdef CONFIG_MXC_EPDC
 878         setup_epdc();
 879 #endif
 880
 881         return 0;
 882 }
 883
 884 int board_late_init(void)
 885 {
 886 #ifdef CONFIG_IMX_CSPI
 887         setup_power();
 888 #endif
 889         return 0;
 890 }
 891
 892 int checkboard(void)
 893 {
 894         printf("Board: MX50 ARM2 board\n");
 895
 896         printf("Boot Reason: [");
 897
 898         switch (__REG(SRC_BASE_ADDR + 0x8)) {
 899         case 0x0001:
 900                 printf("POR");
 901                 break;
 902         case 0x0009:
 903                 printf("RST");
 904                 break;
 905         case 0x0010:
 906         case 0x0011:
 907                 printf("WDOG");
 908                 break;
 909         default:
 910                 printf("unknown");
 911         }
 912         printf("]\n");
 913
 914         printf("Boot Device: ");
 915         switch (get_boot_device()) {
 916         case WEIM_NOR_BOOT:
 917                 printf("NOR\n");
 918                 break;
 919         case ONE_NAND_BOOT:
 920                 printf("ONE NAND\n");
 921                 break;
 922         case PATA_BOOT:
 923                 printf("PATA\n");
 924                 break;
 925         case SATA_BOOT:
 926                 printf("SATA\n");
 927                 break;
 928         case I2C_BOOT:
 929                 printf("I2C\n");
 930                 break;
 931         case SPI_NOR_BOOT:
 932                 printf("SPI NOR\n");
 933                 break;
 934         case SD_BOOT:
 935                 printf("SD\n");
 936                 break;
 937         case MMC_BOOT:
 938                 printf("MMC\n");
 939                 break;
 940         case NAND_BOOT:
 941                 printf("NAND\n");
 942                 break;
 943         case UNKNOWN_BOOT:
 944         default:
 945                 printf("UNKNOWN\n");
 946                 break;
 947         }
 948
 949         return 0;
 950 }