board/freescale/mx51_bbg/mx51_bbg.c

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/mx51.h>
  28 #include <asm/arch/mx51_pins.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <i2c.h>
  32 #include <asm/arch/keypad.h>
  33 #include "board-imx51.h"
  34 #ifdef CONFIG_IMX_ECSPI
  35 #include <imx_spi.h>
  36 #include <asm/arch/imx_spi_pmic.h>
  37 #endif
  38
  39 #include <asm/errno.h>
  40
  41 #ifdef CONFIG_CMD_MMC
  42 #include <mmc.h>
  43 #include <fsl_esdhc.h>
  44 #endif
  45
  46 #ifdef CONFIG_ARCH_MMU
  47 #include <asm/mmu.h>
  48 #include <asm/arch/mmu.h>
  49 #endif
  50
  51 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
  52 #include <asm/imx_iim.h>
  53 #endif
  54
  55 #ifdef CONFIG_FSL_ANDROID
  56 #include <mxc_keyb.h>
  57 #include <part.h>
  58 #include <ext2fs.h>
  59 #include <linux/mtd/mtd.h>
  60 #include <linux/mtd/partitions.h>
  61 #include <ubi_uboot.h>
  62 #include <jffs2/load_kernel.h>
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 static u32 system_rev;
  68 static enum boot_device boot_dev;
  69 u32     mx51_io_base_addr;
  70
  71 static inline void setup_boot_device(void)
  72 {
  73         uint *fis_addr = (uint *)IRAM_BASE_ADDR;
  74
  75         switch (*fis_addr) {
  76         case NAND_FLASH_BOOT:
  77                 boot_dev = NAND_BOOT;
  78                 break;
  79         case SPI_NOR_FLASH_BOOT:
  80                 boot_dev = SPI_NOR_BOOT;
  81                 break;
  82         case MMC_FLASH_BOOT:
  83                 boot_dev = MMC_BOOT;
  84                 break;
  85         default:
  86                 {
  87                         uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
  88                         uint bt_mem_ctl = soc_sbmr & 0x00000003;
  89                         uint bt_mem_type = (soc_sbmr & 0x00000180) >> 7;
  90
  91                         switch (bt_mem_ctl) {
  92                         case 0x3:
  93                                 if (bt_mem_type == 0)
  94                                         boot_dev = MMC_BOOT;
  95                                 else if (bt_mem_type == 3)
  96                                         boot_dev = SPI_NOR_BOOT;
  97                                 else
  98                                         boot_dev = UNKNOWN_BOOT;
  99                                 break;
 100                         case 0x1:
 101                                 boot_dev = NAND_BOOT;
 102                                 break;
 103                         default:
 104                                 boot_dev = UNKNOWN_BOOT;
 105                         }
 106                 }
 107                 break;
 108         }
 109 }
 110
 111 enum boot_device get_boot_device(void)
 112 {
 113         return boot_dev;
 114 }
 115
 116 u32 get_board_rev(void)
 117 {
 118         return system_rev;
 119 }
 120
 121 static inline void setup_soc_rev(void)
 122 {
 123         int reg;
 124 #ifdef CONFIG_ARCH_MMU
 125         reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */
 126 #else
 127         reg = __REG(ROM_SI_REV);
 128 #endif
 129
 130         switch (reg) {
 131         case 0x02:
 132                 system_rev = 0x51000 | CHIP_REV_1_1;
 133                 break;
 134         case 0x10:
 135                 system_rev = 0x51000 | CHIP_REV_2_0;
 136                 break;
 137         case 0x20:
 138                 system_rev = 0x51000 | CHIP_REV_3_0;
 139                 break;
 140         default:
 141                 system_rev = 0x51000 | CHIP_REV_1_0;
 142         }
 143 }
 144
 145 static inline void set_board_rev(void)
 146 {
 147         if ((__REG(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
 148                 system_rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
 149
 150 }
 151
 152 inline int is_soc_rev(int rev)
 153 {
 154         return (system_rev & 0xFF) - rev;
 155 }
 156
 157 #ifdef CONFIG_ARCH_MMU
 158 void board_mmu_init(void)
 159 {
 160         unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
 161         unsigned long i;
 162
 163         /*
 164         * Set the TTB register
 165         */
 166         asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
 167
 168         /*
 169         * Set the Domain Access Control Register
 170         */
 171         i = ARM_ACCESS_DACR_DEFAULT;
 172         asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
 173
 174         /*
 175         * First clear all TT entries - ie Set them to Faulting
 176         */
 177         memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
 178         /* Actual   Virtual  Size   Attributes          Function */
 179         /* Base     Base     MB     cached? buffered?  access permissions */
 180         /* xxx00000 xxx00000 */
 181         X_ARM_MMU_SECTION(0x000, 0x200, 0x1,
 182                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 183                         ARM_ACCESS_PERM_RW_RW); /* ROM */
 184         X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001,
 185                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 186                         ARM_ACCESS_PERM_RW_RW); /* IRAM */
 187         X_ARM_MMU_SECTION(0x300, 0x300, 0x100,
 188                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 189                         ARM_ACCESS_PERM_RW_RW); /* GPU */
 190         X_ARM_MMU_SECTION(0x400, 0x400, 0x200,
 191                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 192                         ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
 193         X_ARM_MMU_SECTION(0x600, 0x600, 0x300,
 194                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 195                         ARM_ACCESS_PERM_RW_RW); /* periperals */
 196         X_ARM_MMU_SECTION(0x900, 0x000, 0x1FF,
 197                         ARM_CACHEABLE, ARM_BUFFERABLE,
 198                         ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 199         X_ARM_MMU_SECTION(0x900, 0x900, 0x200,
 200                         ARM_CACHEABLE, ARM_BUFFERABLE,
 201                         ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 202         X_ARM_MMU_SECTION(0x900, 0xE00, 0x200,
 203                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 204                         ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
 205         X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10,
 206                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 207                         ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
 208         X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
 209                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 210                         ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
 211
 212         /* Workaround for arm errata #709718 */
 213         /* Setup PRRR so device is always mapped to non-shared */
 214         asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
 215         i &= (~(3 << 0x10));
 216         asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
 217
 218         /* Enable MMU */
 219         MMU_ON();
 220 }
 221 #endif
 222
 223 int dram_init(void)
 224 {
 225         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 226         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 227         return 0;
 228 }
 229
 230 static void setup_uart(void)
 231 {
 232         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 233                          PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
 234         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
 235         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
 236         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
 237         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
 238         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
 239         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
 240         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
 241         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
 242         /* enable GPIO1_9 for CLK0 and GPIO1_8 for CLK02 */
 243         writel(0x00000004, 0x73fa83e8);
 244         writel(0x00000004, 0x73fa83ec);
 245 }
 246
 247 void setup_nfc(void)
 248 {
 249         /* Enable NFC IOMUX */
 250         mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
 251         mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
 252         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
 253         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
 254         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
 255         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
 256         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
 257         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
 258 }
 259
 260 static void setup_expio(void)
 261 {
 262         u32 reg;
 263         /* CS5 setup */
 264         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
 265         writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
 266         writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
 267         /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
 268         writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
 269         /* APR = 0 */
 270         writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
 271         /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
 272          * WCSA=0, WCSN=0
 273          */
 274         writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
 275         if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
 276             (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
 277                 if (is_soc_rev(CHIP_REV_2_0) < 0) {
 278                         reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
 279                         reg = (reg & (~0x70000)) | 0x30000;
 280                         writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
 281                         /* make sure divider effective */
 282                         while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
 283                                 ;
 284                         writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
 285                 }
 286                 mx51_io_base_addr = CS5_BASE_ADDR;
 287         } else {
 288                 /* CS1 */
 289                 writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
 290                 writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
 291                 /*  RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
 292                 writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
 293                 /* APR=0 */
 294                 writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
 295                 /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
 296                  * WEN=0, WCSA=0, WCSN=0
 297                  */
 298                 writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
 299                 mx51_io_base_addr = CS1_BASE_ADDR;
 300         }
 301
 302         /* Reset interrupt status reg */
 303         writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
 304         writew(0x00, mx51_io_base_addr + PBC_INT_REST);
 305         writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
 306
 307         /* Reset the XUART and Ethernet controllers */
 308         reg = readw(mx51_io_base_addr + PBC_SW_RESET);
 309         reg |= 0x9;
 310         writew(reg, mx51_io_base_addr + PBC_SW_RESET);
 311         reg &= ~0x9;
 312         writew(reg, mx51_io_base_addr + PBC_SW_RESET);
 313 }
 314
 315 #ifdef CONFIG_IMX_ECSPI
 316 s32 spi_get_cfg(struct imx_spi_dev_t *dev)
 317 {
 318         switch (dev->slave.cs) {
 319         case 0:
 320                 /* pmic */
 321                 dev->base = CSPI1_BASE_ADDR;
 322                 dev->freq = 2500000;
 323                 dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
 324                 dev->ss = 0;
 325                 dev->fifo_sz = 64 * 4;
 326                 dev->us_delay = 0;
 327                 break;
 328         case 1:
 329                 /* spi_nor */
 330                 dev->base = CSPI1_BASE_ADDR;
 331                 dev->freq = 2500000;
 332                 dev->ss_pol = IMX_SPI_ACTIVE_LOW;
 333                 dev->ss = 1;
 334                 dev->fifo_sz = 64 * 4;
 335                 dev->us_delay = 0;
 336                 break;
 337         default:
 338                 printf("Invalid Bus ID! \n");
 339                 break;
 340         }
 341
 342         return 0;
 343 }
 344
 345 void spi_io_init(struct imx_spi_dev_t *dev)
 346 {
 347         switch (dev->base) {
 348         case CSPI1_BASE_ADDR:
 349                 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 350                 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 351                 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
 352
 353                 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 354                 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 355                 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
 356
 357                 if (dev->ss == 0) {
 358                         /* de-select SS1 of instance: ecspi1. */
 359                         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
 360                         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
 361                         /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
 362                         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
 363                         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
 364                 } else if (dev->ss == 1) {
 365                         /* de-select SS0 of instance: ecspi1. */
 366                         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT3);
 367                         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x85);
 368                         /* 000: Select mux mode: ALT0 mux port: SS1 of instance: ecspi1. */
 369                         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0);
 370                         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x105);
 371                 }
 372
 373                 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
 374                 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
 375                 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
 376
 377                 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 378                 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 379                 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
 380                 break;
 381         case CSPI2_BASE_ADDR:
 382         default:
 383                 break;
 384         }
 385 }
 386 #endif
 387
 388 #ifdef CONFIG_MXC_FEC
 389
 390 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
 391
 392 int fec_get_mac_addr(unsigned char *mac)
 393 {
 394         u32 *iim1_mac_base =
 395                 (u32 *)(IIM_BASE_ADDR + IIM_BANK_AREA_1_OFFSET +
 396                         CONFIG_IIM_MAC_ADDR_OFFSET);
 397         int i;
 398
 399         for (i = 0; i < 6; ++i, ++iim1_mac_base)
 400                 mac[i] = (u8)readl(iim1_mac_base);
 401
 402         return 0;
 403 }
 404 #endif
 405
 406 static void setup_fec(void)
 407 {
 408         /*FEC_MDIO*/
 409         writel(0x3, IOMUXC_BASE_ADDR + 0x0D4);
 410         writel(0x1FD, IOMUXC_BASE_ADDR + 0x0468);
 411         writel(0x0, IOMUXC_BASE_ADDR + 0x0954);
 412
 413         /*FEC_MDC*/
 414         writel(0x2, IOMUXC_BASE_ADDR + 0x13C);
 415         writel(0x2004, IOMUXC_BASE_ADDR + 0x0524);
 416
 417         /* FEC RDATA[3] */
 418         writel(0x3, IOMUXC_BASE_ADDR + 0x0EC);
 419         writel(0x180, IOMUXC_BASE_ADDR + 0x0480);
 420         writel(0x0, IOMUXC_BASE_ADDR + 0x0964);
 421
 422         /* FEC RDATA[2] */
 423         writel(0x3, IOMUXC_BASE_ADDR + 0x0E8);
 424         writel(0x180, IOMUXC_BASE_ADDR + 0x047C);
 425         writel(0x0, IOMUXC_BASE_ADDR + 0x0960);
 426
 427         /* FEC RDATA[1] */
 428         writel(0x3, IOMUXC_BASE_ADDR + 0x0d8);
 429         writel(0x180, IOMUXC_BASE_ADDR + 0x046C);
 430         writel(0x0, IOMUXC_BASE_ADDR + 0x095C);
 431
 432         /* FEC RDATA[0] */
 433         writel(0x2, IOMUXC_BASE_ADDR + 0x016C);
 434         writel(0x2180, IOMUXC_BASE_ADDR + 0x0554);
 435         writel(0x0, IOMUXC_BASE_ADDR + 0x0958);
 436
 437         /* FEC TDATA[3] */
 438         writel(0x2, IOMUXC_BASE_ADDR + 0x148);
 439         writel(0x2004, IOMUXC_BASE_ADDR + 0x0530);
 440
 441         /* FEC TDATA[2] */
 442         writel(0x2, IOMUXC_BASE_ADDR + 0x144);
 443         writel(0x2004, IOMUXC_BASE_ADDR + 0x052C);
 444
 445         /* FEC TDATA[1] */
 446         writel(0x2, IOMUXC_BASE_ADDR + 0x140);
 447         writel(0x2004, IOMUXC_BASE_ADDR + 0x0528);
 448
 449         /* FEC TDATA[0] */
 450         writel(0x2, IOMUXC_BASE_ADDR + 0x0170);
 451         writel(0x2004, IOMUXC_BASE_ADDR + 0x0558);
 452
 453         /* FEC TX_EN */
 454         writel(0x1, IOMUXC_BASE_ADDR + 0x014C);
 455         writel(0x2004, IOMUXC_BASE_ADDR + 0x0534);
 456
 457         /* FEC TX_ER */
 458         writel(0x2, IOMUXC_BASE_ADDR + 0x0138);
 459         writel(0x2004, IOMUXC_BASE_ADDR + 0x0520);
 460
 461         /* FEC TX_CLK */
 462         writel(0x1, IOMUXC_BASE_ADDR + 0x0150);
 463         writel(0x2180, IOMUXC_BASE_ADDR + 0x0538);
 464         writel(0x0, IOMUXC_BASE_ADDR + 0x0974);
 465
 466         /* FEC COL */
 467         writel(0x1, IOMUXC_BASE_ADDR + 0x0124);
 468         writel(0x2180, IOMUXC_BASE_ADDR + 0x0500);
 469         writel(0x0, IOMUXC_BASE_ADDR + 0x094c);
 470
 471         /* FEC RX_CLK */
 472         writel(0x1, IOMUXC_BASE_ADDR + 0x0128);
 473         writel(0x2180, IOMUXC_BASE_ADDR + 0x0504);
 474         writel(0x0, IOMUXC_BASE_ADDR + 0x0968);
 475
 476         /* FEC CRS */
 477         writel(0x3, IOMUXC_BASE_ADDR + 0x0f4);
 478         writel(0x180, IOMUXC_BASE_ADDR + 0x0488);
 479         writel(0x0, IOMUXC_BASE_ADDR + 0x0950);
 480
 481         /* FEC RX_ER */
 482         writel(0x3, IOMUXC_BASE_ADDR + 0x0f0);
 483         writel(0x180, IOMUXC_BASE_ADDR + 0x0484);
 484         writel(0x0, IOMUXC_BASE_ADDR + 0x0970);
 485
 486         /* FEC RX_DV */
 487         writel(0x2, IOMUXC_BASE_ADDR + 0x164);
 488         writel(0x2180, IOMUXC_BASE_ADDR + 0x054C);
 489         writel(0x0, IOMUXC_BASE_ADDR + 0x096C);
 490 }
 491 #endif
 492
 493 #ifdef CONFIG_I2C_MXC
 494 static void setup_i2c(unsigned int module_base)
 495 {
 496         unsigned int reg;
 497
 498         switch (module_base) {
 499         case I2C1_BASE_ADDR:
 500                 reg = IOMUXC_BASE_ADDR + 0x5c; /* i2c1 SDA */
 501                 writel(0x14, reg);
 502                 reg = IOMUXC_BASE_ADDR + 0x3f0;
 503                 writel(0x10d, reg);
 504                 reg = IOMUXC_BASE_ADDR + 0x9B4;
 505                 writel(0x0, reg);
 506
 507                 reg = IOMUXC_BASE_ADDR + 0x68; /* i2c2 SCL */
 508                 writel(0x14, reg);
 509                 reg = IOMUXC_BASE_ADDR + 0x3fc;
 510                 writel(0x10d, reg);
 511                 reg = IOMUXC_BASE_ADDR + 0x9B0;
 512                 writel(0x0, reg);
 513                 break;
 514         case I2C2_BASE_ADDR:
 515                 /* dummy here*/
 516                 break;
 517         default:
 518                 printf("Invalid I2C base: 0x%x\n", module_base);
 519                 break;
 520         }
 521 }
 522
 523 static void setup_core_voltage_i2c(void)
 524 {
 525         unsigned int reg;
 526         unsigned char buf[1] = { 0 };
 527
 528         puts("PMIC Mode: linear\n");
 529
 530         writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
 531         reg = readl(GPIO2_BASE_ADDR + 0x0);
 532         reg &= ~0x4000;  /* Lower reset line */
 533         writel(reg, GPIO2_BASE_ADDR + 0x0);
 534
 535         reg = readl(GPIO2_BASE_ADDR + 0x4);
 536         reg |= 0x4000;  /* configure GPIO lines as output */
 537         writel(reg, GPIO2_BASE_ADDR + 0x4);
 538
 539         /* Reset the ethernet controller over GPIO */
 540         writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
 541
 542         /*Configure LDO4*/
 543         i2c_read(0x34, 0x12, 1, buf, 1);
 544         buf[0] = buf[0] | 0x40;
 545         if (i2c_write(0x34, 0x12, 1, buf, 1)) {
 546                 puts("write to PMIC 0x12 failed!\n");
 547                 return;
 548         }
 549         i2c_read(0x34, 0x12, 1, buf, 1);
 550         printf("PMIC 0x12: 0x%x \n", buf[0]);
 551
 552         i2c_read(0x34, 0x10, 1, buf, 1);
 553         buf[0] = buf[0] | 0x40;
 554         if (i2c_write(0x34, 0x10, 1, buf, 1)) {
 555                 puts("write to PMIC 0x10 failed!\n");
 556                 return;
 557         }
 558         i2c_read(0x34, 0x10, 1, buf, 1);
 559         printf("PMIC 0x10: 0x%x \n", buf[0]);
 560
 561         udelay(500);
 562
 563         reg = readl(GPIO2_BASE_ADDR + 0x0);
 564         reg |= 0x4000;
 565         writel(reg, GPIO2_BASE_ADDR + 0x0);
 566 }
 567 #endif
 568
 569 #ifdef CONFIG_IMX_ECSPI
 570 static void setup_core_voltage_spi(void)
 571 {
 572         struct spi_slave *slave;
 573         unsigned int val;
 574         unsigned int reg;
 575
 576         puts("PMIC Mode: SPI\n");
 577
 578 #define REV_ATLAS_LITE_1_0         0x8
 579 #define REV_ATLAS_LITE_1_1         0x9
 580 #define REV_ATLAS_LITE_2_0         0x10
 581 #define REV_ATLAS_LITE_2_1         0x11
 582
 583         slave = spi_pmic_probe();
 584
 585         /* Write needed to Power Gate 2 register */
 586         val = pmic_reg(slave, 34, 0, 0);
 587         val &= ~0x10000;
 588         pmic_reg(slave, 34, val, 1);
 589
 590         /* Write needed to update Charger 0 */
 591         pmic_reg(slave, 48, 0x0023807F, 1);
 592
 593         /* power up the system first */
 594         pmic_reg(slave, 34, 0x00200000, 1);
 595
 596         if (is_soc_rev(CHIP_REV_2_0) >= 0) {
 597                 /* Set core voltage to 1.1V */
 598                 val = pmic_reg(slave, 24, 0, 0);
 599                 val = (val & (~0x1F)) | 0x14;
 600                 pmic_reg(slave, 24, val, 1);
 601
 602                 /* Setup VCC (SW2) to 1.25 */
 603                 val = pmic_reg(slave, 25, 0, 0);
 604                 val = (val & (~0x1F)) | 0x1A;
 605                 pmic_reg(slave, 25, val, 1);
 606
 607                 /* Setup 1V2_DIG1 (SW3) to 1.25 */
 608                 val = pmic_reg(slave, 26, 0, 0);
 609                 val = (val & (~0x1F)) | 0x1A;
 610                 pmic_reg(slave, 26, val, 1);
 611                 udelay(50);
 612                 /* Raise the core frequency to 800MHz */
 613                 writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
 614         } else {
 615                 /* TO 3.0 */
 616                 /* Setup VCC (SW2) to 1.225 */
 617                 val = pmic_reg(slave, 25, 0, 0);
 618                 val = (val & (~0x1F)) | 0x19;
 619                 pmic_reg(slave, 25, val, 1);
 620
 621                 /* Setup 1V2_DIG1 (SW3) to 1.2 */
 622                 val = pmic_reg(slave, 26, 0, 0);
 623                 val = (val & (~0x1F)) | 0x18;
 624                 pmic_reg(slave, 26, val, 1);
 625         }
 626
 627         if (((pmic_reg(slave, 7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0) ||
 628                 (((pmic_reg(slave, 7, 0, 0) >> 9) & 0x3) == 0)) {
 629                 /* Set switchers in PWM mode for Atlas 2.0 and lower */
 630                 /* Setup the switcher mode for SW1 & SW2*/
 631                 val = pmic_reg(slave, 28, 0, 0);
 632                 val = (val & (~0x3C0F)) | 0x1405;
 633                 pmic_reg(slave, 28, val, 1);
 634
 635                 /* Setup the switcher mode for SW3 & SW4 */
 636                 val = pmic_reg(slave, 29, 0, 0);
 637                 val = (val & (~0xF0F)) | 0x505;
 638                 pmic_reg(slave, 29, val, 1);
 639         } else {
 640                 /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
 641                 /* Setup the switcher mode for SW1 & SW2*/
 642                 val = pmic_reg(slave, 28, 0, 0);
 643                 val = (val & (~0x3C0F)) | 0x2008;
 644                 pmic_reg(slave, 28, val, 1);
 645
 646                 /* Setup the switcher mode for SW3 & SW4 */
 647                 val = pmic_reg(slave, 29, 0, 0);
 648                 val = (val & (~0xF0F)) | 0x808;
 649                 pmic_reg(slave, 29, val, 1);
 650         }
 651
 652         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
 653         val = pmic_reg(slave, 30, 0, 0);
 654         val &= ~0x34030;
 655         val |= 0x10020;
 656         pmic_reg(slave, 30, val, 1);
 657
 658         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 659         val = pmic_reg(slave, 31, 0, 0);
 660         val &= ~0x1FC;
 661         val |= 0x1F4;
 662         pmic_reg(slave, 31, val, 1);
 663
 664         /* Configure VGEN3 and VCAM regulators to use external PNP */
 665         val = 0x208;
 666         pmic_reg(slave, 33, val, 1);
 667         udelay(200);
 668
 669         reg = readl(GPIO2_BASE_ADDR + 0x0);
 670         reg &= ~0x4000;  /* Lower reset line */
 671         writel(reg, GPIO2_BASE_ADDR + 0x0);
 672
 673         reg = readl(GPIO2_BASE_ADDR + 0x4);
 674         reg |= 0x4000;  /* configure GPIO lines as output */
 675         writel(reg, GPIO2_BASE_ADDR + 0x4);
 676
 677         /* Reset the ethernet controller over GPIO */
 678         writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
 679
 680         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 681         val = 0x49249;
 682         pmic_reg(slave, 33, val, 1);
 683
 684         udelay(500);
 685
 686         reg = readl(GPIO2_BASE_ADDR + 0x0);
 687         reg |= 0x4000;
 688         writel(reg, GPIO2_BASE_ADDR + 0x0);
 689
 690         spi_pmic_free(slave);
 691 }
 692 #endif
 693
 694 #ifdef CONFIG_NET_MULTI
 695
 696 int board_eth_init(bd_t *bis)
 697 {
 698         int rc = -ENODEV;
 699
 700         return rc;
 701 }
 702 #endif
 703
 704 #ifdef CONFIG_CMD_MMC
 705
 706 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 707         {MMC_SDHC1_BASE_ADDR, 1, 1},
 708         {MMC_SDHC2_BASE_ADDR, 1, 1},
 709 };
 710
 711 #ifdef CONFIG_DYNAMIC_MMC_DEVNO
 712 int get_mmc_env_devno()
 713 {
 714         uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
 715         return (soc_sbmr & 0x00180000) ? 1 : 0;
 716 }
 717 #endif
 718
 719 int esdhc_gpio_init(bd_t *bis)
 720 {
 721         s32 status = 0;
 722         u32 index = 0;
 723
 724         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 725                 ++index) {
 726                 switch (index) {
 727                 case 0:
 728                         mxc_request_iomux(MX51_PIN_SD1_CMD,
 729                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 730                         mxc_request_iomux(MX51_PIN_SD1_CLK,
 731                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 732
 733                         mxc_request_iomux(MX51_PIN_SD1_DATA0,
 734                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 735                         mxc_request_iomux(MX51_PIN_SD1_DATA1,
 736                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 737                         mxc_request_iomux(MX51_PIN_SD1_DATA2,
 738                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 739                         mxc_request_iomux(MX51_PIN_SD1_DATA3,
 740                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 741                         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 742                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 743                                         PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 744                                         PAD_CTL_PUE_PULL |
 745                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 746                         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 747                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 748                                         PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 749                                         PAD_CTL_PUE_PULL |
 750                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 751                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 752                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 753                                         PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 754                                         PAD_CTL_PUE_PULL |
 755                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 756                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 757                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 758                                         PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 759                                         PAD_CTL_PUE_PULL |
 760                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 761                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 762                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 763                                         PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 764                                         PAD_CTL_PUE_PULL |
 765                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 766                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 767                                         PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 768                                         PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 769                                         PAD_CTL_PUE_PULL |
 770                                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 771                         break;
 772                 case 1:
 773                         mxc_request_iomux(MX51_PIN_SD2_CMD,
 774                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 775                         mxc_request_iomux(MX51_PIN_SD2_CLK,
 776                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 777
 778                         mxc_request_iomux(MX51_PIN_SD2_DATA0,
 779                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 780                         mxc_request_iomux(MX51_PIN_SD2_DATA1,
 781                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 782                         mxc_request_iomux(MX51_PIN_SD2_DATA2,
 783                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 784                         mxc_request_iomux(MX51_PIN_SD2_DATA3,
 785                                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 786                         mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
 787                                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 788                                         PAD_CTL_SRE_FAST);
 789                         mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
 790                                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 791                                         PAD_CTL_SRE_FAST);
 792                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
 793                                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 794                                         PAD_CTL_SRE_FAST);
 795                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
 796                                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 797                                         PAD_CTL_SRE_FAST);
 798                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
 799                                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 800                                         PAD_CTL_SRE_FAST);
 801                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
 802                                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 803                                         PAD_CTL_SRE_FAST);
 804                         break;
 805                 default:
 806                         printf("Warning: you configured more ESDHC controller"
 807                                 "(%d) as supported by the board(2)\n",
 808                                 CONFIG_SYS_FSL_ESDHC_NUM);
 809                         return status;
 810                         break;
 811                 }
 812                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 813         }
 814
 815         return status;
 816 }
 817
 818 int board_mmc_init(bd_t *bis)
 819 {
 820         if (!esdhc_gpio_init(bis))
 821                 return 0;
 822         else
 823                 return -1;
 824 }
 825
 826 #endif
 827
 828 #if defined(CONFIG_MXC_KPD)
 829 int setup_mxc_kpd(void)
 830 {
 831         mxc_request_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0);
 832         mxc_request_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0);
 833         mxc_request_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0);
 834         mxc_request_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0);
 835         mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0);
 836         mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0);
 837         mxc_request_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0);
 838         mxc_request_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0);
 839         mxc_request_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0);
 840         mxc_request_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0);
 841
 842         return 0;
 843 }
 844 #endif
 845
 846 int board_init(void)
 847 {
 848 #ifdef CONFIG_MFG
 849 /* MFG firmware need reset usb to avoid host crash firstly */
 850 #define USBCMD 0x140
 851         int val = readl(OTG_BASE_ADDR + USBCMD);
 852         val &= ~0x1; /*RS bit*/
 853         writel(val, OTG_BASE_ADDR + USBCMD);
 854 #endif
 855         setup_boot_device();
 856         setup_soc_rev();
 857         set_board_rev();
 858
 859         gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;        /* board id for linux */
 860         /* address of boot parameters */
 861         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 862
 863         setup_uart();
 864         setup_nfc();
 865         setup_expio();
 866 #ifdef CONFIG_MXC_FEC
 867         setup_fec();
 868 #endif
 869 #ifdef CONFIG_I2C_MXC
 870         setup_i2c(I2C1_BASE_ADDR);
 871 #endif
 872
 873         return 0;
 874 }
 875
 876 #ifdef BOARD_LATE_INIT
 877 #if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
 878 inline int waiting_for_func_key_pressing(void)
 879 {
 880         struct kpp_key_info key_info = {0, 0};
 881         int switch_delay = CONFIG_ANDROID_BOOTMOD_DELAY;
 882         int state = 0, boot_mode_switch = 0;
 883
 884         mxc_kpp_init();
 885
 886         puts("Press home + power to enter recovery mode ...\n");
 887
 888         while ((switch_delay > 0) && (!boot_mode_switch)) {
 889                 int i;
 890
 891                 --switch_delay;
 892                 /* delay 100 * 10ms */
 893                 for (i = 0; !boot_mode_switch && i < 100; ++i) {
 894                         /* A state machine to scan home + power key */
 895                         /* Check for home + power */
 896                         if (mxc_kpp_getc(&key_info)) {
 897                                 switch (state) {
 898                                 case 0:
 899                                         /* First press */
 900                                         if (TEST_HOME_KEY_DEPRESS(key_info.val, key_info.evt)) {
 901                                                 /* Press Home */
 902                                                 state = 1;
 903                                         } else if (TEST_POWER_KEY_DEPRESS(key_info.val, key_info.evt)) {
 904                                                 /* Press Power */
 905                                                 state = 2;
 906                                         } else {
 907                                                 state = 0;
 908                                         }
 909                                         break;
 910                                 case 1:
 911                                         /* Home is already pressed, try to detect Power */
 912                                         if (TEST_POWER_KEY_DEPRESS(key_info.val,
 913                                                     key_info.evt)) {
 914                                                 /* Switch */
 915                                                 boot_mode_switch = 1;
 916                                         } else {
 917                                             if (TEST_HOME_KEY_DEPRESS(key_info.val,
 918                                                         key_info.evt)) {
 919                                                 /* Not switch */
 920                                                 state = 2;
 921                                             } else
 922                                                 state = 0;
 923                                         }
 924                                         break;
 925                                 case 2:
 926                                         /* Power is already pressed, try to detect Home */
 927                                         if (TEST_HOME_KEY_DEPRESS(key_info.val,
 928                                                     key_info.evt)) {
 929                                                 /* Switch */
 930                                                 boot_mode_switch = 1;
 931                                         } else {
 932                                                 if (TEST_POWER_KEY_DEPRESS(key_info.val,
 933                                                             key_info.evt)) {
 934                                                         /* Not switch */
 935                                                         state = 1;
 936                                                 } else
 937                                                         state = 0;
 938                                         }
 939                                         break;
 940                                 default:
 941                                         break;
 942                                 }
 943
 944                                 if (1 == boot_mode_switch)
 945                                         return 1;
 946                         }
 947                 }
 948                 for (i = 0; i < 100; ++i)
 949                         udelay(10000);
 950         }
 951
 952         return 0;
 953 }
 954
 955 inline int switch_to_recovery_mode(void)
 956 {
 957         char *env = NULL;
 958         char *boot_args = NULL;
 959         char *boot_cmd = NULL;
 960
 961         printf("Boot mode switched to recovery mode!\n");
 962
 963         switch (get_boot_device()) {
 964         case MMC_BOOT:
 965                 boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC;
 966                 boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC;
 967                 break;
 968         case NAND_BOOT:
 969                 printf("Recovery mode not supported in NAND boot\n");
 970                 return -1;
 971                 break;
 972         case SPI_NOR_BOOT:
 973                 printf("Recovery mode not supported in SPI NOR boot\n");
 974                 return -1;
 975                 break;
 976         case UNKNOWN_BOOT:
 977         default:
 978                 printf("Unknown boot device!\n");
 979                 return -1;
 980                 break;
 981         }
 982
 983         env = getenv("bootargs_android_recovery");
 984         /* Set env to recovery mode */
 985         if (!env)
 986                 setenv("bootargs_android", boot_args);
 987         else
 988                 setenv("bootargs_android", env);
 989
 990         env = getenv("bootcmd_android_recovery");
 991         if (!env)
 992                 setenv("bootcmd_android", boot_cmd);
 993         else
 994                 setenv("bootcmd_android", env);
 995         setenv("bootcmd", "run bootcmd_android");
 996
 997         return 0;
 998 }
 999
1000 inline int check_recovery_cmd_file(void)
1001 {
1002         disk_partition_t info;
1003         ulong part_length;
1004         int filelen;
1005
1006         switch (get_boot_device()) {
1007         case MMC_BOOT:
1008                 {
1009                         block_dev_desc_t *dev_desc = NULL;
1010                         struct mmc *mmc = find_mmc_device(0);
1011
1012                         dev_desc = get_dev("mmc", 0);
1013
1014                         if (NULL == dev_desc) {
1015                                 puts("** Block device MMC 0 not supported\n");
1016                                 return 0;
1017                         }
1018
1019                         mmc_init(mmc);
1020
1021                         if (get_partition_info(dev_desc,
1022                                         CONFIG_ANDROID_CACHE_PARTITION_MMC,
1023                                         &info)) {
1024                                 printf("** Bad partition %d **\n",
1025                                         CONFIG_ANDROID_CACHE_PARTITION_MMC);
1026                                 return 0;
1027                         }
1028
1029                         part_length = ext2fs_set_blk_dev(dev_desc,
1030                                                         CONFIG_ANDROID_CACHE_PARTITION_MMC);
1031                         if (part_length == 0) {
1032                                 printf("** Bad partition - mmc 0:%d **\n",
1033                                         CONFIG_ANDROID_CACHE_PARTITION_MMC);
1034                                 ext2fs_close();
1035                                 return 0;
1036                         }
1037
1038                         if (!ext2fs_mount(part_length)) {
1039                                 printf("** Bad ext2 partition or disk - mmc 0:%d **\n",
1040                                         CONFIG_ANDROID_CACHE_PARTITION_MMC);
1041                                 ext2fs_close();
1042                                 return 0;
1043                         }
1044
1045                         filelen = ext2fs_open(CONFIG_ANDROID_RECOVERY_CMD_FILE);
1046
1047                         ext2fs_close();
1048                 }
1049                 break;
1050         case NAND_BOOT:
1051                 return 0;
1052                 break;
1053         case SPI_NOR_BOOT:
1054                 return 0;
1055                 break;
1056         case UNKNOWN_BOOT:
1057         default:
1058                 return 0;
1059                 break;
1060         }
1061
1062         return (filelen > 0) ? 1 : 0;
1063
1064 }
1065 #endif
1066
1067 int board_late_init(void)
1068 {
1069 #ifdef CONFIG_I2C_MXC
1070         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1071         if (!i2c_probe(0x34))
1072                 setup_core_voltage_i2c();
1073         else
1074 #endif
1075 #ifdef CONFIG_IMX_ECSPI
1076                 setup_core_voltage_spi();
1077 #endif
1078
1079 #if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
1080         if (waiting_for_func_key_pressing())
1081                 switch_to_recovery_mode();
1082         else {
1083                 if (check_recovery_cmd_file()) {
1084                         puts("Recovery command file founded!\n");
1085                         switch_to_recovery_mode();
1086                 }
1087         }
1088 #endif
1089
1090         return 0;
1091 }
1092 #endif
1093
1094 int checkboard(void)
1095 {
1096         printf("Board: MX51 BABBAGE ");
1097
1098         if (is_soc_rev(CHIP_REV_3_0) == 0) {
1099                 printf("3.0 [");
1100         } else if ((is_soc_rev(CHIP_REV_2_0) == 0)
1101          && (system_rev & (BOARD_REV_2_0 << BOARD_VER_OFFSET))) {
1102                 printf("2.5 [");
1103         } else if (is_soc_rev(CHIP_REV_2_0) == 0) {
1104                 printf("2.0 [");
1105         } else if (is_soc_rev(CHIP_REV_1_1) == 0) {
1106                 printf("1.1 [");
1107         } else {
1108                 printf("1.0 [");
1109         }
1110
1111         switch (__REG(SRC_BASE_ADDR + 0x8)) {
1112         case 0x0001:
1113                 printf("POR");
1114                 break;
1115         case 0x0009:
1116                 printf("RST");
1117                 break;
1118         case 0x0010:
1119         case 0x0011:
1120                 printf("WDOG");
1121                 break;
1122         default:
1123                 printf("unknown");
1124         }
1125         printf("]\n");
1126
1127         printf("Boot Device: ");
1128         switch (get_boot_device()) {
1129         case NAND_BOOT:
1130                 printf("NAND\n");
1131                 break;
1132         case SPI_NOR_BOOT:
1133                 printf("SPI NOR\n");
1134                 break;
1135         case MMC_BOOT:
1136                 printf("MMC\n");
1137                 break;
1138         case UNKNOWN_BOOT:
1139         default:
1140                 printf("UNKNOWN\n");
1141                 break;
1142         }
1143         return 0;
1144 }
1145