board/freescale/mx53_evk/mx53_evk.c

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/mx53.h>
  28 #include <asm/arch/mx53_pins.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <imx_spi.h>
  32
  33 #if CONFIG_I2C_MXC
  34 #include <i2c.h>
  35 #endif
  36
  37 #ifdef CONFIG_CMD_MMC
  38 #include <mmc.h>
  39 #include <fsl_esdhc.h>
  40 #endif
  41
  42 #ifdef CONFIG_ARCH_MMU
  43 #include <asm/mmu.h>
  44 #include <asm/arch/mmu.h>
  45 #endif
  46
  47 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
  48 #include <asm/imx_iim.h>
  49 #endif
  50
  51 #ifdef CONFIG_CMD_CLOCK
  52 #include <asm/clock.h>
  53 #endif
  54
  55 DECLARE_GLOBAL_DATA_PTR;
  56
  57 static u32 system_rev;
  58 static enum boot_device boot_dev;
  59
  60 static inline void setup_boot_device(void)
  61 {
  62         uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
  63         uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
  64         uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
  65
  66         switch (bt_mem_ctl) {
  67         case 0x0:
  68                 if (bt_mem_type)
  69                         boot_dev = ONE_NAND_BOOT;
  70                 else
  71                         boot_dev = WEIM_NOR_BOOT;
  72                 break;
  73         case 0x2:
  74                 if (bt_mem_type)
  75                         boot_dev = SATA_BOOT;
  76                 else
  77                         boot_dev = PATA_BOOT;
  78                 break;
  79         case 0x3:
  80                 if (bt_mem_type)
  81                         boot_dev = SPI_NOR_BOOT;
  82                 else
  83                         boot_dev = I2C_BOOT;
  84                 break;
  85         case 0x4:
  86         case 0x5:
  87                 boot_dev = SD_BOOT;
  88                 break;
  89         case 0x6:
  90         case 0x7:
  91                 boot_dev = MMC_BOOT;
  92                 break;
  93         case 0x8 ... 0xf:
  94                 boot_dev = NAND_BOOT;
  95                 break;
  96         default:
  97                 boot_dev = UNKNOWN_BOOT;
  98                 break;
  99         }
 100 }
 101
 102 enum boot_device get_boot_device(void)
 103 {
 104         return boot_dev;
 105 }
 106
 107 u32 get_board_rev(void)
 108 {
 109         return system_rev;
 110 }
 111
 112 static inline void setup_soc_rev(void)
 113 {
 114         system_rev = 0x53000 | CHIP_REV_1_0;
 115 }
 116
 117 static inline void setup_board_rev(int rev)
 118 {
 119         system_rev |= (rev & 0xF) << 8;
 120 }
 121
 122 inline int is_soc_rev(int rev)
 123 {
 124         return (system_rev & 0xFF) - rev;
 125 }
 126
 127 #ifdef CONFIG_ARCH_MMU
 128 void board_mmu_init(void)
 129 {
 130         unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
 131         unsigned long i;
 132
 133         /*
 134         * Set the TTB register
 135         */
 136         asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
 137
 138         /*
 139         * Set the Domain Access Control Register
 140         */
 141         i = ARM_ACCESS_DACR_DEFAULT;
 142         asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
 143
 144         /*
 145         * First clear all TT entries - ie Set them to Faulting
 146         */
 147         memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
 148         /* Actual   Virtual  Size   Attributes          Function */
 149         /* Base     Base     MB     cached? buffered?  access permissions */
 150         /* xxx00000 xxx00000 */
 151         X_ARM_MMU_SECTION(0x000, 0x000, 0x10,
 152                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 153                         ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */
 154         X_ARM_MMU_SECTION(0x070, 0x070, 0x010,
 155                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 156                         ARM_ACCESS_PERM_RW_RW); /* IRAM */
 157         X_ARM_MMU_SECTION(0x100, 0x100, 0x040,
 158                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 159                         ARM_ACCESS_PERM_RW_RW); /* SATA */
 160         X_ARM_MMU_SECTION(0x180, 0x180, 0x100,
 161                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 162                         ARM_ACCESS_PERM_RW_RW); /* IPUv3M */
 163         X_ARM_MMU_SECTION(0x200, 0x200, 0x200,
 164                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 165                         ARM_ACCESS_PERM_RW_RW); /* GPU */
 166         X_ARM_MMU_SECTION(0x400, 0x400, 0x300,
 167                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 168                         ARM_ACCESS_PERM_RW_RW); /* periperals */
 169         X_ARM_MMU_SECTION(0x700, 0x700, 0x400,
 170                         ARM_CACHEABLE, ARM_BUFFERABLE,
 171                         ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
 172         X_ARM_MMU_SECTION(0x700, 0xB00, 0x400,
 173                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 174                         ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
 175         X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100,
 176                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 177                         ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
 178         X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x040,
 179                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 180                         ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */
 181         X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001,
 182                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 183                         ARM_ACCESS_PERM_RW_RW); /* iRam */
 184
 185         /* Workaround for arm errata #709718 */
 186         /* Setup PRRR so device is always mapped to non-shared */
 187         asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
 188         i &= (~(3 << 0x10));
 189         asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
 190
 191         /* Enable MMU */
 192         MMU_ON();
 193 }
 194 #endif
 195
 196 int dram_init(void)
 197 {
 198         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 199         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 200         return 0;
 201 }
 202
 203 static void setup_uart(void)
 204 {
 205
 206         /* UART1 RXD */
 207         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
 208         mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 0x1E4);
 209         mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
 210
 211         /* UART1 TXD */
 212         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
 213         mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 0x1E4);
 214 }
 215
 216 #ifdef CONFIG_I2C_MXC
 217 static void setup_i2c(unsigned int module_base)
 218 {
 219         switch (module_base) {
 220         case I2C1_BASE_ADDR:
 221                 /* i2c1 SDA */
 222                 mxc_request_iomux(MX53_PIN_CSI0_D8,
 223                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
 224                 mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
 225                                 INPUT_CTL_PATH0);
 226                 mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST |
 227                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 228                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 229                                 PAD_CTL_HYS_ENABLE);
 230                 /* i2c1 SCL */
 231                 mxc_request_iomux(MX53_PIN_CSI0_D9,
 232                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
 233                 mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
 234                                 INPUT_CTL_PATH0);
 235                 mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST |
 236                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 237                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 238                                 PAD_CTL_HYS_ENABLE);
 239                 break;
 240         case I2C2_BASE_ADDR:
 241                 /* i2c2 SDA */
 242                 mxc_request_iomux(MX53_PIN_KEY_ROW3,
 243                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
 244                 mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
 245                                 INPUT_CTL_PATH0);
 246                 mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
 247                                 PAD_CTL_SRE_FAST |
 248                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 249                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 250                                 PAD_CTL_HYS_ENABLE);
 251
 252                 /* i2c2 SCL */
 253                 mxc_request_iomux(MX53_PIN_KEY_COL3,
 254                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
 255                 mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
 256                                 INPUT_CTL_PATH0);
 257                 mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
 258                                 PAD_CTL_SRE_FAST |
 259                                 PAD_CTL_ODE_OPENDRAIN_ENABLE |
 260                                 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 261                                 PAD_CTL_HYS_ENABLE);
 262                 break;
 263         default:
 264                 printf("Invalid I2C base: 0x%x\n", module_base);
 265                 break;
 266         }
 267 }
 268
 269 void setup_core_voltages(void)
 270 {
 271         unsigned char buf[4] = { 0 };
 272
 273         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 274
 275         /* Set core voltage VDDGP to 1.05V for 800MHZ */
 276         buf[0] = 0x45;
 277         buf[1] = 0x4a;
 278         buf[2] = 0x52;
 279         if (i2c_write(0x8, 24, 1, buf, 3))
 280                 return;
 281
 282         /* Set DDR voltage VDDA to 1.25V */
 283         buf[0] = 0;
 284         buf[1] = 0x63;
 285         buf[2] = 0x1a;
 286         if (i2c_write(0x8, 26, 1, buf, 3))
 287                 return;
 288
 289         /* Raise the core frequency to 800MHz */
 290         writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
 291 }
 292
 293 #ifndef CONFIG_MX53_ARM2
 294 static int __read_adc_channel(unsigned int chan)
 295 {
 296         unsigned char buf[4] = { 0 };
 297
 298         buf[0] = (0xb0 | ((chan & 0x1) << 3) | ((chan >> 1) & 0x7));
 299
 300         /* LTC2495 need 410ms delay */
 301         udelay(410000);
 302
 303         if (i2c_write(0x14, chan, 0, &buf[0], 1)) {
 304                 printf("%s:i2c_write:error\n", __func__);
 305                 return -1;
 306         }
 307
 308         /* LTC2495 need 410ms delay*/
 309         udelay(410000);
 310
 311         if (i2c_read(0x14, chan, 0, &buf[0], 3)) {
 312                 printf("%s:i2c_read:error\n", __func__);
 313                 return -1;
 314         }
 315
 316         return buf[0] << 16 | buf[1] << 8 | buf[2];
 317 }
 318
 319 static int __lookup_board_id(int adc_val)
 320 {
 321         int id;
 322
 323         if (adc_val < 0x3FFFC0)
 324                 id = 0;
 325         else if (adc_val < 0x461863)
 326                 id = 1;
 327         else if (adc_val < 0x4C30C4)
 328                 id = 2;
 329         else if (adc_val < 0x524926)
 330                 id = 3;
 331         else if (adc_val < 0x586187)
 332                 id = 4;
 333         else if (adc_val < 0x5E79E9)
 334                 id = 5;
 335         else if (adc_val < 0x64924A)
 336                 id = 6;
 337         else if (adc_val < 0x6AAAAC)
 338                 id = 7;
 339         else if (adc_val < 0x70C30D)
 340                 id = 8;
 341         else if (adc_val < 0x76DB6F)
 342                 id = 9;
 343         else if (adc_val < 0x7CF3D0)
 344                 id = 10;
 345         else if (adc_val < 0x830C32)
 346                 id = 11;
 347         else if (adc_val < 0x892493)
 348                 id = 12;
 349         else if (adc_val < 0x8F3CF5)
 350                 id = 13;
 351         else if (adc_val < 0x955556)
 352                 id = 14;
 353         else if (adc_val < 0x9B6DB8)
 354                 id = 15;
 355         else if (adc_val < 0xA18619)
 356                 id = 16;
 357         else if (adc_val < 0xA79E7B)
 358                 id = 17;
 359         else if (adc_val < 0xADB6DC)
 360                 id = 18;
 361         else if (adc_val < 0xB3CF3E)
 362                 id = 19;
 363         else if (adc_val < 0xB9E79F)
 364                 id = 20;
 365         else if (adc_val <= 0xC00000)
 366                 id = 21;
 367                 else
 368                 return -1;
 369
 370         return id;
 371 }
 372
 373 static int __print_board_info(int id0, int id1)
 374 {
 375         int ret = 0;
 376
 377         switch (id0) {
 378         case 21:
 379                 switch (id1) {
 380                 case 15:
 381                         printf("MX53-EVK with DDR2 1GByte RevB\n");
 382
 383                         break;
 384                 case 18:
 385                         printf("MX53-EVK with DDR2 2GByte RevA1\n");
 386
 387                         break;
 388                 case 19:
 389                         printf("MX53-EVK with DDR2 2GByte RevA2\n");
 390                         break;
 391                 default:
 392                         printf("Unkown board id1:%d\n", id1);
 393                         ret = -1;
 394
 395                         break;
 396                 }
 397
 398                 break;
 399         case 11:
 400                 switch (id1) {
 401                 case 1:
 402                         printf("MX53 1.5V DDR3 x8 CPU Card, Rev. A\n");
 403
 404                         break;
 405                 case 11:
 406                         printf("MX53 1.8V DDR2 x8 CPU Card, Rev. A\n");
 407
 408                         break;
 409                 default:
 410                         printf("Unkown board id1:%d\n", id1);
 411                         ret = -1;
 412
 413                         break;
 414                 }
 415
 416                 break;
 417         default:
 418                 printf("Unkown board id0:%d\n", id0);
 419
 420                 break;
 421         }
 422
 423         return ret;
 424 }
 425
 426 static int _identify_board_fix_up(int id0, int id1)
 427 {
 428         int ret = 0;
 429
 430 #ifdef CONFIG_CMD_CLOCK
 431         /* For EVK RevB, set DDR to 400MHz */
 432         if (id0 == 21 && id1 == 15) {
 433                 ret = clk_config(CONFIG_REF_CLK_FREQ, 400, PERIPH_CLK);
 434                 if (ret < 0)
 435                         return ret;
 436
 437                 ret = clk_config(CONFIG_REF_CLK_FREQ, 400, DDR_CLK);
 438                 if (ret < 0)
 439                         return ret;
 440
 441                 /* set up rev #2 for EVK RevB board */
 442                 setup_board_rev(2);
 443         }
 444 #endif
 445         return ret;
 446 }
 447
 448 int identify_board_id(void)
 449 {
 450         int ret = 0;
 451         int bd_id0, bd_id1;
 452
 453 #define CPU_CHANNEL_ID0 0xc
 454 #define CPU_CHANNEL_ID1 0xd
 455
 456         ret = bd_id0 = __read_adc_channel(CPU_CHANNEL_ID0);
 457         if (ret < 0)
 458                 return ret;
 459
 460         ret = bd_id1 = __read_adc_channel(CPU_CHANNEL_ID1);
 461         if (ret < 0)
 462                 return ret;
 463
 464         ret = bd_id0 = __lookup_board_id(bd_id0);
 465         if (ret < 0)
 466                 return ret;
 467
 468         ret = bd_id1 = __lookup_board_id(bd_id1);
 469         if (ret < 0)
 470                 return ret;
 471
 472         ret = __print_board_info(bd_id0, bd_id1);
 473         if (ret < 0)
 474                 return ret;
 475
 476         ret = _identify_board_fix_up(bd_id0, bd_id1);
 477
 478         return ret;
 479
 480 }
 481 #endif
 482 #endif
 483
 484 #ifdef CONFIG_IMX_ECSPI
 485 s32 spi_get_cfg(struct imx_spi_dev_t *dev)
 486 {
 487         switch (dev->slave.cs) {
 488         case 0:
 489                 /* pmic */
 490                 dev->base = CSPI1_BASE_ADDR;
 491                 dev->freq = 2500000;
 492                 dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
 493                 dev->ss = 0;
 494                 dev->fifo_sz = 64 * 4;
 495                 dev->us_delay = 0;
 496                 break;
 497         case 1:
 498                 /* spi_nor */
 499                 dev->base = CSPI1_BASE_ADDR;
 500                 dev->freq = 2500000;
 501                 dev->ss_pol = IMX_SPI_ACTIVE_LOW;
 502                 dev->ss = 1;
 503                 dev->fifo_sz = 64 * 4;
 504                 dev->us_delay = 0;
 505                 break;
 506         default:
 507                 printf("Invalid Bus ID! \n");
 508                 break;
 509         }
 510
 511         return 0;
 512 }
 513
 514 void spi_io_init(struct imx_spi_dev_t *dev)
 515 {
 516         switch (dev->base) {
 517         case CSPI1_BASE_ADDR:
 518                 /* Select mux mode: ALT4 mux port: MOSI of instance: ecspi1 */
 519                 mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4);
 520                 mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0x104);
 521                 mxc_iomux_set_input(
 522                                 MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, 0x3);
 523
 524                 /* Select mux mode: ALT4 mux port: MISO of instance: ecspi1. */
 525                 mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4);
 526                 mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0x104);
 527                 mxc_iomux_set_input(
 528                                 MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, 0x3);
 529
 530                 if (dev->ss == 0) {
 531                         /* de-select SS1 of instance: ecspi1. */
 532                         mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
 533                         mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x1E4);
 534
 535                         /* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
 536                         mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
 537                         mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x104);
 538                         mxc_iomux_set_input(
 539                                 MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, 0x3);
 540                 } else if (dev->ss == 1) {
 541                         /* de-select SS0 of instance: ecspi1. */
 542                         mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
 543                         mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x1E4);
 544
 545                         /* mux mode: ALT0 mux port: SS1 of instance: ecspi1. */
 546                         mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
 547                         mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x104);
 548                         mxc_iomux_set_input(
 549                                 MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, 0x2);
 550                 }
 551
 552                 /* Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 553                 mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4);
 554                 mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0x104);
 555                 mxc_iomux_set_input(
 556                         MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x3);
 557
 558                 break;
 559         case CSPI2_BASE_ADDR:
 560         default:
 561
 562                 break;
 563         }
 564 }
 565 #endif
 566
 567 #ifdef CONFIG_MXC_FEC
 568
 569 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
 570
 571 int fec_get_mac_addr(unsigned char *mac)
 572 {
 573         u32 *iim1_mac_base =
 574                 (u32 *)(IIM_BASE_ADDR + IIM_BANK_AREA_1_OFFSET +
 575                         CONFIG_IIM_MAC_ADDR_OFFSET);
 576         int i;
 577
 578         for (i = 0; i < 6; ++i, ++iim1_mac_base)
 579                 mac[i] = (u8)readl(iim1_mac_base);
 580
 581         return 0;
 582 }
 583 #endif
 584
 585 static void setup_fec(void)
 586 {
 587         volatile unsigned int reg;
 588
 589         /*FEC_MDIO*/
 590         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
 591         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 0x1FC);
 592         mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 593
 594         /*FEC_MDC*/
 595         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 596         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, 0x004);
 597
 598         /* FEC RXD1 */
 599         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 600         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 0x180);
 601
 602         /* FEC RXD0 */
 603         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 604         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 0x180);
 605
 606          /* FEC TXD1 */
 607         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 608         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, 0x004);
 609
 610         /* FEC TXD0 */
 611         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 612         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, 0x004);
 613
 614         /* FEC TX_EN */
 615         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 616         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, 0x004);
 617
 618         /* FEC TX_CLK */
 619         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 620         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 0x180);
 621
 622         /* FEC RX_ER */
 623         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 624         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 0x180);
 625
 626         /* FEC CRS */
 627         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 628         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 0x180);
 629
 630         /* phy reset: gpio7-6 */
 631         mxc_request_iomux(MX53_PIN_ATA_DA_0, IOMUX_CONFIG_ALT1);
 632
 633         reg = readl(GPIO7_BASE_ADDR + 0x0);
 634         reg &= ~0x40;
 635         writel(reg, GPIO7_BASE_ADDR + 0x0);
 636
 637         reg = readl(GPIO7_BASE_ADDR + 0x4);
 638         reg |= 0x40;
 639         writel(reg, GPIO7_BASE_ADDR + 0x4);
 640
 641         udelay(500);
 642
 643         reg = readl(GPIO7_BASE_ADDR + 0x0);
 644         reg |= 0x40;
 645         writel(reg, GPIO7_BASE_ADDR + 0x0);
 646
 647 }
 648 #endif
 649
 650 #ifdef CONFIG_CMD_MMC
 651
 652 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 653         {MMC_SDHC1_BASE_ADDR, 1, 1},
 654         {MMC_SDHC3_BASE_ADDR, 1, 1},
 655 };
 656
 657 #ifdef CONFIG_DYNAMIC_MMC_DEVNO
 658 int get_mmc_env_devno()
 659 {
 660         uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
 661         return (soc_sbmr & 0x00300000)  ? 1 : 0;
 662 }
 663 #endif
 664
 665
 666 int esdhc_gpio_init(bd_t *bis)
 667 {
 668         s32 status = 0;
 669         u32 index = 0;
 670
 671         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 672                 ++index) {
 673                 switch (index) {
 674                 case 0:
 675                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 676                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 677                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 678                                                 IOMUX_CONFIG_ALT0);
 679                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 680                                                 IOMUX_CONFIG_ALT0);
 681                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 682                                                 IOMUX_CONFIG_ALT0);
 683                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 684                                                 IOMUX_CONFIG_ALT0);
 685
 686                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
 687                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
 688                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
 689                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
 690                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
 691                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
 692                         break;
 693                 case 1:
 694                         mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 695                                                 IOMUX_CONFIG_ALT2);
 696                         mxc_request_iomux(MX53_PIN_ATA_IORDY,
 697                                                 IOMUX_CONFIG_ALT2);
 698                         mxc_request_iomux(MX53_PIN_ATA_DATA8,
 699                                                 IOMUX_CONFIG_ALT4);
 700                         mxc_request_iomux(MX53_PIN_ATA_DATA9,
 701                                                 IOMUX_CONFIG_ALT4);
 702                         mxc_request_iomux(MX53_PIN_ATA_DATA10,
 703                                                 IOMUX_CONFIG_ALT4);
 704                         mxc_request_iomux(MX53_PIN_ATA_DATA11,
 705                                                 IOMUX_CONFIG_ALT4);
 706                         mxc_request_iomux(MX53_PIN_ATA_DATA0,
 707                                                 IOMUX_CONFIG_ALT4);
 708                         mxc_request_iomux(MX53_PIN_ATA_DATA1,
 709                                                 IOMUX_CONFIG_ALT4);
 710                         mxc_request_iomux(MX53_PIN_ATA_DATA2,
 711                                                 IOMUX_CONFIG_ALT4);
 712                         mxc_request_iomux(MX53_PIN_ATA_DATA3,
 713                                                 IOMUX_CONFIG_ALT4);
 714
 715                         mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4);
 716                         mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4);
 717                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4);
 718                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4);
 719                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4);
 720                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4);
 721                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4);
 722                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4);
 723                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4);
 724                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4);
 725
 726                         break;
 727                 default:
 728                         printf("Warning: you configured more ESDHC controller"
 729                                 "(%d) as supported by the board(2)\n",
 730                                 CONFIG_SYS_FSL_ESDHC_NUM);
 731                         return status;
 732                         break;
 733                 }
 734                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 735         }
 736
 737         return status;
 738 }
 739
 740 int board_mmc_init(bd_t *bis)
 741 {
 742         if (!esdhc_gpio_init(bis))
 743                 return 0;
 744         else
 745                 return -1;
 746 }
 747
 748 #endif
 749
 750 int board_init(void)
 751 {
 752 #ifdef CONFIG_MFG
 753 /* MFG firmware need reset usb to avoid host crash firstly */
 754 #define USBCMD 0x140
 755         int val = readl(OTG_BASE_ADDR + USBCMD);
 756         val &= ~0x1; /*RS bit*/
 757         writel(val, OTG_BASE_ADDR + USBCMD);
 758 #endif
 759         setup_boot_device();
 760         setup_soc_rev();
 761 #if defined(CONFIG_MX53_ARM2) || defined(CONFIG_MX53_ARM2_DDR3)
 762         setup_board_rev(1);
 763 #endif
 764         gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;    /* board id for linux */
 765         /* address of boot parameters */
 766         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 767
 768         setup_uart();
 769         setup_fec();
 770
 771 #ifdef CONFIG_I2C_MXC
 772         setup_i2c(CONFIG_SYS_I2C_PORT);
 773         setup_core_voltages();
 774 #endif
 775
 776         return 0;
 777 }
 778
 779 int board_late_init(void)
 780 {
 781         return 0;
 782 }
 783
 784 int checkboard(void)
 785 {
 786         printf("Board: ");
 787
 788 #ifdef CONFIG_MX53_ARM2
 789         printf("Board: MX53 ARMADILLO2 ");
 790         printf("1.0 [");
 791 #else
 792 #ifdef CONFIG_I2C_MXC
 793         identify_board_id();
 794
 795         printf("Boot Reason: [");
 796 #endif
 797 #endif
 798
 799         switch (__REG(SRC_BASE_ADDR + 0x8)) {
 800         case 0x0001:
 801                 printf("POR");
 802                 break;
 803         case 0x0009:
 804                 printf("RST");
 805                 break;
 806         case 0x0010:
 807         case 0x0011:
 808                 printf("WDOG");
 809                 break;
 810         default:
 811                 printf("unknown");
 812         }
 813         printf("]\n");
 814
 815         printf("Boot Device: ");
 816         switch (get_boot_device()) {
 817         case WEIM_NOR_BOOT:
 818                 printf("NOR\n");
 819                 break;
 820         case ONE_NAND_BOOT:
 821                 printf("ONE NAND\n");
 822                 break;
 823         case PATA_BOOT:
 824                 printf("PATA\n");
 825                 break;
 826         case SATA_BOOT:
 827                 printf("SATA\n");
 828                 break;
 829         case I2C_BOOT:
 830                 printf("I2C\n");
 831                 break;
 832         case SPI_NOR_BOOT:
 833                 printf("SPI NOR\n");
 834                 break;
 835         case SD_BOOT:
 836                 printf("SD\n");
 837                 break;
 838         case MMC_BOOT:
 839                 printf("MMC\n");
 840                 break;
 841         case NAND_BOOT:
 842                 printf("NAND\n");
 843                 break;
 844         case UNKNOWN_BOOT:
 845         default:
 846                 printf("UNKNOWN\n");
 847                 break;
 848         }
 849         return 0;
 850 }