board/freescale/mx53ard/mx53ard.c

   1 /*
   2  * (C) Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/arch/crm_regs.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/iomux-mx53.h>
  30 #include <asm/errno.h>
  31 #include <netdev.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc.h>
  34 #include <asm/gpio.h>
  35
  36 #define ETHERNET_INT            IMX_GPIO_NR(2, 31)
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 int dram_init(void)
  41 {
  42         u32 size1, size2;
  43
  44         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  45         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  46
  47         gd->ram_size = size1 + size2;
  48
  49         return 0;
  50 }
  51 void dram_init_banksize(void)
  52 {
  53         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  54         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  55
  56         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  57         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  58 }
  59
  60 #ifdef CONFIG_NAND_MXC
  61 static void setup_iomux_nand(void)
  62 {
  63         static const iomux_v3_cfg_t nand_pads[] = {
  64                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
  65                                 PAD_CTL_DSE_HIGH),
  66                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
  67                                 PAD_CTL_DSE_HIGH),
  68                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
  69                                 PAD_CTL_PUS_100K_UP),
  70                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
  71                                 PAD_CTL_DSE_HIGH),
  72                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
  73                                 PAD_CTL_DSE_HIGH),
  74                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
  75                                 PAD_CTL_PUS_100K_UP),
  76                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
  77                                 PAD_CTL_DSE_HIGH),
  78                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
  79                                 PAD_CTL_DSE_HIGH),
  80                 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
  81                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  82                 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
  83                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  84                 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
  85                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  86                 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
  87                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  88                 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
  89                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  90                 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
  91                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  92                 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
  93                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  94                 NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
  95                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  96         };
  97
  98         u32 i, reg;
  99
 100         reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
 101         reg &= ~M4IF_GENP_WEIM_MM_MASK;
 102         __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
 103         for (i = 0x4; i < 0x94; i += 0x18) {
 104                 reg = __raw_readl(WEIM_BASE_ADDR + i);
 105                 reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
 106                 __raw_writel(reg, WEIM_BASE_ADDR + i);
 107         }
 108
 109         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 110 }
 111 #else
 112 static void setup_iomux_nand(void)
 113 {
 114 }
 115 #endif
 116
 117 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 118                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 119
 120 static void setup_iomux_uart(void)
 121 {
 122         static const iomux_v3_cfg_t uart_pads[] = {
 123                 NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
 124                 NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
 125         };
 126
 127         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 128 }
 129
 130 #ifdef CONFIG_FSL_ESDHC
 131 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 132         {MMC_SDHC1_BASE_ADDR},
 133         {MMC_SDHC2_BASE_ADDR},
 134 };
 135
 136 int board_mmc_getcd(struct mmc *mmc)
 137 {
 138         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 139         int ret;
 140
 141         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 142         gpio_direction_input(IMX_GPIO_NR(1, 1));
 143         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
 144         gpio_direction_input(IMX_GPIO_NR(1, 4));
 145
 146         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 147                 ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
 148         else
 149                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 150
 151         return ret;
 152 }
 153
 154 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 155                                  PAD_CTL_PUS_100K_UP)
 156 #define SD_CLK_PAD_CTRL         (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
 157 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 158                                  PAD_CTL_DSE_HIGH)
 159
 160 int board_mmc_init(bd_t *bis)
 161 {
 162         static const iomux_v3_cfg_t sd1_pads[] = {
 163                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 164                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
 165                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 166                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 167                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 168                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 169         };
 170
 171         static const iomux_v3_cfg_t sd2_pads[] = {
 172                 NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
 173                 NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
 174                 NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
 175                 NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
 176                 NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
 177                 NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
 178                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
 179                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
 180                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
 181                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
 182         };
 183
 184         u32 index;
 185         s32 status = 0;
 186
 187         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 188         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 189
 190         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 191                 switch (index) {
 192                 case 0:
 193                         imx_iomux_v3_setup_multiple_pads(sd1_pads,
 194                                                          ARRAY_SIZE(sd1_pads));
 195                         break;
 196                 case 1:
 197                         imx_iomux_v3_setup_multiple_pads(sd2_pads,
 198                                                          ARRAY_SIZE(sd2_pads));
 199                         break;
 200                 default:
 201                         printf("Warning: you configured more ESDHC controller"
 202                                 "(%d) as supported by the board(2)\n",
 203                                 CONFIG_SYS_FSL_ESDHC_NUM);
 204                         return status;
 205                 }
 206                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 207         }
 208
 209         return status;
 210 }
 211 #endif
 212
 213 static void weim_smc911x_iomux(void)
 214 {
 215         static const iomux_v3_cfg_t weim_smc911x_pads[] = {
 216                 /* Data bus */
 217                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
 218                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 219                 NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
 220                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 221                 NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
 222                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 223                 NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
 224                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 225                 NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
 226                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 227                 NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
 228                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 229                 NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
 230                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 231                 NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
 232                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 233                 NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
 234                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 235                 NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
 236                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 237                 NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
 238                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 239                 NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
 240                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 241                 NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
 242                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 243                 NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
 244                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 245                 NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
 246                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 247                 NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
 248                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 249
 250                 /* Address lines */
 251                 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
 252                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 253                 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
 254                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 255                 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
 256                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 257                 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
 258                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 259                 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
 260                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 261                 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
 262                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 263                 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
 264                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 265
 266                 /* other EIM signals for ethernet */
 267                 MX53_PAD_EIM_OE__EMI_WEIM_OE,
 268                 MX53_PAD_EIM_RW__EMI_WEIM_RW,
 269                 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
 270         };
 271
 272         /* ETHERNET_INT as GPIO2_31 */
 273         imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
 274         gpio_direction_input(ETHERNET_INT);
 275
 276         /* WEIM bus */
 277         imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
 278                                                 ARRAY_SIZE(weim_smc911x_pads));
 279 }
 280
 281 static void weim_cs1_settings(void)
 282 {
 283         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 284
 285         writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
 286         writel(0x0, &weim_regs->cs1gcr2);
 287         writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
 288         writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
 289         writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
 290         writel(0x0, &weim_regs->cs1wcr2);
 291         writel(0x0, &weim_regs->wcr);
 292
 293         set_chipselect_size(CS0_64M_CS1_64M);
 294 }
 295
 296 int board_early_init_f(void)
 297 {
 298         setup_iomux_nand();
 299         setup_iomux_uart();
 300         return 0;
 301 }
 302
 303 int board_init(void)
 304 {
 305         /* address of boot parameters */
 306         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 307
 308         return 0;
 309 }
 310
 311 int board_eth_init(bd_t *bis)
 312 {
 313         int rc = -ENODEV;
 314
 315         weim_smc911x_iomux();
 316         weim_cs1_settings();
 317
 318 #ifdef CONFIG_SMC911X
 319         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 320 #endif
 321         return rc;
 322 }
 323
 324 int checkboard(void)
 325 {
 326         puts("Board: MX53ARD\n");
 327
 328         return 0;
 329 }