board/freescale/mx6qarm2/mx6qarm2.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/mx6-pins.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/errno.h>
  13 #include <asm/gpio.h>
  14 #include <asm/imx-common/iomux-v3.h>
  15 #include <mmc.h>
  16 #include <fsl_esdhc.h>
  17 #include <miiphy.h>
  18 #include <netdev.h>
  19 #include <usb.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  24         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  25         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  26
  27 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  28         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  29         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  30
  31 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  32         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  33
  34 int dram_init(void)
  35 {
  36 #if defined(CONFIG_SOC_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
  37         defined(CONFIG_DDR_32BIT)
  38         gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
  39 #else
  40         gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
  41 #endif
  42
  43         return 0;
  44 }
  45
  46 iomux_v3_cfg_t const uart4_pads[] = {
  47         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  48         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  49 };
  50
  51 iomux_v3_cfg_t const usdhc3_pads[] = {
  52         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  53         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  54         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  55         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  56         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  57         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62         MX6_PAD_NANDF_CS0__GPIO6_IO11, /* CD */
  63 };
  64
  65 iomux_v3_cfg_t const usdhc4_pads[] = {
  66         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76 };
  77
  78 iomux_v3_cfg_t const enet_pads[] = {
  79         MX6_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94 };
  95
  96
  97 static void setup_iomux_uart(void)
  98 {
  99         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 100 }
 101
 102 static void setup_iomux_enet(void)
 103 {
 104         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 105 }
 106
 107 #ifdef CONFIG_FSL_ESDHC
 108 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 109         {USDHC3_BASE_ADDR},
 110         {USDHC4_BASE_ADDR},
 111 };
 112
 113 int board_mmc_getcd(struct mmc *mmc)
 114 {
 115         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 116         int ret;
 117
 118         if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 119                 gpio_direction_input(IMX_GPIO_NR(6, 11));
 120                 ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
 121         } else /* Don't have the CD GPIO pin on board */
 122                 ret = 1;
 123
 124         return ret;
 125 }
 126
 127 int board_mmc_init(bd_t *bis)
 128 {
 129         int ret;
 130         u32 index = 0;
 131
 132         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 133         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 134
 135         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 136                 switch (index) {
 137                 case 0:
 138                         imx_iomux_v3_setup_multiple_pads(
 139                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 140                         break;
 141                 case 1:
 142                         imx_iomux_v3_setup_multiple_pads(
 143                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 144                         break;
 145                 default:
 146                         printf("Warning: you configured more USDHC controllers"
 147                                 "(%d) then supported by the board (%d)\n",
 148                                 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 149                         return -EINVAL;
 150                 }
 151
 152                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 153                 if (ret)
 154                         return ret;
 155         }
 156
 157         return 0;
 158 }
 159 #endif
 160
 161 #define MII_MMD_ACCESS_CTRL_REG         0xd
 162 #define MII_MMD_ACCESS_ADDR_DATA_REG    0xe
 163 #define MII_DBG_PORT_REG                0x1d
 164 #define MII_DBG_PORT2_REG               0x1e
 165
 166 int fecmxc_mii_postcall(int phy)
 167 {
 168         unsigned short val;
 169
 170         /*
 171          * Due to the i.MX6Q Armadillo2 board HW design,there is
 172          * no 125Mhz clock input from SOC. In order to use RGMII,
 173          * We need enable AR8031 ouput a 125MHz clk from CLK_25M
 174          */
 175         miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
 176         miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
 177         miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
 178         miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
 179         val &= 0xffe3;
 180         val |= 0x18;
 181         miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
 182
 183         /* For the RGMII phy, we need enable tx clock delay */
 184         miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
 185         miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
 186         val |= 0x0100;
 187         miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
 188
 189         miiphy_write("FEC", phy, MII_BMCR, 0xa100);
 190
 191         return 0;
 192 }
 193
 194 int board_eth_init(bd_t *bis)
 195 {
 196         struct eth_device *dev;
 197         int ret = cpu_eth_init(bis);
 198
 199         if (ret)
 200                 return ret;
 201
 202         dev = eth_get_dev_by_name("FEC");
 203         if (!dev) {
 204                 printf("FEC MXC: Unable to get FEC device entry\n");
 205                 return -EINVAL;
 206         }
 207
 208         ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
 209         if (ret) {
 210                 printf("FEC MXC: Unable to register FEC mii postcall\n");
 211                 return ret;
 212         }
 213
 214         return 0;
 215 }
 216
 217 #ifdef CONFIG_USB_EHCI_MX6
 218 #define USB_OTHERREGS_OFFSET    0x800
 219 #define UCTRL_PWR_POL           (1 << 9)
 220
 221 static iomux_v3_cfg_t const usb_otg_pads[] = {
 222         MX6_PAD_EIM_D22__USB_OTG_PWR,
 223         MX6_PAD_GPIO_1__USB_OTG_ID,
 224 };
 225
 226 static void setup_usb(void)
 227 {
 228         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 229                                          ARRAY_SIZE(usb_otg_pads));
 230
 231         /*
 232          * set daisy chain for otg_pin_id on 6q.
 233          * for 6dl, this bit is reserved
 234          */
 235         imx_iomux_set_gpr_register(1, 13, 1, 1);
 236 }
 237
 238 int board_ehci_hcd_init(int port)
 239 {
 240         u32 *usbnc_usb_ctrl;
 241
 242         if (port > 0)
 243                 return -EINVAL;
 244
 245         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 246                                  port * 4);
 247
 248         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 249
 250         return 0;
 251 }
 252 #endif
 253
 254 int board_early_init_f(void)
 255 {
 256         setup_iomux_uart();
 257         setup_iomux_enet();
 258
 259         return 0;
 260 }
 261
 262 int board_init(void)
 263 {
 264         /* address of boot parameters */
 265         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 266
 267 #ifdef CONFIG_USB_EHCI_MX6
 268         setup_usb();
 269 #endif
 270
 271         return 0;
 272 }
 273
 274 int checkboard(void)
 275 {
 276 #ifdef CONFIG_SOC_MX6DL
 277         puts("Board: MX6DL-Armadillo2\n");
 278 #else
 279         puts("Board: MX6Q-Armadillo2\n");
 280 #endif
 281
 282         return 0;
 283 }