board/freescale/mx6qsabreauto/mx6qsabreauto.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/errno.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <asm/imx-common/boot_mode.h>
  20 #include <asm/imx-common/spi.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc.h>
  23 #include <miiphy.h>
  24 #include <netdev.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <i2c.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/imx-common/video.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <pca953x.h>
  31 #include <power/pmic.h>
  32 #include <power/pfuze100_pmic.h>
  33 #include "../common/pfuze.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  39         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  42         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47
  48 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  50         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  51
  52 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  53 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  54                         PAD_CTL_SRE_FAST)
  55 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  56
  57 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  58
  59 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
  60         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  61         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  62
  63 #define I2C_PMIC        1
  64
  65 int dram_init(void)
  66 {
  67         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  68
  69         return 0;
  70 }
  71
  72 static iomux_v3_cfg_t const uart4_pads[] = {
  73         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  74         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  75 };
  76
  77 static iomux_v3_cfg_t const enet_pads[] = {
  78         MX6_PAD_KEY_COL1__ENET_MDIO             | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_KEY_COL2__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93 };
  94
  95 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  96 static struct i2c_pads_info i2c_pad_info1 = {
  97         .scl = {
  98                 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  99                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
 100                 .gp = IMX_GPIO_NR(2, 30)
 101         },
 102         .sda = {
 103                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 104                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 105                 .gp = IMX_GPIO_NR(4, 13)
 106         }
 107 };
 108
 109 #ifndef CONFIG_SYS_FLASH_CFI
 110 /*
 111  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
 112  * Compass Sensor, Accelerometer, Res Touch
 113  */
 114 static struct i2c_pads_info i2c_pad_info2 = {
 115         .scl = {
 116                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
 117                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 118                 .gp = IMX_GPIO_NR(1, 3)
 119         },
 120         .sda = {
 121                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 122                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 123                 .gp = IMX_GPIO_NR(3, 18)
 124         }
 125 };
 126 #endif
 127
 128 static iomux_v3_cfg_t const i2c3_pads[] = {
 129         MX6_PAD_EIM_A24__GPIO5_IO04,
 130 };
 131
 132 static iomux_v3_cfg_t const port_exp[] = {
 133         MX6_PAD_SD2_DAT0__GPIO1_IO15,
 134 };
 135
 136 /*Define for building port exp gpio, pin starts from 0*/
 137 #define PORTEXP_IO_NR(chip, pin) \
 138         ((chip << 5) + pin)
 139
 140 /*Get the chip addr from a ioexp gpio*/
 141 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
 142         (gpio_nr >> 5)
 143
 144 /*Get the pin number from a ioexp gpio*/
 145 #define PORTEXP_IO_TO_PIN(gpio_nr) \
 146         (gpio_nr & 0x1f)
 147
 148 static int port_exp_direction_output(unsigned gpio, int value)
 149 {
 150         int ret;
 151
 152         i2c_set_bus_num(2);
 153         ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
 154         if (ret)
 155                 return ret;
 156
 157         ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
 158                 (1 << PORTEXP_IO_TO_PIN(gpio)),
 159                 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
 160
 161         if (ret)
 162                 return ret;
 163
 164         ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
 165                 (1 << PORTEXP_IO_TO_PIN(gpio)),
 166                 (value << PORTEXP_IO_TO_PIN(gpio)));
 167
 168         if (ret)
 169                 return ret;
 170
 171         return 0;
 172 }
 173
 174 static iomux_v3_cfg_t const eimnor_pads[] = {
 175         MX6_PAD_EIM_D16__EIM_DATA16     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 176         MX6_PAD_EIM_D17__EIM_DATA17     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 177         MX6_PAD_EIM_D18__EIM_DATA18     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 178         MX6_PAD_EIM_D19__EIM_DATA19     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 179         MX6_PAD_EIM_D20__EIM_DATA20     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 180         MX6_PAD_EIM_D21__EIM_DATA21     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 181         MX6_PAD_EIM_D22__EIM_DATA22     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 182         MX6_PAD_EIM_D23__EIM_DATA23     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 183         MX6_PAD_EIM_D24__EIM_DATA24     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 184         MX6_PAD_EIM_D25__EIM_DATA25     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 185         MX6_PAD_EIM_D26__EIM_DATA26     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 186         MX6_PAD_EIM_D27__EIM_DATA27     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 187         MX6_PAD_EIM_D28__EIM_DATA28     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 188         MX6_PAD_EIM_D29__EIM_DATA29     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 189         MX6_PAD_EIM_D30__EIM_DATA30     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 190         MX6_PAD_EIM_D31__EIM_DATA31     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 191         MX6_PAD_EIM_DA0__EIM_AD00       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 192         MX6_PAD_EIM_DA1__EIM_AD01       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 193         MX6_PAD_EIM_DA2__EIM_AD02       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 194         MX6_PAD_EIM_DA3__EIM_AD03       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 195         MX6_PAD_EIM_DA4__EIM_AD04       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 196         MX6_PAD_EIM_DA5__EIM_AD05       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 197         MX6_PAD_EIM_DA6__EIM_AD06       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 198         MX6_PAD_EIM_DA7__EIM_AD07       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 199         MX6_PAD_EIM_DA8__EIM_AD08       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 200         MX6_PAD_EIM_DA9__EIM_AD09       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 201         MX6_PAD_EIM_DA10__EIM_AD10      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 202         MX6_PAD_EIM_DA11__EIM_AD11      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
 203         MX6_PAD_EIM_DA12__EIM_AD12      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 204         MX6_PAD_EIM_DA13__EIM_AD13      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 205         MX6_PAD_EIM_DA14__EIM_AD14      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 206         MX6_PAD_EIM_DA15__EIM_AD15      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 207         MX6_PAD_EIM_A16__EIM_ADDR16     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 208         MX6_PAD_EIM_A17__EIM_ADDR17     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 209         MX6_PAD_EIM_A18__EIM_ADDR18     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 210         MX6_PAD_EIM_A19__EIM_ADDR19     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 211         MX6_PAD_EIM_A20__EIM_ADDR20     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 212         MX6_PAD_EIM_A21__EIM_ADDR21     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 213         MX6_PAD_EIM_A22__EIM_ADDR22     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 214         MX6_PAD_EIM_A23__EIM_ADDR23     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 215         MX6_PAD_EIM_OE__EIM_OE_B,
 216         MX6_PAD_EIM_RW__EIM_RW,
 217         MX6_PAD_EIM_CS0__EIM_CS0_B,
 218 };
 219
 220 static void eimnor_cs_setup(void)
 221 {
 222         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 223
 224         writel(0x00020181, &weim_regs->cs0gcr1);
 225         writel(0x00000001, &weim_regs->cs0gcr2);
 226         writel(0x0a020000, &weim_regs->cs0rcr1);
 227         writel(0x0000c000, &weim_regs->cs0rcr2);
 228         writel(0x0804a240, &weim_regs->cs0wcr1);
 229         writel(0x00000120, &weim_regs->wcr);
 230
 231         set_chipselect_size(CS0_128);
 232 }
 233
 234 static void setup_iomux_eimnor(void)
 235 {
 236         imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
 237
 238         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 239
 240         eimnor_cs_setup();
 241 }
 242
 243 static void setup_iomux_enet(void)
 244 {
 245         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 246 }
 247
 248 static iomux_v3_cfg_t const usdhc3_pads[] = {
 249         MX6_PAD_SD3_CLK__SD3_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 250         MX6_PAD_SD3_CMD__SD3_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 251         MX6_PAD_SD3_DAT0__SD3_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 252         MX6_PAD_SD3_DAT1__SD3_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 253         MX6_PAD_SD3_DAT2__SD3_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 254         MX6_PAD_SD3_DAT3__SD3_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 255         MX6_PAD_SD3_DAT4__SD3_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 256         MX6_PAD_SD3_DAT5__SD3_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 257         MX6_PAD_SD3_DAT6__SD3_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 258         MX6_PAD_SD3_DAT7__SD3_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 259         MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 260         MX6_PAD_NANDF_CS2__GPIO6_IO15,
 261 };
 262
 263 static void setup_iomux_uart(void)
 264 {
 265         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 266 }
 267
 268 #ifdef CONFIG_FSL_ESDHC
 269 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 270         {USDHC3_BASE_ADDR},
 271 };
 272
 273 int board_mmc_getcd(struct mmc *mmc)
 274 {
 275         gpio_direction_input(IMX_GPIO_NR(6, 15));
 276         return !gpio_get_value(IMX_GPIO_NR(6, 15));
 277 }
 278
 279 int board_mmc_init(bd_t *bis)
 280 {
 281         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 282
 283         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 284         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 285 }
 286 #endif
 287
 288 #ifdef CONFIG_NAND_MXS
 289 static iomux_v3_cfg_t gpmi_pads[] = {
 290         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 291         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 292         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 293         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
 294         MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 295         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 296         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 297         MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 298         MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 299         MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 300         MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 301         MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 302         MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 303         MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 304         MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 305         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
 306 };
 307
 308 static void setup_gpmi_nand(void)
 309 {
 310         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 311
 312         /* config gpmi nand iomux */
 313         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 314
 315         setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 316                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 317                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
 318
 319         /* enable apbh clock gating */
 320         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 321 }
 322 #endif
 323
 324 int mx6_rgmii_rework(struct phy_device *phydev)
 325 {
 326         unsigned short val;
 327
 328         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 329         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 330         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 331         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 332
 333         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 334         val &= 0xffe3;
 335         val |= 0x18;
 336         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 337
 338         /* introduce tx clock delay */
 339         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 340         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 341         val |= 0x0100;
 342         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 343
 344         return 0;
 345 }
 346
 347 int board_phy_config(struct phy_device *phydev)
 348 {
 349         mx6_rgmii_rework(phydev);
 350
 351         if (phydev->drv->config)
 352                 phydev->drv->config(phydev);
 353
 354         return 0;
 355 }
 356
 357 static void setup_fec(void)
 358 {
 359         if (is_mx6dqp()) {
 360                 /*
 361                  * select ENET MAC0 TX clock from PLL
 362                  */
 363                 imx_iomux_set_gpr_register(5, 9, 1, 1);
 364                 enable_fec_anatop_clock(ENET_125MHZ);
 365         }
 366
 367         setup_iomux_enet();
 368 }
 369
 370 int board_eth_init(bd_t *bis)
 371 {
 372         setup_fec();
 373
 374         return cpu_eth_init(bis);
 375 }
 376
 377 #define BOARD_REV_B  0x200
 378 #define BOARD_REV_A  0x100
 379
 380 static int mx6sabre_rev(void)
 381 {
 382         /*
 383          * Get Board ID information from OCOTP_GP1[15:8]
 384          * i.MX6Q ARD RevA: 0x01
 385          * i.MX6Q ARD RevB: 0x02
 386          */
 387         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 388         struct fuse_bank *bank = &ocotp->bank[4];
 389         struct fuse_bank4_regs *fuse =
 390                         (struct fuse_bank4_regs *)bank->fuse_regs;
 391         int reg = readl(&fuse->gp1);
 392         int ret;
 393
 394         switch (reg >> 8 & 0x0F) {
 395         case 0x02:
 396                 ret = BOARD_REV_B;
 397                 break;
 398         case 0x01:
 399         default:
 400                 ret = BOARD_REV_A;
 401                 break;
 402         }
 403
 404         return ret;
 405 }
 406
 407 u32 get_board_rev(void)
 408 {
 409         int rev = mx6sabre_rev();
 410
 411         return (get_cpu_rev() & ~(0xF << 8)) | rev;
 412 }
 413
 414 #if defined(CONFIG_VIDEO_IPUV3)
 415 static void do_enable_hdmi(struct display_info_t const *dev)
 416 {
 417         imx_enable_hdmi_phy();
 418 }
 419
 420 struct display_info_t const displays[] = {{
 421         .bus    = -1,
 422         .addr   = 0,
 423         .pixfmt = IPU_PIX_FMT_RGB24,
 424         .detect = detect_hdmi,
 425         .enable = do_enable_hdmi,
 426         .mode   = {
 427                 .name           = "HDMI",
 428                 .refresh        = 60,
 429                 .xres           = 1024,
 430                 .yres           = 768,
 431                 .pixclock       = 15385,
 432                 .left_margin    = 220,
 433                 .right_margin   = 40,
 434                 .upper_margin   = 21,
 435                 .lower_margin   = 7,
 436                 .hsync_len      = 60,
 437                 .vsync_len      = 10,
 438                 .sync           = FB_SYNC_EXT,
 439                 .vmode          = FB_VMODE_NONINTERLACED,
 440 } } };
 441 size_t display_count = ARRAY_SIZE(displays);
 442
 443 static void setup_display(void)
 444 {
 445         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 446         int reg;
 447
 448         enable_ipu_clock();
 449         imx_setup_hdmi();
 450
 451         reg = readl(&mxc_ccm->chsccdr);
 452         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 453                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 454         writel(reg, &mxc_ccm->chsccdr);
 455 }
 456 #endif /* CONFIG_VIDEO_IPUV3 */
 457
 458 /*
 459  * Do not overwrite the console
 460  * Use always serial for U-Boot console
 461  */
 462 int overwrite_console(void)
 463 {
 464         return 1;
 465 }
 466
 467 int board_early_init_f(void)
 468 {
 469         setup_iomux_uart();
 470 #ifdef CONFIG_VIDEO_IPUV3
 471         setup_display();
 472 #endif
 473
 474 #ifdef CONFIG_NAND_MXS
 475         setup_gpmi_nand();
 476 #endif
 477
 478         return 0;
 479 }
 480
 481 int board_init(void)
 482 {
 483         /* address of boot parameters */
 484         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 485
 486         /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
 487         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 488         /* I2C 3 Steer */
 489         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 490         imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 491 #ifndef CONFIG_SYS_FLASH_CFI
 492         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 493 #endif
 494         gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 495         imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
 496
 497         setup_iomux_eimnor();
 498         return 0;
 499 }
 500
 501 #ifdef CONFIG_MXC_SPI
 502 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 503 {
 504         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 505 }
 506 #endif
 507
 508 int power_init_board(void)
 509 {
 510         struct pmic *p;
 511         unsigned int value;
 512
 513         p = pfuze_common_init(I2C_PMIC);
 514         if (!p)
 515                 return -ENODEV;
 516
 517         if (is_mx6dqp()) {
 518                 /* set SW2 staby volatage 0.975V*/
 519                 pmic_reg_read(p, PFUZE100_SW2STBY, &value);
 520                 value &= ~0x3f;
 521                 value |= 0x17;
 522                 pmic_reg_write(p, PFUZE100_SW2STBY, value);
 523         }
 524
 525         return pfuze_mode_init(p, APS_PFM);
 526 }
 527
 528 #ifdef CONFIG_CMD_BMODE
 529 static const struct boot_mode board_boot_modes[] = {
 530         /* 4 bit bus width */
 531         {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 532         {NULL,   0},
 533 };
 534 #endif
 535
 536 int board_late_init(void)
 537 {
 538 #ifdef CONFIG_CMD_BMODE
 539         add_board_boot_modes(board_boot_modes);
 540 #endif
 541
 542 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 543         setenv("board_name", "SABREAUTO");
 544
 545         if (is_mx6dqp())
 546                 setenv("board_rev", "MX6QP");
 547         else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 548                 setenv("board_rev", "MX6Q");
 549         else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
 550                 setenv("board_rev", "MX6DL");
 551 #endif
 552
 553         return 0;
 554 }
 555
 556 int checkboard(void)
 557 {
 558         int rev = mx6sabre_rev();
 559         char *revname;
 560
 561         switch (rev) {
 562         case BOARD_REV_B:
 563                 revname = "B";
 564                 break;
 565         case BOARD_REV_A:
 566         default:
 567                 revname = "A";
 568                 break;
 569         }
 570
 571         printf("Board: MX6Q-Sabreauto rev%s\n", revname);
 572
 573         return 0;
 574 }
 575
 576 #ifdef CONFIG_USB_EHCI_MX6
 577 #define USB_HOST1_PWR     PORTEXP_IO_NR(0x32, 7)
 578 #define USB_OTG_PWR       PORTEXP_IO_NR(0x34, 1)
 579
 580 iomux_v3_cfg_t const usb_otg_pads[] = {
 581         MX6_PAD_ENET_RX_ER__USB_OTG_ID,
 582 };
 583
 584 int board_ehci_hcd_init(int port)
 585 {
 586         switch (port) {
 587         case 0:
 588                 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 589                         ARRAY_SIZE(usb_otg_pads));
 590
 591                 /*
 592                   * Set daisy chain for otg_pin_id on 6q.
 593                  *  For 6dl, this bit is reserved.
 594                  */
 595                 imx_iomux_set_gpr_register(1, 13, 1, 0);
 596                 break;
 597         case 1:
 598                 break;
 599         default:
 600                 printf("MXC USB port %d not yet supported\n", port);
 601                 return -EINVAL;
 602         }
 603         return 0;
 604 }
 605
 606 int board_ehci_power(int port, int on)
 607 {
 608         switch (port) {
 609         case 0:
 610                 if (on)
 611                         port_exp_direction_output(USB_OTG_PWR, 1);
 612                 else
 613                         port_exp_direction_output(USB_OTG_PWR, 0);
 614                 break;
 615         case 1:
 616                 if (on)
 617                         port_exp_direction_output(USB_HOST1_PWR, 1);
 618                 else
 619                         port_exp_direction_output(USB_HOST1_PWR, 0);
 620                 break;
 621         default:
 622                 printf("MXC USB port %d not yet supported\n", port);
 623                 return -EINVAL;
 624         }
 625
 626         return 0;
 627 }
 628 #endif