board/freescale/mx6qsabreauto/mx6qsabreauto.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/errno.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <asm/imx-common/boot_mode.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc.h>
  22 #include <miiphy.h>
  23 #include <netdev.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <i2c.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  30         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  31         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  34         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  35         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  39
  40 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  42         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  43
  44 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  45
  46 int dram_init(void)
  47 {
  48         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  49
  50         return 0;
  51 }
  52
  53 iomux_v3_cfg_t const uart4_pads[] = {
  54         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  55         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  56 };
  57
  58 iomux_v3_cfg_t const enet_pads[] = {
  59         MX6_PAD_KEY_COL1__ENET_MDIO             | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60         MX6_PAD_KEY_COL2__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74 };
  75
  76 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  77 struct i2c_pads_info i2c_pad_info1 = {
  78         .scl = {
  79                 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  80                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  81                 .gp = IMX_GPIO_NR(2, 30)
  82         },
  83         .sda = {
  84                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  85                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  86                 .gp = IMX_GPIO_NR(4, 13)
  87         }
  88 };
  89
  90 /*
  91  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  92  * Compass Sensor, Accelerometer, Res Touch
  93  */
  94 struct i2c_pads_info i2c_pad_info2 = {
  95         .scl = {
  96                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
  97                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
  98                 .gp = IMX_GPIO_NR(1, 3)
  99         },
 100         .sda = {
 101                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 102                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 103                 .gp = IMX_GPIO_NR(3, 18)
 104         }
 105 };
 106
 107 iomux_v3_cfg_t const i2c3_pads[] = {
 108         MX6_PAD_EIM_A24__GPIO5_IO04             | MUX_PAD_CTRL(NO_PAD_CTRL),
 109 };
 110
 111 iomux_v3_cfg_t const port_exp[] = {
 112         MX6_PAD_SD2_DAT0__GPIO1_IO15            | MUX_PAD_CTRL(NO_PAD_CTRL),
 113 };
 114
 115 static void setup_iomux_enet(void)
 116 {
 117         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 118 }
 119
 120 iomux_v3_cfg_t const usdhc3_pads[] = {
 121         MX6_PAD_SD3_CLK__SD3_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD3_CMD__SD3_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD3_DAT0__SD3_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD3_DAT1__SD3_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT2__SD3_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT3__SD3_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT4__SD3_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT5__SD3_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT6__SD3_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT7__SD3_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(NO_PAD_CTRL),
 133 };
 134
 135 static void setup_iomux_uart(void)
 136 {
 137         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 138 }
 139
 140 #ifdef CONFIG_FSL_ESDHC
 141 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 142         {USDHC3_BASE_ADDR},
 143 };
 144
 145 int board_mmc_getcd(struct mmc *mmc)
 146 {
 147         gpio_direction_input(IMX_GPIO_NR(6, 15));
 148         return !gpio_get_value(IMX_GPIO_NR(6, 15));
 149 }
 150
 151 int board_mmc_init(bd_t *bis)
 152 {
 153         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 154
 155         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 156         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 157 }
 158 #endif
 159
 160 int mx6_rgmii_rework(struct phy_device *phydev)
 161 {
 162         unsigned short val;
 163
 164         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 165         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 166         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 167         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 168
 169         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 170         val &= 0xffe3;
 171         val |= 0x18;
 172         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 173
 174         /* introduce tx clock delay */
 175         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 176         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 177         val |= 0x0100;
 178         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 179
 180         return 0;
 181 }
 182
 183 int board_phy_config(struct phy_device *phydev)
 184 {
 185         mx6_rgmii_rework(phydev);
 186
 187         if (phydev->drv->config)
 188                 phydev->drv->config(phydev);
 189
 190         return 0;
 191 }
 192
 193 int board_eth_init(bd_t *bis)
 194 {
 195         setup_iomux_enet();
 196
 197         return cpu_eth_init(bis);
 198 }
 199
 200 #define BOARD_REV_B  0x200
 201 #define BOARD_REV_A  0x100
 202
 203 static int mx6sabre_rev(void)
 204 {
 205         /*
 206          * Get Board ID information from OCOTP_GP1[15:8]
 207          * i.MX6Q ARD RevA: 0x01
 208          * i.MX6Q ARD RevB: 0x02
 209          */
 210         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 211         struct fuse_bank *bank = &ocotp->bank[4];
 212         struct fuse_bank4_regs *fuse =
 213                         (struct fuse_bank4_regs *)bank->fuse_regs;
 214         int reg = readl(&fuse->gp1);
 215         int ret;
 216
 217         switch (reg >> 8 & 0x0F) {
 218         case 0x02:
 219                 ret = BOARD_REV_B;
 220                 break;
 221         case 0x01:
 222         default:
 223                 ret = BOARD_REV_A;
 224                 break;
 225         }
 226
 227         return ret;
 228 }
 229
 230 u32 get_board_rev(void)
 231 {
 232         int rev = mx6sabre_rev();
 233
 234         return (get_cpu_rev() & ~(0xF << 8)) | rev;
 235 }
 236
 237 int board_early_init_f(void)
 238 {
 239         setup_iomux_uart();
 240
 241         return 0;
 242 }
 243
 244 int board_init(void)
 245 {
 246         /* address of boot parameters */
 247         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 248
 249         /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
 250         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 251         /* I2C 3 Steer */
 252         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 253         imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 254         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 255
 256         gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 257         imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
 258
 259         return 0;
 260 }
 261
 262 #ifdef CONFIG_MXC_SPI
 263 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 264 {
 265         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 266 }
 267 #endif
 268
 269 #ifdef CONFIG_CMD_BMODE
 270 static const struct boot_mode board_boot_modes[] = {
 271         /* 4 bit bus width */
 272         {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 273         {NULL,   0},
 274 };
 275 #endif
 276
 277 int board_late_init(void)
 278 {
 279 #ifdef CONFIG_CMD_BMODE
 280         add_board_boot_modes(board_boot_modes);
 281 #endif
 282
 283         return 0;
 284 }
 285
 286 int checkboard(void)
 287 {
 288         int rev = mx6sabre_rev();
 289         char *revname;
 290
 291         switch (rev) {
 292         case BOARD_REV_B:
 293                 revname = "B";
 294                 break;
 295         case BOARD_REV_A:
 296         default:
 297                 revname = "A";
 298                 break;
 299         }
 300
 301         printf("Board: MX6Q-Sabreauto rev%s\n", revname);
 302
 303         return 0;
 304 }