board/freescale/t4qds/eth.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <netdev.h>
  10 #include <asm/mmu.h>
  11 #include <asm/processor.h>
  12 #include <asm/cache.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/fsl_law.h>
  15 #include <fsl_ddr_sdram.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <malloc.h>
  20 #include <fm_eth.h>
  21 #include <fsl_mdio.h>
  22 #include <miiphy.h>
  23 #include <phy.h>
  24 #include <asm/fsl_dtsec.h>
  25 #include <asm/fsl_serdes.h>
  26 #include "../common/qixis.h"
  27 #include "../common/fman.h"
  28
  29 #include "t4240qds_qixis.h"
  30
  31 #define EMI_NONE        0xFFFFFFFF
  32 #define EMI1_RGMII      0
  33 #define EMI1_SLOT1      1
  34 #define EMI1_SLOT2      2
  35 #define EMI1_SLOT3      3
  36 #define EMI1_SLOT4      4
  37 #define EMI1_SLOT5      5
  38 #define EMI1_SLOT7      7
  39 #define EMI2            8
  40 /* Slot6 and Slot8 do not have EMI connections */
  41
  42 static int mdio_mux[NUM_FM_PORTS];
  43
  44 static const char *mdio_names[] = {
  45         "T4240QDS_MDIO0",
  46         "T4240QDS_MDIO1",
  47         "T4240QDS_MDIO2",
  48         "T4240QDS_MDIO3",
  49         "T4240QDS_MDIO4",
  50         "T4240QDS_MDIO5",
  51         "NULL",
  52         "T4240QDS_MDIO7",
  53         "T4240QDS_10GC",
  54 };
  55
  56 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  57 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  58 static u8 slot_qsgmii_phyaddr[5][4] = {
  59         {0, 0, 0, 0},/* not used, to make index match slot No. */
  60         {0, 1, 2, 3},
  61         {4, 5, 6, 7},
  62         {8, 9, 0xa, 0xb},
  63         {0xc, 0xd, 0xe, 0xf},
  64 };
  65 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
  66
  67 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  68 {
  69         return mdio_names[muxval];
  70 }
  71
  72 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  73 {
  74         struct mii_dev *bus;
  75         const char *name = t4240qds_mdio_name_for_muxval(muxval);
  76
  77         if (!name) {
  78                 printf("No bus for muxval %x\n", muxval);
  79                 return NULL;
  80         }
  81
  82         bus = miiphy_get_dev_by_name(name);
  83
  84         if (!bus) {
  85                 printf("No bus by name %s\n", name);
  86                 return NULL;
  87         }
  88
  89         return bus;
  90 }
  91
  92 struct t4240qds_mdio {
  93         u8 muxval;
  94         struct mii_dev *realbus;
  95 };
  96
  97 static void t4240qds_mux_mdio(u8 muxval)
  98 {
  99         u8 brdcfg4;
 100         if ((muxval < 6) || (muxval == 7)) {
 101                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 102                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 103                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 104                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 105         }
 106 }
 107
 108 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
 109                                 int regnum)
 110 {
 111         struct t4240qds_mdio *priv = bus->priv;
 112
 113         t4240qds_mux_mdio(priv->muxval);
 114
 115         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 116 }
 117
 118 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 119                                 int regnum, u16 value)
 120 {
 121         struct t4240qds_mdio *priv = bus->priv;
 122
 123         t4240qds_mux_mdio(priv->muxval);
 124
 125         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 126 }
 127
 128 static int t4240qds_mdio_reset(struct mii_dev *bus)
 129 {
 130         struct t4240qds_mdio *priv = bus->priv;
 131
 132         return priv->realbus->reset(priv->realbus);
 133 }
 134
 135 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 136 {
 137         struct t4240qds_mdio *pmdio;
 138         struct mii_dev *bus = mdio_alloc();
 139
 140         if (!bus) {
 141                 printf("Failed to allocate T4240QDS MDIO bus\n");
 142                 return -1;
 143         }
 144
 145         pmdio = malloc(sizeof(*pmdio));
 146         if (!pmdio) {
 147                 printf("Failed to allocate T4240QDS private data\n");
 148                 free(bus);
 149                 return -1;
 150         }
 151
 152         bus->read = t4240qds_mdio_read;
 153         bus->write = t4240qds_mdio_write;
 154         bus->reset = t4240qds_mdio_reset;
 155         sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
 156
 157         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 158
 159         if (!pmdio->realbus) {
 160                 printf("No bus with name %s\n", realbusname);
 161                 free(bus);
 162                 free(pmdio);
 163                 return -1;
 164         }
 165
 166         pmdio->muxval = muxval;
 167         bus->priv = pmdio;
 168
 169         return mdio_register(bus);
 170 }
 171
 172 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 173                                 enum fm_port port, int offset)
 174 {
 175         int interface = fm_info_get_enet_if(port);
 176
 177         if (interface == PHY_INTERFACE_MODE_SGMII ||
 178             interface == PHY_INTERFACE_MODE_QSGMII) {
 179                 switch (port) {
 180                 case FM1_DTSEC1:
 181                         if (qsgmiiphy_fix[port])
 182                                 fdt_set_phy_handle(blob, prop, pa,
 183                                                    "sgmii_phy21");
 184                         break;
 185                 case FM1_DTSEC2:
 186                         if (qsgmiiphy_fix[port])
 187                                 fdt_set_phy_handle(blob, prop, pa,
 188                                                    "sgmii_phy22");
 189                         break;
 190                 case FM1_DTSEC3:
 191                         if (qsgmiiphy_fix[port])
 192                                 fdt_set_phy_handle(blob, prop, pa,
 193                                                    "sgmii_phy23");
 194                         break;
 195                 case FM1_DTSEC4:
 196                         if (qsgmiiphy_fix[port])
 197                                 fdt_set_phy_handle(blob, prop, pa,
 198                                                    "sgmii_phy24");
 199                         break;
 200                 case FM1_DTSEC6:
 201                         if (qsgmiiphy_fix[port])
 202                                 fdt_set_phy_handle(blob, prop, pa,
 203                                                    "sgmii_phy12");
 204                         break;
 205                 case FM1_DTSEC9:
 206                         if (qsgmiiphy_fix[port])
 207                                 fdt_set_phy_handle(blob, prop, pa,
 208                                                    "sgmii_phy14");
 209                         else
 210                                 fdt_set_phy_handle(blob, prop, pa,
 211                                                    "phy_sgmii4");
 212                         break;
 213                 case FM1_DTSEC10:
 214                         if (qsgmiiphy_fix[port])
 215                                 fdt_set_phy_handle(blob, prop, pa,
 216                                                    "sgmii_phy13");
 217                         else
 218                                 fdt_set_phy_handle(blob, prop, pa,
 219                                                    "phy_sgmii3");
 220                         break;
 221                 case FM2_DTSEC1:
 222                         if (qsgmiiphy_fix[port])
 223                                 fdt_set_phy_handle(blob, prop, pa,
 224                                                    "sgmii_phy41");
 225                         break;
 226                 case FM2_DTSEC2:
 227                         if (qsgmiiphy_fix[port])
 228                                 fdt_set_phy_handle(blob, prop, pa,
 229                                                    "sgmii_phy42");
 230                         break;
 231                 case FM2_DTSEC3:
 232                         if (qsgmiiphy_fix[port])
 233                                 fdt_set_phy_handle(blob, prop, pa,
 234                                                    "sgmii_phy43");
 235                         break;
 236                 case FM2_DTSEC4:
 237                         if (qsgmiiphy_fix[port])
 238                                 fdt_set_phy_handle(blob, prop, pa,
 239                                                    "sgmii_phy44");
 240                         break;
 241                 case FM2_DTSEC6:
 242                         if (qsgmiiphy_fix[port])
 243                                 fdt_set_phy_handle(blob, prop, pa,
 244                                                    "sgmii_phy32");
 245                         break;
 246                 case FM2_DTSEC9:
 247                         if (qsgmiiphy_fix[port])
 248                                 fdt_set_phy_handle(blob, prop, pa,
 249                                                    "sgmii_phy34");
 250                         else
 251                                 fdt_set_phy_handle(blob, prop, pa,
 252                                                    "phy_sgmii12");
 253                         break;
 254                 case FM2_DTSEC10:
 255                         if (qsgmiiphy_fix[port])
 256                                 fdt_set_phy_handle(blob, prop, pa,
 257                                                    "sgmii_phy33");
 258                         else
 259                                 fdt_set_phy_handle(blob, prop, pa,
 260                                                    "phy_sgmii11");
 261                         break;
 262                 default:
 263                         break;
 264                 }
 265         }
 266 }
 267
 268 void fdt_fixup_board_enet(void *fdt)
 269 {
 270         int i;
 271         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 272         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 273
 274         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 275         for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 276                 switch (fm_info_get_enet_if(i)) {
 277                 case PHY_INTERFACE_MODE_SGMII:
 278                 case PHY_INTERFACE_MODE_QSGMII:
 279                         switch (mdio_mux[i]) {
 280                         case EMI1_SLOT1:
 281                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 282                                 break;
 283                         case EMI1_SLOT2:
 284                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 285                                 break;
 286                         case EMI1_SLOT3:
 287                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 288                                 break;
 289                         case EMI1_SLOT4:
 290                                 fdt_status_okay_by_alias(fdt, "emi1_slot4");
 291                                 break;
 292                         default:
 293                                 break;
 294                         }
 295                         break;
 296                 case PHY_INTERFACE_MODE_XGMII:
 297                         /* check if it's XFI interface for 10g */
 298                         if ((prtcl2 == 56) || (prtcl2 == 57)) {
 299                                 fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
 300                                 break;
 301                         }
 302                         switch (i) {
 303                         case FM1_10GEC1:
 304                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
 305                                 break;
 306                         case FM1_10GEC2:
 307                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
 308                                 break;
 309                         case FM2_10GEC1:
 310                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
 311                                 break;
 312                         case FM2_10GEC2:
 313                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
 314                                 break;
 315                         default:
 316                                 break;
 317                         }
 318                         break;
 319                 default:
 320                         break;
 321                 }
 322         }
 323 }
 324
 325 static void initialize_qsgmiiphy_fix(void)
 326 {
 327         int i;
 328         unsigned short reg;
 329
 330         for (i = 1; i <= 4; i++) {
 331                 /*
 332                  * Try to read if a SGMII card is used, we do it slot by slot.
 333                  * if a SGMII PHY address is valid on a slot, then we mark
 334                  * all ports on the slot, then fix the PHY address for the
 335                  * marked port when doing dtb fixup.
 336                  */
 337                 if (miiphy_read(mdio_names[i],
 338                                 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
 339                         debug("Slot%d PHY ID register 2 read failed\n", i);
 340                         continue;
 341                 }
 342
 343                 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
 344
 345                 if (reg == 0xFFFF) {
 346                         /* No physical device present at this address */
 347                         continue;
 348                 }
 349
 350                 switch (i) {
 351                 case 1:
 352                         qsgmiiphy_fix[FM1_DTSEC5] = 1;
 353                         qsgmiiphy_fix[FM1_DTSEC6] = 1;
 354                         qsgmiiphy_fix[FM1_DTSEC9] = 1;
 355                         qsgmiiphy_fix[FM1_DTSEC10] = 1;
 356                         slot_qsgmii_phyaddr[1][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 357                         slot_qsgmii_phyaddr[1][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 358                         slot_qsgmii_phyaddr[1][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 359                         slot_qsgmii_phyaddr[1][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 360                         break;
 361                 case 2:
 362                         qsgmiiphy_fix[FM1_DTSEC1] = 1;
 363                         qsgmiiphy_fix[FM1_DTSEC2] = 1;
 364                         qsgmiiphy_fix[FM1_DTSEC3] = 1;
 365                         qsgmiiphy_fix[FM1_DTSEC4] = 1;
 366                         slot_qsgmii_phyaddr[2][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 367                         slot_qsgmii_phyaddr[2][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 368                         slot_qsgmii_phyaddr[2][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 369                         slot_qsgmii_phyaddr[2][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 370                         break;
 371                 case 3:
 372                         qsgmiiphy_fix[FM2_DTSEC5] = 1;
 373                         qsgmiiphy_fix[FM2_DTSEC6] = 1;
 374                         qsgmiiphy_fix[FM2_DTSEC9] = 1;
 375                         qsgmiiphy_fix[FM2_DTSEC10] = 1;
 376                         slot_qsgmii_phyaddr[3][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 377                         slot_qsgmii_phyaddr[3][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 378                         slot_qsgmii_phyaddr[3][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 379                         slot_qsgmii_phyaddr[3][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 380                         break;
 381                 case 4:
 382                         qsgmiiphy_fix[FM2_DTSEC1] = 1;
 383                         qsgmiiphy_fix[FM2_DTSEC2] = 1;
 384                         qsgmiiphy_fix[FM2_DTSEC3] = 1;
 385                         qsgmiiphy_fix[FM2_DTSEC4] = 1;
 386                         slot_qsgmii_phyaddr[4][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 387                         slot_qsgmii_phyaddr[4][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 388                         slot_qsgmii_phyaddr[4][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 389                         slot_qsgmii_phyaddr[4][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 390                         break;
 391                 default:
 392                         break;
 393                 }
 394         }
 395 }
 396
 397 int board_eth_init(bd_t *bis)
 398 {
 399 #if defined(CONFIG_FMAN_ENET)
 400         int i, idx, lane, slot, interface;
 401         struct memac_mdio_info dtsec_mdio_info;
 402         struct memac_mdio_info tgec_mdio_info;
 403         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 404         u32 srds_prtcl_s1, srds_prtcl_s2;
 405
 406         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 407                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 408         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 409         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 410                                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 411         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 412
 413         /* Initialize the mdio_mux array so we can recognize empty elements */
 414         for (i = 0; i < NUM_FM_PORTS; i++)
 415                 mdio_mux[i] = EMI_NONE;
 416
 417         dtsec_mdio_info.regs =
 418                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
 419
 420         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 421
 422         /* Register the 1G MDIO bus */
 423         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 424
 425         tgec_mdio_info.regs =
 426                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
 427         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 428
 429         /* Register the 10G MDIO bus */
 430         fm_memac_mdio_init(bis, &tgec_mdio_info);
 431
 432         /* Register the muxing front-ends to the MDIO buses */
 433         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
 434         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 435         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 436         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 437         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 438         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 439         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 440         t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 441
 442         initialize_qsgmiiphy_fix();
 443
 444         switch (srds_prtcl_s1) {
 445         case 1:
 446         case 2:
 447         case 4:
 448                 /* XAUI/HiGig in Slot1 and Slot2 */
 449                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 450                 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 451                 break;
 452         case 27:
 453         case 28:
 454         case 35:
 455         case 36:
 456                 /* SGMII in Slot1 and Slot2 */
 457                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 458                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 459                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 460                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 461                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 462                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 463                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 464                         fm_info_set_phy_address(FM1_DTSEC9,
 465                                                 slot_qsgmii_phyaddr[1][3]);
 466                         fm_info_set_phy_address(FM1_DTSEC10,
 467                                                 slot_qsgmii_phyaddr[1][2]);
 468                 }
 469                 break;
 470         case 37:
 471         case 38:
 472                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 473                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 474                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 475                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 476                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 477                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 478                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 479                         fm_info_set_phy_address(FM1_DTSEC9,
 480                                                 slot_qsgmii_phyaddr[1][2]);
 481                         fm_info_set_phy_address(FM1_DTSEC10,
 482                                                 slot_qsgmii_phyaddr[1][3]);
 483                 }
 484                 break;
 485         case 39:
 486         case 40:
 487         case 45:
 488         case 46:
 489         case 47:
 490         case 48:
 491                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 492                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 493                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 494                         fm_info_set_phy_address(FM1_DTSEC10,
 495                                                 slot_qsgmii_phyaddr[1][2]);
 496                         fm_info_set_phy_address(FM1_DTSEC9,
 497                                                 slot_qsgmii_phyaddr[1][3]);
 498                 }
 499                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 500                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 501                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 502                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 503                 break;
 504         default:
 505                 puts("Invalid SerDes1 protocol for T4240QDS\n");
 506                 break;
 507         }
 508
 509         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 510                 idx = i - FM1_DTSEC1;
 511                 interface = fm_info_get_enet_if(i);
 512                 switch (interface) {
 513                 case PHY_INTERFACE_MODE_SGMII:
 514                 case PHY_INTERFACE_MODE_QSGMII:
 515                         if (interface == PHY_INTERFACE_MODE_QSGMII) {
 516                                 if (idx <= 3)
 517                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 518                                                         QSGMII_FM1_A);
 519                                 else
 520                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 521                                                         QSGMII_FM1_B);
 522                                 if (lane < 0)
 523                                         break;
 524                                 slot = lane_to_slot_fsm1[lane];
 525                                 debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
 526                                       idx + 1, slot);
 527                         } else {
 528                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 529                                                 SGMII_FM1_DTSEC1 + idx);
 530                                 if (lane < 0)
 531                                         break;
 532                                 slot = lane_to_slot_fsm1[lane];
 533                                 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 534                                       idx + 1, slot);
 535                         }
 536                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 537                                 fm_disable_port(i);
 538                         switch (slot) {
 539                         case 1:
 540                                 mdio_mux[i] = EMI1_SLOT1;
 541                                 fm_info_set_mdio(i,
 542                                         mii_dev_for_muxval(mdio_mux[i]));
 543                                 break;
 544                         case 2:
 545                                 mdio_mux[i] = EMI1_SLOT2;
 546                                 fm_info_set_mdio(i,
 547                                         mii_dev_for_muxval(mdio_mux[i]));
 548                                 break;
 549                         };
 550                         break;
 551                 case PHY_INTERFACE_MODE_RGMII:
 552                         /* FM1 DTSEC5 routes to RGMII with EC2 */
 553                         debug("FM1@DTSEC%u is RGMII at address %u\n",
 554                                 idx + 1, 2);
 555                         if (i == FM1_DTSEC5)
 556                                 fm_info_set_phy_address(i, 2);
 557                         mdio_mux[i] = EMI1_RGMII;
 558                         fm_info_set_mdio(i,
 559                                 mii_dev_for_muxval(mdio_mux[i]));
 560                         break;
 561                 default:
 562                         break;
 563                 }
 564         }
 565
 566         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 567                 idx = i - FM1_10GEC1;
 568                 switch (fm_info_get_enet_if(i)) {
 569                 case PHY_INTERFACE_MODE_XGMII:
 570                         lane = serdes_get_first_lane(FSL_SRDS_1,
 571                                                 XAUI_FM1_MAC9 + idx);
 572                         if (lane < 0)
 573                                 break;
 574                         slot = lane_to_slot_fsm1[lane];
 575                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 576                                 fm_disable_port(i);
 577                         mdio_mux[i] = EMI2;
 578                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 579                         break;
 580                 default:
 581                         break;
 582                 }
 583         }
 584
 585 #if (CONFIG_SYS_NUM_FMAN == 2)
 586         switch (srds_prtcl_s2) {
 587         case 1:
 588         case 2:
 589         case 4:
 590                 /* XAUI/HiGig in Slot3 and Slot4 */
 591                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 592                 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 593                 break;
 594         case 6:
 595         case 7:
 596         case 12:
 597         case 13:
 598         case 14:
 599         case 15:
 600         case 16:
 601         case 21:
 602         case 22:
 603         case 23:
 604         case 24:
 605         case 25:
 606         case 26:
 607                 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
 608                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 609                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 610                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 611                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 612                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 613                 break;
 614         case 27:
 615         case 28:
 616         case 35:
 617         case 36:
 618                 /* SGMII in Slot3 and Slot4 */
 619                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 620                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 621                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 622                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 623                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 624                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 625                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 626                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 627                 break;
 628         case 37:
 629         case 38:
 630                 /* QSGMII in Slot3 and Slot4 */
 631                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 632                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 633                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 634                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 635                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 636                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 637                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
 638                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
 639                 break;
 640         case 39:
 641         case 40:
 642         case 45:
 643         case 46:
 644         case 47:
 645         case 48:
 646                 /* SGMII in Slot3 */
 647                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 648                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 649                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 650                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 651                 /* QSGMII in Slot4 */
 652                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 653                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 654                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 655                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 656                 break;
 657         case 49:
 658         case 50:
 659         case 51:
 660         case 52:
 661         case 53:
 662         case 54:
 663                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 664                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 665                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 666                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 667                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 668                 break;
 669         case 56:
 670         case 57:
 671                 /* XFI in Slot3, SGMII in Slot4 */
 672                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 673                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 674                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 675                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 676                 break;
 677         default:
 678                 puts("Invalid SerDes2 protocol for T4240QDS\n");
 679                 break;
 680         }
 681
 682         for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 683                 idx = i - FM2_DTSEC1;
 684                 interface = fm_info_get_enet_if(i);
 685                 switch (interface) {
 686                 case PHY_INTERFACE_MODE_SGMII:
 687                 case PHY_INTERFACE_MODE_QSGMII:
 688                         if (interface == PHY_INTERFACE_MODE_QSGMII) {
 689                                 if (idx <= 3)
 690                                         lane = serdes_get_first_lane(FSL_SRDS_2,
 691                                                         QSGMII_FM2_A);
 692                                 else
 693                                         lane = serdes_get_first_lane(FSL_SRDS_2,
 694                                                         QSGMII_FM2_B);
 695                                 if (lane < 0)
 696                                         break;
 697                                 slot = lane_to_slot_fsm2[lane];
 698                                 debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
 699                                       idx + 1, slot);
 700                         } else {
 701                                 lane = serdes_get_first_lane(FSL_SRDS_2,
 702                                                 SGMII_FM2_DTSEC1 + idx);
 703                                 if (lane < 0)
 704                                         break;
 705                                 slot = lane_to_slot_fsm2[lane];
 706                                 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
 707                                       idx + 1, slot);
 708                         }
 709                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 710                                 fm_disable_port(i);
 711                         switch (slot) {
 712                         case 3:
 713                                 mdio_mux[i] = EMI1_SLOT3;
 714                                 fm_info_set_mdio(i,
 715                                         mii_dev_for_muxval(mdio_mux[i]));
 716                                 break;
 717                         case 4:
 718                                 mdio_mux[i] = EMI1_SLOT4;
 719                                 fm_info_set_mdio(i,
 720                                         mii_dev_for_muxval(mdio_mux[i]));
 721                                 break;
 722                         };
 723                         break;
 724                 case PHY_INTERFACE_MODE_RGMII:
 725                         /*
 726                          * If DTSEC5 is RGMII, then it's routed via via EC1 to
 727                          * the first on-board RGMII port.  If DTSEC6 is RGMII,
 728                          * then it's routed via via EC2 to the second on-board
 729                          * RGMII port.
 730                          */
 731                         debug("FM2@DTSEC%u is RGMII at address %u\n",
 732                                 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
 733                         fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
 734                         mdio_mux[i] = EMI1_RGMII;
 735                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 736                         break;
 737                 default:
 738                         break;
 739                 }
 740         }
 741
 742         for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 743                 idx = i - FM2_10GEC1;
 744                 switch (fm_info_get_enet_if(i)) {
 745                 case PHY_INTERFACE_MODE_XGMII:
 746                         lane = serdes_get_first_lane(FSL_SRDS_2,
 747                                                 XAUI_FM2_MAC9 + idx);
 748                         if (lane < 0)
 749                                 break;
 750                         slot = lane_to_slot_fsm2[lane];
 751                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 752                                 fm_disable_port(i);
 753                         mdio_mux[i] = EMI2;
 754                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 755                         break;
 756                 default:
 757                         break;
 758                 }
 759         }
 760 #endif /* CONFIG_SYS_NUM_FMAN */
 761
 762         cpu_eth_init(bis);
 763 #endif /* CONFIG_FMAN_ENET */
 764
 765         return pci_eth_init(bis);
 766 }