board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/spi.h>
  24 #include <asm/imx-common/video.h>
  25 #include <jffs2/load_kernel.h>
  26 #include <hwconfig.h>
  27 #include <i2c.h>
  28 #include <linux/ctype.h>
  29 #include <fdt_support.h>
  30 #include <fsl_esdhc.h>
  31 #include <miiphy.h>
  32 #include <mmc.h>
  33 #include <mtd_node.h>
  34 #include <netdev.h>
  35 #include <pci.h>
  36 #include <power/pmic.h>
  37 #include <power/ltc3676_pmic.h>
  38 #include <power/pfuze100_pmic.h>
  39 #include <fdt_support.h>
  40 #include <jffs2/load_kernel.h>
  41 #include <spi_flash.h>
  42
  43 #include "gsc.h"
  44 #include "ventana_eeprom.h"
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 /* GPIO's common to all baseboards */
  49 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  50 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  51 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  52 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  53 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  54
  55 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  56         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  57         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  58
  59 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  60         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  61         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  62
  63 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  64         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  65         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  66
  67 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  68         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  69         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  70
  71 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  72         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  73         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  74
  75 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  76         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  77         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  78
  79 #define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  80         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  81         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  82
  83 #define DIO_PAD_CFG   (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
  84
  85
  86 /*
  87  * EEPROM board info struct populated by read_eeprom so that we only have to
  88  * read it once.
  89  */
  90 struct ventana_board_info ventana_info;
  91
  92 int board_type;
  93
  94 /* UART1: Function varies per baseboard */
  95 iomux_v3_cfg_t const uart1_pads[] = {
  96         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  97         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  98 };
  99
 100 /* UART2: Serial Console */
 101 iomux_v3_cfg_t const uart2_pads[] = {
 102         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 103         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 104 };
 105
 106 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 107
 108 /* I2C1: GSC */
 109 struct i2c_pads_info mx6q_i2c_pad_info0 = {
 110         .scl = {
 111                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 112                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 113                 .gp = IMX_GPIO_NR(3, 21)
 114         },
 115         .sda = {
 116                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 117                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 118                 .gp = IMX_GPIO_NR(3, 28)
 119         }
 120 };
 121 struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 122         .scl = {
 123                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 124                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 125                 .gp = IMX_GPIO_NR(3, 21)
 126         },
 127         .sda = {
 128                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 129                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 130                 .gp = IMX_GPIO_NR(3, 28)
 131         }
 132 };
 133
 134 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 135 struct i2c_pads_info mx6q_i2c_pad_info1 = {
 136         .scl = {
 137                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 138                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 139                 .gp = IMX_GPIO_NR(4, 12)
 140         },
 141         .sda = {
 142                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 143                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 144                 .gp = IMX_GPIO_NR(4, 13)
 145         }
 146 };
 147 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 148         .scl = {
 149                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 150                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 151                 .gp = IMX_GPIO_NR(4, 12)
 152         },
 153         .sda = {
 154                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 155                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 156                 .gp = IMX_GPIO_NR(4, 13)
 157         }
 158 };
 159
 160 /* I2C3: Misc/Expansion */
 161 struct i2c_pads_info mx6q_i2c_pad_info2 = {
 162         .scl = {
 163                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 164                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 165                 .gp = IMX_GPIO_NR(1, 3)
 166         },
 167         .sda = {
 168                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 169                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 170                 .gp = IMX_GPIO_NR(1, 6)
 171         }
 172 };
 173 struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 174         .scl = {
 175                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 176                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 177                 .gp = IMX_GPIO_NR(1, 3)
 178         },
 179         .sda = {
 180                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 181                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 182                 .gp = IMX_GPIO_NR(1, 6)
 183         }
 184 };
 185
 186 /* MMC */
 187 iomux_v3_cfg_t const usdhc3_pads[] = {
 188         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 189         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 190         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 191         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 192         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 193         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 194         /* CD */
 195         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 196 };
 197
 198 /* ENET */
 199 iomux_v3_cfg_t const enet_pads[] = {
 200         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 201         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 203         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 205         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 206         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 208                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 210                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 212         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 214         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 215         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 216         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 217                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 218         /* PHY nRST */
 219         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 220 };
 221
 222 /* NAND */
 223 iomux_v3_cfg_t const nfc_pads[] = {
 224         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 225         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 226         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 235         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 236         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 237         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 238         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 239 };
 240
 241 #ifdef CONFIG_CMD_NAND
 242 static void setup_gpmi_nand(void)
 243 {
 244         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 245
 246         /* config gpmi nand iomux */
 247         SETUP_IOMUX_PADS(nfc_pads);
 248
 249         /* config gpmi and bch clock to 100 MHz */
 250         clrsetbits_le32(&mxc_ccm->cs2cdr,
 251                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 252                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 253                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 254                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 255                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 256                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 257
 258         /* enable gpmi and bch clock gating */
 259         setbits_le32(&mxc_ccm->CCGR4,
 260                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 261                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 262                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 263                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 264                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 265
 266         /* enable apbh clock gating */
 267         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 268 }
 269 #endif
 270
 271 static void setup_iomux_enet(void)
 272 {
 273         SETUP_IOMUX_PADS(enet_pads);
 274
 275         /* toggle PHY_RST# */
 276         gpio_direction_output(GP_PHY_RST, 0);
 277         mdelay(2);
 278         gpio_set_value(GP_PHY_RST, 1);
 279 }
 280
 281 static void setup_iomux_uart(void)
 282 {
 283         SETUP_IOMUX_PADS(uart1_pads);
 284         SETUP_IOMUX_PADS(uart2_pads);
 285 }
 286
 287 #ifdef CONFIG_USB_EHCI_MX6
 288 iomux_v3_cfg_t const usb_pads[] = {
 289         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 290         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 291         /* OTG PWR */
 292         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 293 };
 294
 295 int board_ehci_hcd_init(int port)
 296 {
 297         struct ventana_board_info *info = &ventana_info;
 298
 299         SETUP_IOMUX_PADS(usb_pads);
 300
 301         /* Reset USB HUB (present on GW54xx/GW53xx) */
 302         switch (info->model[3]) {
 303         case '3': /* GW53xx */
 304         case '5': /* GW552x */
 305                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 306                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 307                 mdelay(2);
 308                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 309                 break;
 310         case '4': /* GW54xx */
 311                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
 312                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 313                 mdelay(2);
 314                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 315                 break;
 316         }
 317
 318         return 0;
 319 }
 320
 321 int board_ehci_power(int port, int on)
 322 {
 323         if (port)
 324                 return 0;
 325         gpio_set_value(GP_USB_OTG_PWR, on);
 326         return 0;
 327 }
 328 #endif /* CONFIG_USB_EHCI_MX6 */
 329
 330 #ifdef CONFIG_FSL_ESDHC
 331 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 332
 333 int board_mmc_getcd(struct mmc *mmc)
 334 {
 335         /* Card Detect */
 336         gpio_direction_input(GP_SD3_CD);
 337         return !gpio_get_value(GP_SD3_CD);
 338 }
 339
 340 int board_mmc_init(bd_t *bis)
 341 {
 342         /* Only one USDHC controller on Ventana */
 343         SETUP_IOMUX_PADS(usdhc3_pads);
 344         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 345         usdhc_cfg.max_bus_width = 4;
 346
 347         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 348 }
 349 #endif /* CONFIG_FSL_ESDHC */
 350
 351 #ifdef CONFIG_MXC_SPI
 352 iomux_v3_cfg_t const ecspi1_pads[] = {
 353         /* SS1 */
 354         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 355         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 356         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 357         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 358 };
 359
 360 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 361 {
 362         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 363 }
 364
 365 static void setup_spi(void)
 366 {
 367         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 368         SETUP_IOMUX_PADS(ecspi1_pads);
 369 }
 370 #endif
 371
 372 /* configure eth0 PHY board-specific LED behavior */
 373 int board_phy_config(struct phy_device *phydev)
 374 {
 375         unsigned short val;
 376
 377         /* Marvel 88E1510 */
 378         if (phydev->phy_id == 0x1410dd1) {
 379                 /*
 380                  * Page 3, Register 16: LED[2:0] Function Control Register
 381                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 382                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 383                  */
 384                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 385                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 386                 val &= 0xff00;
 387                 val |= 0x0017;
 388                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 389                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 390         }
 391
 392         if (phydev->drv->config)
 393                 phydev->drv->config(phydev);
 394
 395         return 0;
 396 }
 397
 398 int board_eth_init(bd_t *bis)
 399 {
 400         setup_iomux_enet();
 401
 402 #ifdef CONFIG_FEC_MXC
 403         if (board_type != GW552x)
 404                 cpu_eth_init(bis);
 405 #endif
 406
 407 #ifdef CONFIG_E1000
 408         e1000_initialize(bis);
 409 #endif
 410
 411 #ifdef CONFIG_CI_UDC
 412         /* For otg ethernet*/
 413         usb_eth_initialize(bis);
 414 #endif
 415
 416         return 0;
 417 }
 418
 419 #if defined(CONFIG_VIDEO_IPUV3)
 420
 421 static void enable_hdmi(struct display_info_t const *dev)
 422 {
 423         imx_enable_hdmi_phy();
 424 }
 425
 426 static int detect_i2c(struct display_info_t const *dev)
 427 {
 428         return i2c_set_bus_num(dev->bus) == 0 &&
 429                 i2c_probe(dev->addr) == 0;
 430 }
 431
 432 static void enable_lvds(struct display_info_t const *dev)
 433 {
 434         struct iomuxc *iomux = (struct iomuxc *)
 435                                 IOMUXC_BASE_ADDR;
 436
 437         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 438         u32 reg = readl(&iomux->gpr[2]);
 439         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 440         writel(reg, &iomux->gpr[2]);
 441
 442         /* Enable Backlight */
 443         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 444         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 445 }
 446
 447 struct display_info_t const displays[] = {{
 448         /* HDMI Output */
 449         .bus    = -1,
 450         .addr   = 0,
 451         .pixfmt = IPU_PIX_FMT_RGB24,
 452         .detect = detect_hdmi,
 453         .enable = enable_hdmi,
 454         .mode   = {
 455                 .name           = "HDMI",
 456                 .refresh        = 60,
 457                 .xres           = 1024,
 458                 .yres           = 768,
 459                 .pixclock       = 15385,
 460                 .left_margin    = 220,
 461                 .right_margin   = 40,
 462                 .upper_margin   = 21,
 463                 .lower_margin   = 7,
 464                 .hsync_len      = 60,
 465                 .vsync_len      = 10,
 466                 .sync           = FB_SYNC_EXT,
 467                 .vmode          = FB_VMODE_NONINTERLACED
 468 } }, {
 469         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 470         .bus    = 2,
 471         .addr   = 0x4,
 472         .pixfmt = IPU_PIX_FMT_LVDS666,
 473         .detect = detect_i2c,
 474         .enable = enable_lvds,
 475         .mode   = {
 476                 .name           = "Hannstar-XGA",
 477                 .refresh        = 60,
 478                 .xres           = 1024,
 479                 .yres           = 768,
 480                 .pixclock       = 15385,
 481                 .left_margin    = 220,
 482                 .right_margin   = 40,
 483                 .upper_margin   = 21,
 484                 .lower_margin   = 7,
 485                 .hsync_len      = 60,
 486                 .vsync_len      = 10,
 487                 .sync           = FB_SYNC_EXT,
 488                 .vmode          = FB_VMODE_NONINTERLACED
 489 } } };
 490 size_t display_count = ARRAY_SIZE(displays);
 491
 492 static void setup_display(void)
 493 {
 494         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 495         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 496         int reg;
 497
 498         enable_ipu_clock();
 499         imx_setup_hdmi();
 500         /* Turn on LDB0,IPU,IPU DI0 clocks */
 501         reg = __raw_readl(&mxc_ccm->CCGR3);
 502         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 503         writel(reg, &mxc_ccm->CCGR3);
 504
 505         /* set LDB0, LDB1 clk select to 011/011 */
 506         reg = readl(&mxc_ccm->cs2cdr);
 507         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 508                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 509         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 510               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 511         writel(reg, &mxc_ccm->cs2cdr);
 512
 513         reg = readl(&mxc_ccm->cscmr2);
 514         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 515         writel(reg, &mxc_ccm->cscmr2);
 516
 517         reg = readl(&mxc_ccm->chsccdr);
 518         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 519                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 520         writel(reg, &mxc_ccm->chsccdr);
 521
 522         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 523              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 524              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 525              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 526              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 527              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 528              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 529              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 530              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 531         writel(reg, &iomux->gpr[2]);
 532
 533         reg = readl(&iomux->gpr[3]);
 534         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 535             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 536                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 537         writel(reg, &iomux->gpr[3]);
 538
 539         /* Backlight CABEN on LVDS connector */
 540         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 541         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 542 }
 543 #endif /* CONFIG_VIDEO_IPUV3 */
 544
 545 /*
 546  * Baseboard specific GPIO
 547  */
 548
 549 /* common to add baseboards */
 550 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 551         /* MSATA_EN */
 552         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 553         /* RS232_EN# */
 554         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 555 };
 556
 557 /* prototype */
 558 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 559         /* PANLEDG# */
 560         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 561         /* PANLEDR# */
 562         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 563         /* LOCLED# */
 564         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 565         /* RS485_EN */
 566         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
 567         /* IOEXP_PWREN# */
 568         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 569         /* IOEXP_IRQ# */
 570         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 571         /* VID_EN */
 572         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 573         /* DIOI2C_DIS# */
 574         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 575         /* PCICK_SSON */
 576         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 577         /* PCI_RST# */
 578         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 579 };
 580
 581 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 582         /* PANLEDG# */
 583         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 584         /* PANLEDR# */
 585         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 586         /* IOEXP_PWREN# */
 587         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 588         /* IOEXP_IRQ# */
 589         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 590
 591         /* GPS_SHDN */
 592         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 593         /* VID_PWR */
 594         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 595         /* PCI_RST# */
 596         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 597         /* PCIESKT_WDIS# */
 598         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 599 };
 600
 601 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 602         /* PANLEDG# */
 603         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 604         /* PANLEDR# */
 605         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 606         /* IOEXP_PWREN# */
 607         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 608         /* IOEXP_IRQ# */
 609         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 610
 611         /* MX6_LOCLED# */
 612         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 613         /* GPS_SHDN */
 614         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 615         /* USBOTG_SEL */
 616         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 617         /* VID_PWR */
 618         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 619         /* PCI_RST# */
 620         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 621         /* PCIESKT_WDIS# */
 622         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 623 };
 624
 625 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 626         /* PANLEDG# */
 627         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 628         /* PANLEDR# */
 629         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 630         /* MX6_LOCLED# */
 631         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 632         /* IOEXP_PWREN# */
 633         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 634         /* IOEXP_IRQ# */
 635         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 636         /* DIOI2C_DIS# */
 637         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 638         /* GPS_SHDN */
 639         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 640         /* VID_EN */
 641         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 642         /* PCI_RST# */
 643         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 644         /* PCIESKT_WDIS# */
 645         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 646 };
 647
 648 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 649         /* PANLEDG# */
 650         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 651         /* PANLEDR# */
 652         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 653         /* MX6_LOCLED# */
 654         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 655         /* MIPI_DIO */
 656         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
 657         /* RS485_EN */
 658         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
 659         /* IOEXP_PWREN# */
 660         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 661         /* IOEXP_IRQ# */
 662         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 663         /* DIOI2C_DIS# */
 664         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 665         /* PCICK_SSON */
 666         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 667         /* PCI_RST# */
 668         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 669         /* VID_EN */
 670         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 671         /* PCIESKT_WDIS# */
 672         IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
 673 };
 674
 675 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
 676         /* PANLEDG# */
 677         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 678         /* PANLEDR# */
 679         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 680         /* MX6_LOCLED# */
 681         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 682         /* PCI_RST# */
 683         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 684         /* MX6_DIO[4:9] */
 685         IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
 686         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 687         IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
 688         IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
 689         IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
 690         IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
 691         /* PCIEGBE1_OFF# */
 692         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
 693         /* PCIEGBE2_OFF# */
 694         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 695         /* PCIESKT_WDIS# */
 696         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 697 };
 698
 699 /*
 700  * each baseboard has 4 user configurable Digital IO lines which can
 701  * be pinmuxed as a GPIO or in some cases a PWM
 702  */
 703 struct dio_cfg {
 704         iomux_v3_cfg_t gpio_padmux[2];
 705         unsigned gpio_param;
 706         iomux_v3_cfg_t pwm_padmux[2];
 707         unsigned pwm_param;
 708 };
 709
 710 struct ventana {
 711         /* pinmux */
 712         iomux_v3_cfg_t const *gpio_pads;
 713         int num_pads;
 714         /* DIO pinmux/val */
 715         struct dio_cfg dio_cfg[4];
 716         /* various gpios (0 if non-existent) */
 717         int leds[3];
 718         int pcie_rst;
 719         int mezz_pwren;
 720         int mezz_irq;
 721         int rs485en;
 722         int gps_shdn;
 723         int vidin_en;
 724         int dioi2c_en;
 725         int pcie_sson;
 726         int usb_sel;
 727         int wdis;
 728 };
 729
 730 struct ventana gpio_cfg[] = {
 731         /* GW5400proto */
 732         {
 733                 .gpio_pads = gw54xx_gpio_pads,
 734                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 735                 .dio_cfg = {
 736                         {
 737                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 738                                 IMX_GPIO_NR(1, 9),
 739                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 740                                 1
 741                         },
 742                         {
 743                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 744                                 IMX_GPIO_NR(1, 19),
 745                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 746                                 2
 747                         },
 748                         {
 749                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 750                                 IMX_GPIO_NR(2, 9),
 751                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 752                                 3
 753                         },
 754                         {
 755                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 756                                 IMX_GPIO_NR(2, 10),
 757                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 758                                 4
 759                         },
 760                 },
 761                 .leds = {
 762                         IMX_GPIO_NR(4, 6),
 763                         IMX_GPIO_NR(4, 10),
 764                         IMX_GPIO_NR(4, 15),
 765                 },
 766                 .pcie_rst = IMX_GPIO_NR(1, 29),
 767                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 768                 .mezz_irq = IMX_GPIO_NR(4, 9),
 769                 .rs485en = IMX_GPIO_NR(3, 24),
 770                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 771                 .pcie_sson = IMX_GPIO_NR(1, 20),
 772         },
 773
 774         /* GW51xx */
 775         {
 776                 .gpio_pads = gw51xx_gpio_pads,
 777                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 778                 .dio_cfg = {
 779                         {
 780                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 781                                 IMX_GPIO_NR(1, 16),
 782                                 { 0, 0 },
 783                                 0
 784                         },
 785                         {
 786                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 787                                 IMX_GPIO_NR(1, 19),
 788                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 789                                 2
 790                         },
 791                         {
 792                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 793                                 IMX_GPIO_NR(1, 17),
 794                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 795                                 3
 796                         },
 797                         {
 798                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 799                                 IMX_GPIO_NR(1, 18),
 800                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 801                                 4
 802                         },
 803                 },
 804                 .leds = {
 805                         IMX_GPIO_NR(4, 6),
 806                         IMX_GPIO_NR(4, 10),
 807                 },
 808                 .pcie_rst = IMX_GPIO_NR(1, 0),
 809                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 810                 .mezz_irq = IMX_GPIO_NR(2, 18),
 811                 .gps_shdn = IMX_GPIO_NR(1, 2),
 812                 .vidin_en = IMX_GPIO_NR(5, 20),
 813                 .wdis = IMX_GPIO_NR(7, 12),
 814         },
 815
 816         /* GW52xx */
 817         {
 818                 .gpio_pads = gw52xx_gpio_pads,
 819                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 820                 .dio_cfg = {
 821                         {
 822                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 823                                 IMX_GPIO_NR(1, 16),
 824                                 { 0, 0 },
 825                                 0
 826                         },
 827                         {
 828                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 829                                 IMX_GPIO_NR(1, 19),
 830                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 831                                 2
 832                         },
 833                         {
 834                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 835                                 IMX_GPIO_NR(1, 17),
 836                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 837                                 3
 838                         },
 839                         {
 840                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 841                                 IMX_GPIO_NR(1, 20),
 842                                 { 0, 0 },
 843                                 0
 844                         },
 845                 },
 846                 .leds = {
 847                         IMX_GPIO_NR(4, 6),
 848                         IMX_GPIO_NR(4, 7),
 849                         IMX_GPIO_NR(4, 15),
 850                 },
 851                 .pcie_rst = IMX_GPIO_NR(1, 29),
 852                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 853                 .mezz_irq = IMX_GPIO_NR(2, 18),
 854                 .gps_shdn = IMX_GPIO_NR(1, 27),
 855                 .vidin_en = IMX_GPIO_NR(3, 31),
 856                 .usb_sel = IMX_GPIO_NR(1, 2),
 857                 .wdis = IMX_GPIO_NR(7, 12),
 858         },
 859
 860         /* GW53xx */
 861         {
 862                 .gpio_pads = gw53xx_gpio_pads,
 863                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 864                 .dio_cfg = {
 865                         {
 866                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 867                                 IMX_GPIO_NR(1, 16),
 868                                 { 0, 0 },
 869                                 0
 870                         },
 871                         {
 872                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 873                                 IMX_GPIO_NR(1, 19),
 874                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 875                                 2
 876                         },
 877                         {
 878                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 879                                 IMX_GPIO_NR(1, 17),
 880                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 881                                 3
 882                         },
 883                         {
 884                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 885                                 IMX_GPIO_NR(1, 20),
 886                                 { 0, 0 },
 887                                 0
 888                         },
 889                 },
 890                 .leds = {
 891                         IMX_GPIO_NR(4, 6),
 892                         IMX_GPIO_NR(4, 7),
 893                         IMX_GPIO_NR(4, 15),
 894                 },
 895                 .pcie_rst = IMX_GPIO_NR(1, 29),
 896                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 897                 .mezz_irq = IMX_GPIO_NR(2, 18),
 898                 .gps_shdn = IMX_GPIO_NR(1, 27),
 899                 .vidin_en = IMX_GPIO_NR(3, 31),
 900                 .wdis = IMX_GPIO_NR(7, 12),
 901         },
 902
 903         /* GW54xx */
 904         {
 905                 .gpio_pads = gw54xx_gpio_pads,
 906                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 907                 .dio_cfg = {
 908                         {
 909                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 910                                 IMX_GPIO_NR(1, 9),
 911                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 912                                 1
 913                         },
 914                         {
 915                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 916                                 IMX_GPIO_NR(1, 19),
 917                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 918                                 2
 919                         },
 920                         {
 921                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 922                                 IMX_GPIO_NR(2, 9),
 923                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 924                                 3
 925                         },
 926                         {
 927                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 928                                 IMX_GPIO_NR(2, 10),
 929                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 930                                 4
 931                         },
 932                 },
 933                 .leds = {
 934                         IMX_GPIO_NR(4, 6),
 935                         IMX_GPIO_NR(4, 7),
 936                         IMX_GPIO_NR(4, 15),
 937                 },
 938                 .pcie_rst = IMX_GPIO_NR(1, 29),
 939                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 940                 .mezz_irq = IMX_GPIO_NR(2, 18),
 941                 .rs485en = IMX_GPIO_NR(7, 1),
 942                 .vidin_en = IMX_GPIO_NR(3, 31),
 943                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 944                 .pcie_sson = IMX_GPIO_NR(1, 20),
 945                 .wdis = IMX_GPIO_NR(5, 17),
 946         },
 947
 948         /* GW552x */
 949         {
 950                 .gpio_pads = gw552x_gpio_pads,
 951                 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
 952                 .dio_cfg = {
 953                         {
 954                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 955                                 IMX_GPIO_NR(1, 16),
 956                                 { 0, 0 },
 957                                 0
 958                         },
 959                         {
 960                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 961                                 IMX_GPIO_NR(1, 19),
 962                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 963                                 2
 964                         },
 965                         {
 966                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 967                                 IMX_GPIO_NR(1, 17),
 968                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 969                                 3
 970                         },
 971                         {
 972                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 973                                 IMX_GPIO_NR(2, 10),
 974                                 { 0, 0 },
 975                                 0
 976                         },
 977                 },
 978                 .leds = {
 979                         IMX_GPIO_NR(4, 6),
 980                         IMX_GPIO_NR(4, 7),
 981                         IMX_GPIO_NR(4, 15),
 982                 },
 983                 .pcie_rst = IMX_GPIO_NR(1, 29),
 984         },
 985 };
 986
 987 /* setup board specific PMIC */
 988 int power_init_board(void)
 989 {
 990         struct pmic *p;
 991         u32 reg;
 992
 993         /* configure PFUZE100 PMIC */
 994         if (board_type == GW54xx || board_type == GW54proto) {
 995                 power_pfuze100_init(CONFIG_I2C_PMIC);
 996                 p = pmic_get("PFUZE100");
 997                 if (p && !pmic_probe(p)) {
 998                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 999                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
1000
1001                         /* Set VGEN1 to 1.5V and enable */
1002                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
1003                         reg &= ~(LDO_VOL_MASK);
1004                         reg |= (LDOA_1_50V | LDO_EN);
1005                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1006
1007                         /* Set SWBST to 5.0V and enable */
1008                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
1009                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1010                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1011                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1012                 }
1013         }
1014
1015         /* configure LTC3676 PMIC */
1016         else {
1017                 power_ltc3676_init(CONFIG_I2C_PMIC);
1018                 p = pmic_get("LTC3676_PMIC");
1019                 if (p && !pmic_probe(p)) {
1020                         puts("PMIC:  LTC3676\n");
1021                         /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
1022                         if (is_cpu_type(MXC_CPU_MX6Q)) {
1023                                 /* mask PGOOD during SW1 transition */
1024                                 reg = 0x1d | LTC3676_PGOOD_MASK;
1025                                 pmic_reg_write(p, LTC3676_DVB1B, reg);
1026                                 /* set SW1 (VDD_SOC) to 1259mV */
1027                                 reg = 0x1d;
1028                                 pmic_reg_write(p, LTC3676_DVB1A, reg);
1029
1030                                 /* mask PGOOD during SW3 transition */
1031                                 reg = 0x1d | LTC3676_PGOOD_MASK;
1032                                 pmic_reg_write(p, LTC3676_DVB3B, reg);
1033                                 /*set SW3 (VDD_ARM) to 1259mV */
1034                                 reg = 0x1d;
1035                                 pmic_reg_write(p, LTC3676_DVB3A, reg);
1036                         }
1037                 }
1038         }
1039
1040         return 0;
1041 }
1042
1043 /* setup GPIO pinmux and default configuration per baseboard */
1044 static void setup_board_gpio(int board)
1045 {
1046         struct ventana_board_info *info = &ventana_info;
1047         const char *s;
1048         char arg[10];
1049         size_t len;
1050         int i;
1051         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
1052
1053         if (board >= GW_UNKNOWN)
1054                 return;
1055
1056         /* RS232_EN# */
1057         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
1058
1059         /* MSATA Enable */
1060         if (is_cpu_type(MXC_CPU_MX6Q) &&
1061             test_bit(EECONFIG_SATA, info->config)) {
1062                 gpio_direction_output(GP_MSATA_SEL,
1063                                       (hwconfig("msata")) ?  1 : 0);
1064         } else {
1065                 gpio_direction_output(GP_MSATA_SEL, 0);
1066         }
1067
1068 #if !defined(CONFIG_CMD_PCI)
1069         /* assert PCI_RST# (released by OS when clock is valid) */
1070         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1071 #endif
1072
1073         /* turn off (active-high) user LED's */
1074         for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
1075                 if (gpio_cfg[board].leds[i])
1076                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
1077         }
1078
1079         /* Expansion Mezzanine IO */
1080         if (gpio_cfg[board].mezz_pwren)
1081                 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1082         if (gpio_cfg[board].mezz_irq)
1083                 gpio_direction_input(gpio_cfg[board].mezz_irq);
1084
1085         /* RS485 Transmit Enable */
1086         if (gpio_cfg[board].rs485en)
1087                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1088
1089         /* GPS_SHDN */
1090         if (gpio_cfg[board].gps_shdn)
1091                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1092
1093         /* Analog video codec power enable */
1094         if (gpio_cfg[board].vidin_en)
1095                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1096
1097         /* DIOI2C_DIS# */
1098         if (gpio_cfg[board].dioi2c_en)
1099                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1100
1101         /* PCICK_SSON: disable spread-spectrum clock */
1102         if (gpio_cfg[board].pcie_sson)
1103                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1104
1105         /* USBOTG Select (PCISKT or FrontPanel) */
1106         if (gpio_cfg[board].usb_sel)
1107                 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1108
1109         /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1110         if (gpio_cfg[board].wdis)
1111                 gpio_direction_output(gpio_cfg[board].wdis, 1);
1112
1113         /*
1114          * Configure DIO pinmux/padctl registers
1115          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1116          */
1117         for (i = 0; i < 4; i++) {
1118                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1119                 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1120                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1121
1122                 sprintf(arg, "dio%d", i);
1123                 if (!hwconfig(arg))
1124                         continue;
1125                 s = hwconfig_subarg(arg, "padctrl", &len);
1126                 if (s) {
1127                         ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1128                                             & 0x1ffff) | MUX_MODE_SION;
1129                 }
1130                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1131                         if (!quiet) {
1132                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1133                                        (cfg->gpio_param/32)+1,
1134                                        cfg->gpio_param%32,
1135                                        cfg->gpio_param);
1136                         }
1137                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1138                                                ctrl);
1139                         gpio_direction_input(cfg->gpio_param);
1140                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1141                            cfg->pwm_padmux) {
1142                         if (!quiet)
1143                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1144                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1145                                                MUX_PAD_CTRL(ctrl));
1146                 }
1147         }
1148
1149         if (!quiet) {
1150                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1151                     (test_bit(EECONFIG_SATA, info->config))) {
1152                         printf("MSATA: %s\n", (hwconfig("msata") ?
1153                                "enabled" : "disabled"));
1154                 }
1155                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1156                        "enabled" : "disabled");
1157         }
1158 }
1159
1160 #if defined(CONFIG_CMD_PCI)
1161 int imx6_pcie_toggle_reset(void)
1162 {
1163         if (board_type < GW_UNKNOWN) {
1164                 uint pin = gpio_cfg[board_type].pcie_rst;
1165                 gpio_direction_output(pin, 0);
1166                 mdelay(50);
1167                 gpio_direction_output(pin, 1);
1168         }
1169         return 0;
1170 }
1171
1172 /*
1173  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
1174  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
1175  * properly and assert reset for 100ms.
1176  */
1177 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
1178                          unsigned short vendor, unsigned short device,
1179                          unsigned short class)
1180 {
1181         u32 dw;
1182
1183         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
1184               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
1185         if (vendor == PCI_VENDOR_ID_PLX &&
1186             (device & 0xfff0) == 0x8600 &&
1187             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
1188                 debug("configuring PLX 860X downstream PERST#\n");
1189                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
1190                 dw |= 0xaaa8; /* GPIO1-7 outputs */
1191                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
1192
1193                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
1194                 dw |= 0xfe;   /* GPIO1-7 output high */
1195                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
1196
1197                 mdelay(100);
1198         }
1199 }
1200 #endif /* CONFIG_CMD_PCI */
1201
1202 #ifdef CONFIG_SERIAL_TAG
1203 /*
1204  * called when setting up ATAGS before booting kernel
1205  * populate serialnum from the following (in order of priority):
1206  *   serial# env var
1207  *   eeprom
1208  */
1209 void get_board_serial(struct tag_serialnr *serialnr)
1210 {
1211         char *serial = getenv("serial#");
1212
1213         if (serial) {
1214                 serialnr->high = 0;
1215                 serialnr->low = simple_strtoul(serial, NULL, 10);
1216         } else if (ventana_info.model[0]) {
1217                 serialnr->high = 0;
1218                 serialnr->low = ventana_info.serial;
1219         } else {
1220                 serialnr->high = 0;
1221                 serialnr->low = 0;
1222         }
1223 }
1224 #endif
1225
1226 /*
1227  * Board Support
1228  */
1229
1230 /* called from SPL board_init_f() */
1231 int board_early_init_f(void)
1232 {
1233         setup_iomux_uart();
1234         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1235
1236 #if defined(CONFIG_VIDEO_IPUV3)
1237         setup_display();
1238 #endif
1239         return 0;
1240 }
1241
1242 int dram_init(void)
1243 {
1244         gd->ram_size = imx_ddr_size();
1245         return 0;
1246 }
1247
1248 int board_init(void)
1249 {
1250         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1251
1252         clrsetbits_le32(&iomuxc_regs->gpr[1],
1253                         IOMUXC_GPR1_OTG_ID_MASK,
1254                         IOMUXC_GPR1_OTG_ID_GPIO1);
1255
1256         /* address of linux boot parameters */
1257         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1258
1259 #ifdef CONFIG_CMD_NAND
1260         setup_gpmi_nand();
1261 #endif
1262 #ifdef CONFIG_MXC_SPI
1263         setup_spi();
1264 #endif
1265         if (is_cpu_type(MXC_CPU_MX6Q)) {
1266                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1267                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1268                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1269         } else {
1270                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1271                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1272                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1273         }
1274
1275 #ifdef CONFIG_CMD_SATA
1276         setup_sata();
1277 #endif
1278         /* read Gateworks EEPROM into global struct (used later) */
1279         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1280
1281         /* board-specifc GPIO iomux */
1282         SETUP_IOMUX_PADS(gw_gpio_pads);
1283         if (board_type < GW_UNKNOWN) {
1284                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1285                 int count = gpio_cfg[board_type].num_pads;
1286
1287                 imx_iomux_v3_setup_multiple_pads(p, count);
1288         }
1289
1290         return 0;
1291 }
1292
1293 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1294 /*
1295  * called during late init (after relocation and after board_init())
1296  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1297  * EEPROM read.
1298  */
1299 int checkboard(void)
1300 {
1301         struct ventana_board_info *info = &ventana_info;
1302         unsigned char buf[4];
1303         const char *p;
1304         int quiet; /* Quiet or minimal output mode */
1305
1306         quiet = 0;
1307         p = getenv("quiet");
1308         if (p)
1309                 quiet = simple_strtol(p, NULL, 10);
1310         else
1311                 setenv("quiet", "0");
1312
1313         puts("\nGateworks Corporation Copyright 2014\n");
1314         if (info->model[0]) {
1315                 printf("Model: %s\n", info->model);
1316                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1317                        info->mfgdate[0], info->mfgdate[1],
1318                        info->mfgdate[2], info->mfgdate[3]);
1319                 printf("Serial:%d\n", info->serial);
1320         } else {
1321                 puts("Invalid EEPROM - board will not function fully\n");
1322         }
1323         if (quiet)
1324                 return 0;
1325
1326         /* Display GSC firmware revision/CRC/status */
1327         i2c_set_bus_num(CONFIG_I2C_GSC);
1328         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1329                 printf("GSC:   v%d", buf[0]);
1330                 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1331                         printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1332                         printf(" 0x%02x", buf[0]); /* irq status */
1333                 }
1334                 puts("\n");
1335         }
1336         /* Display RTC */
1337         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1338                 printf("RTC:   %d\n",
1339                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1340         }
1341
1342         return 0;
1343 }
1344 #endif
1345
1346 #ifdef CONFIG_CMD_BMODE
1347 /*
1348  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1349  * see Table 8-11 and Table 5-9
1350  *  BOOT_CFG1[7] = 1 (boot from NAND)
1351  *  BOOT_CFG1[5] = 0 - raw NAND
1352  *  BOOT_CFG1[4] = 0 - default pad settings
1353  *  BOOT_CFG1[3:2] = 00 - devices = 1
1354  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1355  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1356  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1357  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1358  */
1359 static const struct boot_mode board_boot_modes[] = {
1360         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1361         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1362         { NULL, 0 },
1363 };
1364 #endif
1365
1366 /* late init */
1367 int misc_init_r(void)
1368 {
1369         struct ventana_board_info *info = &ventana_info;
1370         unsigned char reg;
1371
1372         /* set env vars based on EEPROM data */
1373         if (ventana_info.model[0]) {
1374                 char str[16], fdt[36];
1375                 char *p;
1376                 const char *cputype = "";
1377                 int i;
1378
1379                 /*
1380                  * FDT name will be prefixed with CPU type.  Three versions
1381                  * will be created each increasingly generic and bootloader
1382                  * env scripts will try loading each from most specific to
1383                  * least.
1384                  */
1385                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1386                     is_cpu_type(MXC_CPU_MX6D))
1387                         cputype = "imx6q";
1388                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1389                          is_cpu_type(MXC_CPU_MX6SOLO))
1390                         cputype = "imx6dl";
1391                 setenv("soctype", cputype);
1392                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1393                         setenv("flash_layout", "large");
1394                 else
1395                         setenv("flash_layout", "normal");
1396                 memset(str, 0, sizeof(str));
1397                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1398                         str[i] = tolower(info->model[i]);
1399                 if (!getenv("model"))
1400                         setenv("model", str);
1401                 if (!getenv("fdt_file")) {
1402                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1403                         setenv("fdt_file", fdt);
1404                 }
1405                 p = strchr(str, '-');
1406                 if (p) {
1407                         *p++ = 0;
1408
1409                         setenv("model_base", str);
1410                         if (!getenv("fdt_file1")) {
1411                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1412                                 setenv("fdt_file1", fdt);
1413                         }
1414                         if (board_type != GW552x)
1415                                 str[4] = 'x';
1416                         str[5] = 'x';
1417                         str[6] = 0;
1418                         if (!getenv("fdt_file2")) {
1419                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1420                                 setenv("fdt_file2", fdt);
1421                         }
1422                 }
1423
1424                 /* initialize env from EEPROM */
1425                 if (test_bit(EECONFIG_ETH0, info->config) &&
1426                     !getenv("ethaddr")) {
1427                         eth_setenv_enetaddr("ethaddr", info->mac0);
1428                 }
1429                 if (test_bit(EECONFIG_ETH1, info->config) &&
1430                     !getenv("eth1addr")) {
1431                         eth_setenv_enetaddr("eth1addr", info->mac1);
1432                 }
1433
1434                 /* board serial-number */
1435                 sprintf(str, "%6d", info->serial);
1436                 setenv("serial#", str);
1437         }
1438
1439
1440         /* setup baseboard specific GPIO pinmux and config */
1441         setup_board_gpio(board_type);
1442
1443 #ifdef CONFIG_CMD_BMODE
1444         add_board_boot_modes(board_boot_modes);
1445 #endif
1446
1447         /*
1448          *  The Gateworks System Controller implements a boot
1449          *  watchdog (always enabled) as a workaround for IMX6 boot related
1450          *  errata such as:
1451          *    ERR005768 - no fix scheduled
1452          *    ERR006282 - fixed in silicon r1.2
1453          *    ERR007117 - fixed in silicon r1.3
1454          *    ERR007220 - fixed in silicon r1.3
1455          *    ERR007926 - no fix scheduled
1456          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1457          *
1458          * Disable the boot watchdog and display/clear the timeout flag if set
1459          */
1460         i2c_set_bus_num(CONFIG_I2C_GSC);
1461         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1462                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1463                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1464                         puts("Error: could not disable GSC Watchdog\n");
1465         } else {
1466                 puts("Error: could not disable GSC Watchdog\n");
1467         }
1468         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1469                 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1470                         puts("GSC boot watchdog timeout detected\n");
1471                         reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1472                         gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1473                 }
1474         }
1475
1476         return 0;
1477 }
1478
1479 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1480
1481 /*
1482  * called prior to booting kernel or by 'fdt boardsetup' command
1483  *
1484  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1485  *  - mtd partitions based on mtdparts/mtdids env
1486  *  - system-serial (board serial num from EEPROM)
1487  *  - board (full model from EEPROM)
1488  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1489  */
1490 int ft_board_setup(void *blob, bd_t *bd)
1491 {
1492         struct ventana_board_info *info = &ventana_info;
1493         struct ventana_eeprom_config *cfg;
1494         struct node_info nodes[] = {
1495                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1496                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1497         };
1498         const char *model = getenv("model");
1499
1500         if (getenv("fdt_noauto")) {
1501                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1502                 return 0;
1503         }
1504
1505         /* Update partition nodes using info from mtdparts env var */
1506         puts("   Updating MTD partitions...\n");
1507         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1508
1509         if (!model) {
1510                 puts("invalid board info: Leaving FDT fully enabled\n");
1511                 return 0;
1512         }
1513         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1514
1515         /* board serial number */
1516         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1517                     strlen(getenv("serial#")) + 1);
1518
1519         /* board (model contains model from device-tree) */
1520         fdt_setprop(blob, 0, "board", info->model,
1521                     strlen((const char *)info->model) + 1);
1522
1523         /*
1524          * Peripheral Config:
1525          *  remove nodes by alias path if EEPROM config tells us the
1526          *  peripheral is not loaded on the board.
1527          */
1528         if (getenv("fdt_noconfig")) {
1529                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1530                 return 0;
1531         }
1532         cfg = econfig;
1533         while (cfg->name) {
1534                 if (!test_bit(cfg->bit, info->config)) {
1535                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1536                                                cfg->dtalias : cfg->name);
1537                 }
1538                 cfg++;
1539         }
1540
1541         return 0;
1542 }
1543 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1544