board/karo/tk71/tk71.c

   1 /*
   2  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
   3  * on behalf of DENX Software Engineering GmbH
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <miiphy.h>
  10 #include <asm/arch/cpu.h>
  11 #include <asm/arch/soc.h>
  12 #include <asm/arch/mpp.h>
  13 #include <asm/io.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 #define TK71_OE_LOW                     (~0)
  18 #define TK71_OE_HIGH                    (~0)
  19 #define TK71_OE_VAL_LOW                 (0)
  20 #define TK71_OE_VAL_HIGH                (0)
  21
  22 int board_early_init_f(void)
  23 {
  24         /*
  25          * default gpio configuration
  26          * There are maximum 64 gpios controlled through 2 sets of registers
  27          * the  below configuration configures mainly initial LED status
  28          */
  29         mvebu_config_gpio(TK71_OE_VAL_LOW,
  30                           TK71_OE_VAL_HIGH,
  31                           TK71_OE_LOW, TK71_OE_HIGH);
  32
  33         /* Multi-Purpose Pins Functionality configuration */
  34         static const u32 kwmpp_config[] = {
  35                 MPP0_NF_IO2,
  36                 MPP1_NF_IO3,
  37                 MPP2_NF_IO4,
  38                 MPP3_NF_IO5,
  39                 MPP4_NF_IO6,
  40                 MPP5_NF_IO7,
  41                 MPP6_SYSRST_OUTn,
  42                 MPP7_GPO,
  43                 MPP8_TW_SDA,
  44                 MPP9_TW_SCK,
  45                 MPP10_UART0_TXD,
  46                 MPP11_UART0_RXD,
  47                 MPP12_SD_CLK,
  48                 MPP13_SD_CMD,
  49                 MPP14_SD_D0,
  50                 MPP15_SD_D1,
  51                 MPP16_SD_D2,
  52                 MPP17_SD_D3,
  53                 MPP18_NF_IO0,
  54                 MPP19_NF_IO1,
  55                 MPP20_GE1_0,
  56                 MPP21_GE1_1,
  57                 MPP22_GE1_2,
  58                 MPP23_GE1_3,
  59                 MPP24_GE1_4,
  60                 MPP25_GE1_5,
  61                 MPP26_GE1_6,
  62                 MPP27_GE1_7,
  63                 MPP28_GPIO,
  64                 MPP29_GPIO,
  65                 MPP30_GE1_10,
  66                 MPP31_GE1_11,
  67                 MPP32_GE1_12,
  68                 MPP33_GE1_13,
  69                 MPP34_GPIO,
  70                 MPP35_GPIO,
  71                 MPP36_GPIO,
  72                 MPP37_GPIO,
  73                 MPP38_GPIO,
  74                 MPP39_GPIO,
  75                 MPP40_GPIO,
  76                 MPP41_GPIO,
  77                 MPP42_GPIO,
  78                 MPP43_GPIO,
  79                 MPP44_GPIO,
  80                 MPP45_GPIO,
  81                 MPP46_GPIO,
  82                 MPP47_GPIO,
  83                 MPP48_GPIO,
  84                 MPP49_GPIO,
  85                 0
  86         };
  87         kirkwood_mpp_conf(kwmpp_config, NULL);
  88
  89         return 0;
  90 }
  91
  92 int board_init(void)
  93 {
  94         /*
  95          * arch number of board
  96          */
  97         gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
  98
  99         /* adress of boot parameters */
 100         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 101
 102         return 0;
 103 }
 104
 105 #ifdef CONFIG_CMD_NET
 106
 107 #define MV88E1116_MAC_CTRL2_REG         21
 108 #define MV88E1116_PGADR_REG             22
 109 #define MV88E1116_RGMII_TXTM_CTRL       (1 << 4)
 110 #define MV88E1116_RGMII_RXTM_CTRL       (1 << 5)
 111
 112 static void mv_phy_88e1118_init(char *name)
 113 {
 114         u16 reg;
 115         u16 devadr;
 116
 117         if (miiphy_set_current_dev(name))
 118                 return;
 119
 120         /* command to read PHY dev address */
 121         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 122                 printf("Err..%s could not read PHY dev address\n",
 123                         __func__);
 124                 return;
 125         }
 126
 127         /*
 128          * Enable RGMII delay on Tx and Rx for CPU port
 129          * Ref: sec 4.7.2 of chip datasheet
 130          */
 131         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 132         miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
 133         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 134         miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
 135         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 136
 137         /* reset the phy */
 138         miiphy_reset(name, devadr);
 139
 140         printf("88E1118 Initialized on %s\n", name);
 141 }
 142
 143 /* Configure and enable Switch and PHY */
 144 void reset_phy(void)
 145 {
 146         /* configure and initialize PHY */
 147         mv_phy_88e1118_init("egiga0");
 148
 149 }
 150 #endif