2 * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
22 #include <fdt_support.h>
28 #include <linux/list.h>
32 #include <asm/arch/iomux-mx28.h>
33 #include <asm/arch/clock.h>
34 #include <asm/arch/imx-regs.h>
35 #include <asm/arch/sys_proto.h>
37 #include "../common/karo.h"
39 DECLARE_GLOBAL_DATA_PTR;
41 #define MXS_GPIO_NR(p, o) (((p) << 5) | (o))
43 #define TX28_LCD_PWR_GPIO MX28_PAD_LCD_ENABLE__GPIO_1_31
44 #define TX28_LCD_RST_GPIO MX28_PAD_LCD_RESET__GPIO_3_30
45 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
47 #define TX28_USBH_VBUSEN_GPIO MX28_PAD_SPDIF__GPIO_3_27
48 #define TX28_USBH_OC_GPIO MX28_PAD_JTAG_RTCK__GPIO_4_20
49 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
50 #define TX28_USBOTG_OC_GPIO MX28_PAD_GPMI_CE3N__GPIO_0_19
51 #define TX28_USBOTG_ID_GPIO MX28_PAD_PWM2__GPIO_3_18
53 #define TX28_LED_GPIO MX28_PAD_ENET0_RXD3__GPIO_4_10
55 #define STK5_CAN_XCVR_GPIO MX28_PAD_LCD_D00__GPIO_1_0
57 static const struct gpio tx28_gpios[] = {
58 { TX28_USBH_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBH VBUSEN", },
59 { TX28_USBH_OC_GPIO, GPIOFLAG_INPUT, "USBH OC", },
60 { TX28_USBOTG_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
61 { TX28_USBOTG_OC_GPIO, GPIOFLAG_INPUT, "USBOTG OC", },
62 { TX28_USBOTG_ID_GPIO, GPIOFLAG_INPUT, "USBOTG ID", },
65 static const iomux_cfg_t tx28_pads[] = {
67 #if CONFIG_CONS_INDEX == 0
68 MX28_PAD_AUART0_RX__DUART_CTS,
69 MX28_PAD_AUART0_TX__DUART_RTS,
70 MX28_PAD_AUART0_CTS__DUART_RX,
71 MX28_PAD_AUART0_RTS__DUART_TX,
72 #elif CONFIG_CONS_INDEX == 1
73 MX28_PAD_AUART1_RX__AUART1_RX,
74 MX28_PAD_AUART1_TX__AUART1_TX,
75 MX28_PAD_AUART1_CTS__AUART1_CTS,
76 MX28_PAD_AUART1_RTS__AUART1_RTS,
77 #elif CONFIG_CONS_INDEX == 2
78 MX28_PAD_AUART3_RX__AUART3_RX,
79 MX28_PAD_AUART3_TX__AUART3_TX,
80 MX28_PAD_AUART3_CTS__AUART3_CTS,
81 MX28_PAD_AUART3_RTS__AUART3_RTS,
83 /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
84 MX28_PAD_I2C0_SCL__I2C0_SCL,
85 MX28_PAD_I2C0_SDA__I2C0_SDA,
88 MX28_PAD_SPDIF__GPIO_3_27,
89 MX28_PAD_JTAG_RTCK__GPIO_4_20,
91 /* USBOTG VBUSEN, OC, ID */
92 MX28_PAD_GPMI_CE2N__GPIO_0_18,
93 MX28_PAD_GPMI_CE3N__GPIO_0_19,
94 MX28_PAD_PWM2__GPIO_3_18,
101 /* provide at least _some_ sort of randomness */
102 #define MAX_LOOPS 100
104 static u32 random __attribute__((section("data")));
106 static inline void random_init(void)
108 struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
112 for (i = 0; i < MAX_LOOPS; i++) {
113 u32 hclk = readl(&digctl_regs->hw_digctl_hclkcount);
114 u32 entropy = readl(&digctl_regs->hw_digctl_entropy);
115 u32 usec = readl(&digctl_regs->hw_digctl_microseconds);
117 seed = get_timer(hclk ^ entropy ^ usec ^ random ^ seed);
123 #define RTC_PERSISTENT0_CLK32_MASK (RTC_PERSISTENT0_CLOCKSOURCE | \
124 RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
125 static u32 boot_cause __attribute__((section("data")));
127 int board_early_init_f(void)
129 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
135 /* IO0 clock at 480MHz */
136 mxs_set_ioclk(MXC_IOCLK0, 480000);
137 /* IO1 clock at 480MHz */
138 mxs_set_ioclk(MXC_IOCLK1, 480000);
140 /* SSP0 clock at 96MHz */
141 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
142 /* SSP2 clock at 96MHz */
143 mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
145 gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
146 mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
148 while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
149 RTC_STAT_STALE_REGS_PERSISTENT0) {
154 boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
155 if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
156 RTC_PERSISTENT0_CLK32_MASK) {
157 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
159 writel(RTC_PERSISTENT0_CLK32_MASK,
160 &rtc_regs->hw_rtc_persistent0_set);
165 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
172 printf("CTRL-C detected; safeboot enabled\n");
174 /* Address of boot parameters */
175 #ifdef CONFIG_OF_LIBFDT
176 gd->bd->bi_arch_number = -1;
178 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
184 return mxs_dram_init();
187 #ifdef CONFIG_CMD_MMC
188 static int tx28_mmc_wp(int dev_no)
193 int board_mmc_init(bd_t *bis)
195 return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
197 #endif /* CONFIG_CMD_MMC */
199 #ifdef CONFIG_FEC_MXC
200 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
202 #ifndef CONFIG_TX28_S
203 #define FEC_MAX_IDX 1
205 #define FEC_MAX_IDX 0
211 static int fec_get_mac_addr(int index)
214 struct mxs_ocotp_regs *ocotp_regs =
215 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
216 u32 *cust = &ocotp_regs->hw_ocotp_cust0;
218 char env_name[] = "eth.addr";
222 if (index < 0 || index > FEC_MAX_IDX)
225 /* set this bit to open the OTP banks for reading */
226 writel(OCOTP_CTRL_RD_BANK_OPEN,
227 &ocotp_regs->hw_ocotp_ctrl_set);
229 /* wait until OTP contents are readable */
230 while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
236 for (i = 0; i < sizeof(mac); i++) {
237 int shift = 24 - i % 4 * 8;
240 val = readl(&cust[index * 8 + i]);
241 mac[i] = val >> shift;
243 if (!is_valid_ethaddr(mac)) {
245 printf("No valid MAC address programmed\n");
250 printf("MAC addr from fuse: %pM\n", mac);
251 snprintf(env_name, sizeof(env_name), "ethaddr");
253 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
255 eth_setenv_enetaddr(env_name, mac);
259 static inline int tx28_fec1_enabled(void)
267 off = fdt_path_offset(gd->fdt_blob, "ethernet1");
271 status = fdt_getprop(gd->fdt_blob, off, "status", NULL);
272 return status && (strcmp(status, "okay") == 0);
275 static void tx28_init_mac(void)
279 ret = fec_get_mac_addr(0);
281 printf("Failed to read FEC0 MAC address from OCOTP\n");
285 if (tx28_fec1_enabled()) {
286 ret = fec_get_mac_addr(1);
288 printf("Failed to read FEC1 MAC address from OCOTP\n");
295 static inline void tx28_init_mac(void)
298 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
300 static const iomux_cfg_t tx28_fec_pads[] = {
301 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
302 MX28_PAD_ENET0_RXD0__ENET0_RXD0,
303 MX28_PAD_ENET0_RXD1__ENET0_RXD1,
306 int board_eth_init(bd_t *bis)
310 /* Reset the external phy */
311 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
313 /* Power on the external phy */
314 gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
316 /* Pull strap pins to high */
317 gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
318 gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
319 gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
320 gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
323 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
326 mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
328 ret = cpu_eth_init(bis);
330 printf("cpu_eth_init() failed: %d\n", ret);
334 #ifndef CONFIG_TX28_S
335 if (getenv("ethaddr")) {
336 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
338 printf("FEC MXS: Unable to init FEC0\n");
343 if (getenv("eth1addr")) {
344 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
346 printf("FEC MXS: Unable to init FEC1\n");
351 if (getenv("ethaddr")) {
352 ret = fecmxc_initialize(bis);
354 printf("FEC MXS: Unable to init FEC\n");
362 static inline void tx28_init_mac(void)
365 #endif /* CONFIG_FEC_MXC */
373 void show_activity(int arg)
375 static int led_state = LED_STATE_INIT;
378 if (led_state == LED_STATE_INIT) {
380 gpio_set_value(TX28_LED_GPIO, 1);
381 led_state = LED_STATE_ON;
383 if (get_timer(last) > CONFIG_SYS_HZ) {
385 if (led_state == LED_STATE_ON) {
386 gpio_set_value(TX28_LED_GPIO, 0);
388 gpio_set_value(TX28_LED_GPIO, 1);
390 led_state = 1 - led_state;
395 static const iomux_cfg_t stk5_pads[] = {
396 /* SW controlled LED on STK5 baseboard */
397 MX28_PAD_ENET0_RXD3__GPIO_4_10,
400 static const struct gpio stk5_gpios[] = {
404 vidinfo_t panel_info = {
405 /* set to max. size supported by SoC */
409 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
412 static struct fb_videomode tx28_fb_modes[] = {
414 /* Standard VGA timing */
419 .pixclock = KHZ2PICOS(25175),
426 .vmode = FB_VMODE_NONINTERLACED,
429 /* Emerging ETV570 640 x 480 display. Syncs low active,
430 * DE high active, 115.2 mm x 86.4 mm display area
431 * VGA compatible timing
437 .pixclock = KHZ2PICOS(25175),
444 .vmode = FB_VMODE_NONINTERLACED,
447 /* Emerging ET0350G0DH6 320 x 240 display.
448 * 70.08 mm x 52.56 mm display area.
454 .pixclock = KHZ2PICOS(6500),
455 .left_margin = 68 - 34,
458 .upper_margin = 18 - 3,
461 .vmode = FB_VMODE_NONINTERLACED,
464 /* Emerging ET0430G0DH6 480 x 272 display.
465 * 95.04 mm x 53.856 mm display area.
471 .pixclock = KHZ2PICOS(9000),
478 .sync = FB_SYNC_CLK_LAT_FALL,
479 .vmode = FB_VMODE_NONINTERLACED,
482 /* Emerging ET0500G0DH6 800 x 480 display.
483 * 109.6 mm x 66.4 mm display area.
489 .pixclock = KHZ2PICOS(33260),
490 .left_margin = 216 - 128,
492 .right_margin = 1056 - 800 - 216,
493 .upper_margin = 35 - 2,
495 .lower_margin = 525 - 480 - 35,
496 .vmode = FB_VMODE_NONINTERLACED,
499 /* Emerging ETQ570G0DH6 320 x 240 display.
500 * 115.2 mm x 86.4 mm display area.
506 .pixclock = KHZ2PICOS(6400),
510 .upper_margin = 16, /* 15 according to datasheet */
511 .vsync_len = 3, /* TVP -> 1>x>5 */
512 .lower_margin = 4, /* 4.5 according to datasheet */
513 .vmode = FB_VMODE_NONINTERLACED,
516 /* Emerging ET0700G0DH6 800 x 480 display.
517 * 152.4 mm x 91.44 mm display area.
523 .pixclock = KHZ2PICOS(33260),
524 .left_margin = 216 - 128,
526 .right_margin = 1056 - 800 - 216,
527 .upper_margin = 35 - 2,
529 .lower_margin = 525 - 480 - 35,
530 .vmode = FB_VMODE_NONINTERLACED,
533 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
534 .vmode = FB_VMODE_NONINTERLACED,
538 static int lcd_enabled = 1;
539 static int lcd_bl_polarity;
541 static int lcd_backlight_polarity(void)
543 return lcd_bl_polarity;
546 void lcd_enable(void)
549 * global variable from common/lcd.c
550 * Set to 0 here to prevent messages from going to LCD
551 * rather than serial console
555 karo_load_splashimage(1);
557 debug("Switching LCD on\n");
558 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
560 gpio_set_value(TX28_LCD_RST_GPIO, 1);
562 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
563 lcd_backlight_polarity());
567 void lcd_disable(void)
571 void lcd_panel_disable(void)
574 debug("Switching LCD off\n");
575 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
576 !lcd_backlight_polarity());
577 gpio_set_value(TX28_LCD_RST_GPIO, 0);
578 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
582 static const iomux_cfg_t stk5_lcd_pads[] = {
584 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
585 /* LCD POWER_ENABLE */
586 MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
587 /* LCD Backlight (PWM) */
588 MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
591 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
592 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
593 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
594 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
595 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
596 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
597 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
598 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
599 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
600 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
601 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
602 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
603 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
604 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
605 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
606 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
607 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
608 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
609 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
610 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
611 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
612 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
613 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
614 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
615 MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
616 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
617 MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
618 MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
621 static const struct gpio stk5_lcd_gpios[] = {
622 { TX28_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
623 { TX28_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
624 { TX28_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
627 void lcd_ctrl_init(void *lcdbase)
629 int color_depth = 24;
630 const char *video_mode = karo_get_vmode(getenv("video_mode"));
634 struct fb_videomode *p = tx28_fb_modes;
635 struct fb_videomode fb_mode;
636 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
639 debug("LCD disabled\n");
644 debug("Disabling LCD\n");
646 setenv("splashimage", NULL);
651 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
653 if (video_mode == NULL) {
654 debug("Disabling LCD\n");
659 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
661 debug("Using video mode from FDT\n");
663 if (fb_mode.xres > panel_info.vl_col ||
664 fb_mode.yres > panel_info.vl_row) {
665 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
666 fb_mode.xres, fb_mode.yres,
667 panel_info.vl_col, panel_info.vl_row);
673 debug("Trying compiled-in video modes\n");
674 while (p->name != NULL) {
675 if (strcmp(p->name, vm) == 0) {
676 debug("Using video mode: '%s'\n", p->name);
683 debug("Trying to decode video_mode: '%s'\n", vm);
684 while (*vm != '\0') {
685 if (*vm >= '0' && *vm <= '9') {
688 val = simple_strtoul(vm, &end, 0);
691 if (val > panel_info.vl_col)
692 val = panel_info.vl_col;
694 panel_info.vl_col = val;
696 } else if (!yres_set) {
697 if (val > panel_info.vl_row)
698 val = panel_info.vl_row;
700 panel_info.vl_row = val;
702 } else if (!bpp_set) {
712 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
713 end - vm, vm, color_depth);
716 } else if (!refresh_set) {
743 if (p->xres == 0 || p->yres == 0) {
744 printf("Invalid video mode: %s\n", getenv("video_mode"));
746 printf("Supported video modes are:");
747 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
748 printf(" %s", p->name);
753 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
754 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
755 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
759 panel_info.vl_col = p->xres;
760 panel_info.vl_row = p->yres;
762 switch (color_depth) {
764 panel_info.vl_bpix = LCD_COLOR8;
767 panel_info.vl_bpix = LCD_COLOR16;
770 panel_info.vl_bpix = LCD_COLOR32;
773 p->pixclock = KHZ2PICOS(refresh *
774 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
775 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
777 debug("Pixel clock set to %lu.%03lu MHz\n",
778 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
783 debug("Creating new display-timing node from '%s'\n",
785 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
787 printf("Failed to create new display-timing node from '%s': %d\n",
791 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
792 mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
793 ARRAY_SIZE(stk5_lcd_pads));
795 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
796 color_depth, refresh);
798 if (karo_load_splashimage(0) == 0) {
801 /* setup env variable for mxsfb display driver */
802 snprintf(vmode, sizeof(vmode),
803 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
804 p->xres, p->yres, p->left_margin, p->right_margin,
805 p->upper_margin, p->lower_margin, p->hsync_len,
806 p->vsync_len, p->sync, p->pixclock, color_depth);
807 setenv("videomode", vmode);
809 debug("Initializing LCD controller\n");
811 setenv("videomode", NULL);
813 debug("Skipping initialization of LCD controller\n");
817 #define lcd_enabled 0
818 #endif /* CONFIG_LCD */
820 static void stk5_board_init(void)
822 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
823 mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
826 static void stk5v3_board_init(void)
831 static void stk5v5_board_init(void)
835 /* init flexcan transceiver enable GPIO */
836 gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH,
837 "Flexcan Transceiver");
838 mxs_iomux_setup_pad(STK5_CAN_XCVR_GPIO);
841 int board_late_init(void)
844 const char *baseboard;
849 setenv_ulong("safeboot", 1);
853 baseboard = getenv("baseboard");
857 printf("Baseboard: %s\n", baseboard);
859 if (strncmp(baseboard, "stk5", 4) == 0) {
860 if ((strlen(baseboard) == 4) ||
861 strcmp(baseboard, "stk5-v3") == 0) {
863 } else if (strcmp(baseboard, "stk5-v5") == 0) {
864 const char *otg_mode = getenv("otg_mode");
866 if (otg_mode && strcmp(otg_mode, "host") == 0) {
867 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
868 otg_mode, baseboard);
869 setenv("otg_mode", "none");
873 printf("WARNING: Unsupported STK5 board rev.: %s\n",
877 printf("WARNING: Unsupported baseboard: '%s'\n",
889 #define BOOT_CAUSE_MASK (RTC_PERSISTENT0_EXTERNAL_RESET | \
890 RTC_PERSISTENT0_ALARM_WAKE | \
891 RTC_PERSISTENT0_THERMAL_RESET)
893 static void thermal_init(void)
895 struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
896 struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
898 writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
899 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
900 &power_regs->hw_power_thermal);
902 writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
903 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
904 &clkctrl_regs->hw_clkctrl_reset);
909 struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
910 u32 pwr_sts = readl(&power_regs->hw_power_sts);
911 u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
912 const char *dlm = "";
914 printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
915 CONFIG_SYS_SDRAM_SIZE / SZ_128M +
916 CONFIG_SYS_NAND_BLOCKS / 2048 * 2);
918 printf("POWERUP Source: ");
919 if (pwrup_src & (3 << 0)) {
920 printf("%sPSWITCH %s voltage", dlm,
921 pwrup_src & (1 << 1) ? "HIGH" : "MID");
924 if (pwrup_src & (1 << 4)) {
925 printf("%sRTC", dlm);
928 if (pwrup_src & (1 << 5)) {
934 if (boot_cause & BOOT_CAUSE_MASK) {
936 printf("Last boot cause: ");
937 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
938 printf("%sEXTERNAL", dlm);
941 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
942 printf("%sTHERMAL", dlm);
947 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
948 printf("%sALARM WAKE", dlm);
954 while (pwr_sts & POWER_STS_THERMAL_WARNING) {
955 static int first = 1;
958 printf("CPU too hot to boot\n");
963 pwr_sts = readl(&power_regs->hw_power_sts);
966 if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
972 #if defined(CONFIG_OF_BOARD_SETUP)
973 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
974 #include <jffs2/jffs2.h>
975 #include <mtd_node.h>
976 static struct node_info tx28_nand_nodes[] = {
977 { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
980 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
983 static const char *tx28_touchpanels[] = {
989 int ft_board_setup(void *blob, bd_t *bd)
991 const char *baseboard = getenv("baseboard");
992 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
993 const char *video_mode = karo_get_vmode(getenv("video_mode"));
996 ret = fdt_increase_size(blob, 4096);
998 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1001 #ifdef CONFIG_TX28_S
1002 /* TX28-41xx (aka TX28S) has no external RTC
1003 * and no I2C GPIO extender
1005 karo_fdt_remove_node(blob, "ds1339");
1006 karo_fdt_remove_node(blob, "gpio5");
1009 karo_fdt_enable_node(blob, "stk5led", 0);
1011 fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
1013 karo_fdt_fixup_touchpanel(blob, tx28_touchpanels,
1014 ARRAY_SIZE(tx28_touchpanels));
1015 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1016 karo_fdt_fixup_flexcan(blob, stk5_v5);
1017 karo_fdt_update_fb_mode(blob, video_mode);
1021 #endif /* CONFIG_OF_BOARD_SETUP */