275965950ce8f9c8f863de3d812ebe5fd0210367
[karo-tx-uboot.git] / board / karo / tx28 / tx28.c
1 /*
2  * Copyright (C) 2011-2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18
19 #include <common.h>
20 #include <errno.h>
21 #include <libfdt.h>
22 #include <fdt_support.h>
23 #include <lcd.h>
24 #include <netdev.h>
25 #include <mmc.h>
26 #include <mxcfb.h>
27 #include <video_fb.h>
28 #include <linux/list.h>
29 #include <linux/fb.h>
30 #include <asm/io.h>
31 #include <asm/gpio.h>
32 #include <asm/arch/iomux-mx28.h>
33 #include <asm/arch/clock.h>
34 #include <asm/arch/imx-regs.h>
35 #include <asm/arch/sys_proto.h>
36
37 #include "../common/karo.h"
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 #define MXS_GPIO_NR(p, o)      (((p) << 5) | (o))
42
43 #define TX28_LCD_PWR_GPIO       MX28_PAD_LCD_ENABLE__GPIO_1_31
44 #define TX28_LCD_RST_GPIO       MX28_PAD_LCD_RESET__GPIO_3_30
45 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
46
47 #define TX28_USBH_VBUSEN_GPIO   MX28_PAD_SPDIF__GPIO_3_27
48 #define TX28_USBH_OC_GPIO       MX28_PAD_JTAG_RTCK__GPIO_4_20
49 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
50 #define TX28_USBOTG_OC_GPIO     MX28_PAD_GPMI_CE3N__GPIO_0_19
51 #define TX28_USBOTG_ID_GPIO     MX28_PAD_PWM2__GPIO_3_18
52
53 #define TX28_LED_GPIO           MX28_PAD_ENET0_RXD3__GPIO_4_10
54
55 #define STK5_CAN_XCVR_GPIO      MX28_PAD_LCD_D00__GPIO_1_0
56
57 #define ENET_PAD_CTRL           (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
58 #define GPIO_PAD_CTRL           (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
59 #define I2C_PAD_CTRL            (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
60
61 static const struct gpio tx28_gpios[] = {
62         { TX28_USBH_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBH VBUSEN", },
63         { TX28_USBH_OC_GPIO, GPIOFLAG_INPUT, "USBH OC", },
64         { TX28_USBOTG_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
65         { TX28_USBOTG_OC_GPIO, GPIOFLAG_INPUT, "USBOTG OC", },
66         { TX28_USBOTG_ID_GPIO, GPIOFLAG_INPUT, "USBOTG ID", },
67 };
68
69 static const iomux_cfg_t tx28_pads[] = {
70         /* UART pads */
71 #if CONFIG_CONS_INDEX == 0
72         MX28_PAD_AUART0_RX__DUART_CTS,
73         MX28_PAD_AUART0_TX__DUART_RTS,
74         MX28_PAD_AUART0_CTS__DUART_RX,
75         MX28_PAD_AUART0_RTS__DUART_TX,
76 #elif CONFIG_CONS_INDEX == 1
77         MX28_PAD_AUART1_RX__AUART1_RX,
78         MX28_PAD_AUART1_TX__AUART1_TX,
79         MX28_PAD_AUART1_CTS__AUART1_CTS,
80         MX28_PAD_AUART1_RTS__AUART1_RTS,
81 #elif CONFIG_CONS_INDEX == 2
82         MX28_PAD_AUART3_RX__AUART3_RX,
83         MX28_PAD_AUART3_TX__AUART3_TX,
84         MX28_PAD_AUART3_CTS__AUART3_CTS,
85         MX28_PAD_AUART3_RTS__AUART3_RTS,
86 #endif
87         /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
88         MX28_PAD_I2C0_SCL__I2C0_SCL | I2C_PAD_CTRL,
89         MX28_PAD_I2C0_SDA__I2C0_SDA | I2C_PAD_CTRL,
90
91         /* USBH VBUSEN, OC */
92         MX28_PAD_SPDIF__GPIO_3_27,
93         MX28_PAD_JTAG_RTCK__GPIO_4_20,
94
95         /* USBOTG VBUSEN, OC, ID */
96         MX28_PAD_GPMI_CE2N__GPIO_0_18,
97         MX28_PAD_GPMI_CE3N__GPIO_0_19,
98         MX28_PAD_PWM2__GPIO_3_18,
99 };
100
101 /*
102  * Functions
103  */
104
105 /* provide at least _some_ sort of randomness */
106 #define MAX_LOOPS       100
107
108 static u32 random __attribute__((section("data")));
109
110 static inline void random_init(void)
111 {
112         struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
113         u32 seed = 0;
114         int i;
115
116         for (i = 0; i < MAX_LOOPS; i++) {
117                 u32 hclk = readl(&digctl_regs->hw_digctl_hclkcount);
118                 u32 entropy = readl(&digctl_regs->hw_digctl_entropy);
119                 u32 usec = readl(&digctl_regs->hw_digctl_microseconds);
120
121                 seed = get_timer(hclk ^ entropy ^ usec ^ random ^ seed);
122                 srand(seed);
123                 random = rand();
124         }
125 }
126
127 #define RTC_PERSISTENT0_CLK32_MASK      (RTC_PERSISTENT0_CLOCKSOURCE |  \
128                                         RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
129 static u32 boot_cause __attribute__((section("data")));
130
131 int board_early_init_f(void)
132 {
133         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
134         u32 rtc_stat;
135         int timeout = 5000;
136
137         random_init();
138
139         /* IO0 clock at 480MHz */
140         mxs_set_ioclk(MXC_IOCLK0, 480000);
141         /* IO1 clock at 480MHz */
142         mxs_set_ioclk(MXC_IOCLK1, 480000);
143
144         /* SSP0 clock at 96MHz */
145         mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
146         /* SSP2 clock at 96MHz */
147         mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
148
149         gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
150         mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
151
152         while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
153                 RTC_STAT_STALE_REGS_PERSISTENT0) {
154                 if (timeout-- < 0)
155                         return 1;
156                 udelay(1);
157         }
158         boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
159         if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
160                 RTC_PERSISTENT0_CLK32_MASK) {
161                 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
162                         goto rtc_err;
163                 writel(RTC_PERSISTENT0_CLK32_MASK,
164                         &rtc_regs->hw_rtc_persistent0_set);
165         }
166         return 0;
167
168 rtc_err:
169         serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
170         return 1;
171 }
172
173 int board_init(void)
174 {
175         if (ctrlc())
176                 printf("CTRL-C detected; safeboot enabled\n");
177
178         /* Address of boot parameters */
179 #ifdef CONFIG_OF_LIBFDT
180         gd->bd->bi_arch_number = -1;
181 #endif
182         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
183         return 0;
184 }
185
186 int dram_init(void)
187 {
188         return mxs_dram_init();
189 }
190
191 #ifdef  CONFIG_CMD_MMC
192 static int tx28_mmc_wp(int dev_no)
193 {
194         return 0;
195 }
196
197 int board_mmc_init(bd_t *bis)
198 {
199         return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
200 }
201 #endif /* CONFIG_CMD_MMC */
202
203 #ifdef CONFIG_FEC_MXC
204 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
205
206 #ifndef CONFIG_TX28_S
207 #define FEC_MAX_IDX                     1
208 #else
209 #define FEC_MAX_IDX                     0
210 #endif
211 #ifndef ETH_ALEN
212 #define ETH_ALEN                        6
213 #endif
214
215 static int fec_get_mac_addr(int index)
216 {
217         int timeout = 1000;
218         struct mxs_ocotp_regs *ocotp_regs =
219                 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
220         u32 *cust = &ocotp_regs->hw_ocotp_cust0;
221         u8 mac[ETH_ALEN];
222         char env_name[] = "eth.addr";
223         u32 val = 0;
224         int i;
225
226         if (index < 0 || index > FEC_MAX_IDX)
227                 return -EINVAL;
228
229         /* set this bit to open the OTP banks for reading */
230         writel(OCOTP_CTRL_RD_BANK_OPEN,
231                 &ocotp_regs->hw_ocotp_ctrl_set);
232
233         /* wait until OTP contents are readable */
234         while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
235                 if (timeout-- < 0)
236                         return -ETIMEDOUT;
237                 udelay(100);
238         }
239
240         for (i = 0; i < sizeof(mac); i++) {
241                 int shift = 24 - i % 4 * 8;
242
243                 if (i % 4 == 0)
244                         val = readl(&cust[index * 8 + i]);
245                 mac[i] = val >> shift;
246         }
247         if (!is_valid_ethaddr(mac)) {
248                 if (index == 0)
249                         printf("No valid MAC address programmed\n");
250                 return 0;
251         }
252
253         if (index == 0) {
254                 printf("MAC addr from fuse: %pM\n", mac);
255                 snprintf(env_name, sizeof(env_name), "ethaddr");
256         } else {
257                 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
258         }
259         eth_setenv_enetaddr(env_name, mac);
260         return 0;
261 }
262
263 static inline int tx28_fec1_enabled(void)
264 {
265         const char *status;
266         int off;
267
268         if (!gd->fdt_blob)
269                 return 0;
270
271         off = fdt_path_offset(gd->fdt_blob, "ethernet1");
272         if (off < 0)
273                 return 0;
274
275         status = fdt_getprop(gd->fdt_blob, off, "status", NULL);
276         return status && (strcmp(status, "okay") == 0);
277 }
278
279 static void tx28_init_mac(void)
280 {
281         int ret;
282
283         ret = fec_get_mac_addr(0);
284         if (ret < 0) {
285                 printf("Failed to read FEC0 MAC address from OCOTP\n");
286                 return;
287         }
288 #ifdef CONFIG_TX28_S
289         if (tx28_fec1_enabled()) {
290                 ret = fec_get_mac_addr(1);
291                 if (ret < 0) {
292                         printf("Failed to read FEC1 MAC address from OCOTP\n");
293                         return;
294                 }
295         }
296 #endif
297 }
298 #else
299 static inline void tx28_init_mac(void)
300 {
301 }
302 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
303
304 static const iomux_cfg_t tx28_fec_pads[] = {
305         MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | ENET_PAD_CTRL,
306         MX28_PAD_ENET0_RXD0__ENET0_RXD0 | ENET_PAD_CTRL,
307         MX28_PAD_ENET0_RXD1__ENET0_RXD1 | ENET_PAD_CTRL,
308 };
309
310 int board_eth_init(bd_t *bis)
311 {
312         int ret;
313
314         /* Reset the external phy */
315         gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
316
317         /* Power on the external phy */
318         gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
319
320         /* Pull strap pins to high */
321         gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
322         gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
323         gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
324         gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
325
326         udelay(25000);
327         gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
328         udelay(100);
329
330         mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
331
332         ret = cpu_eth_init(bis);
333         if (ret) {
334                 printf("cpu_eth_init() failed: %d\n", ret);
335                 return ret;
336         }
337
338 #ifndef CONFIG_TX28_S
339         if (getenv("ethaddr")) {
340                 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
341                 if (ret) {
342                         printf("FEC MXS: Unable to init FEC0\n");
343                         return ret;
344                 }
345         }
346
347         if (getenv("eth1addr")) {
348                 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
349                 if (ret) {
350                         printf("FEC MXS: Unable to init FEC1\n");
351                         return ret;
352                 }
353         }
354 #else
355         if (getenv("ethaddr")) {
356                 ret = fecmxc_initialize(bis);
357                 if (ret) {
358                         printf("FEC MXS: Unable to init FEC\n");
359                         return ret;
360                 }
361         }
362 #endif
363         return 0;
364 }
365 #else
366 static inline void tx28_init_mac(void)
367 {
368 }
369 #endif /* CONFIG_FEC_MXC */
370
371 enum {
372         LED_STATE_INIT = -1,
373         LED_STATE_OFF,
374         LED_STATE_ON,
375 };
376
377 void show_activity(int arg)
378 {
379         static int led_state = LED_STATE_INIT;
380         static ulong last;
381
382         if (led_state == LED_STATE_INIT) {
383                 last = get_timer(0);
384                 gpio_set_value(TX28_LED_GPIO, 1);
385                 led_state = LED_STATE_ON;
386         } else {
387                 if (get_timer(last) > CONFIG_SYS_HZ) {
388                         last = get_timer(0);
389                         if (led_state == LED_STATE_ON) {
390                                 gpio_set_value(TX28_LED_GPIO, 0);
391                         } else {
392                                 gpio_set_value(TX28_LED_GPIO, 1);
393                         }
394                         led_state = 1 - led_state;
395                 }
396         }
397 }
398
399 static const iomux_cfg_t stk5_pads[] = {
400         /* SW controlled LED on STK5 baseboard */
401         MX28_PAD_ENET0_RXD3__GPIO_4_10 | GPIO_PAD_CTRL,
402 };
403
404 static const struct gpio stk5_gpios[] = {
405 };
406
407 #ifdef CONFIG_LCD
408 vidinfo_t panel_info = {
409         /* set to max. size supported by SoC */
410         .vl_col = 1600,
411         .vl_row = 1200,
412
413         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
414 };
415
416 static struct fb_videomode tx28_fb_modes[] = {
417         {
418                 /* Standard VGA timing */
419                 .name           = "VGA",
420                 .refresh        = 60,
421                 .xres           = 640,
422                 .yres           = 480,
423                 .pixclock       = KHZ2PICOS(25175),
424                 .left_margin    = 48,
425                 .hsync_len      = 96,
426                 .right_margin   = 16,
427                 .upper_margin   = 31,
428                 .vsync_len      = 2,
429                 .lower_margin   = 12,
430                 .vmode          = FB_VMODE_NONINTERLACED,
431         },
432         {
433                 /* Emerging ETV570 640 x 480 display. Syncs low active,
434                  * DE high active, 115.2 mm x 86.4 mm display area
435                  * VGA compatible timing
436                  */
437                 .name           = "ETV570",
438                 .refresh        = 60,
439                 .xres           = 640,
440                 .yres           = 480,
441                 .pixclock       = KHZ2PICOS(25175),
442                 .left_margin    = 114,
443                 .hsync_len      = 30,
444                 .right_margin   = 16,
445                 .upper_margin   = 32,
446                 .vsync_len      = 3,
447                 .lower_margin   = 10,
448                 .vmode          = FB_VMODE_NONINTERLACED,
449         },
450         {
451                 /* Emerging ET0350G0DH6 320 x 240 display.
452                  * 70.08 mm x 52.56 mm display area.
453                  */
454                 .name           = "ET0350",
455                 .refresh        = 60,
456                 .xres           = 320,
457                 .yres           = 240,
458                 .pixclock       = KHZ2PICOS(6500),
459                 .left_margin    = 68 - 34,
460                 .hsync_len      = 34,
461                 .right_margin   = 20,
462                 .upper_margin   = 18 - 3,
463                 .vsync_len      = 3,
464                 .lower_margin   = 4,
465                 .vmode          = FB_VMODE_NONINTERLACED,
466         },
467         {
468                 /* Emerging ET0430G0DH6 480 x 272 display.
469                  * 95.04 mm x 53.856 mm display area.
470                  */
471                 .name           = "ET0430",
472                 .refresh        = 60,
473                 .xres           = 480,
474                 .yres           = 272,
475                 .pixclock       = KHZ2PICOS(9000),
476                 .left_margin    = 2,
477                 .hsync_len      = 41,
478                 .right_margin   = 2,
479                 .upper_margin   = 2,
480                 .vsync_len      = 10,
481                 .lower_margin   = 2,
482                 .sync           = FB_SYNC_CLK_LAT_FALL,
483                 .vmode          = FB_VMODE_NONINTERLACED,
484         },
485         {
486                 /* Emerging ET0500G0DH6 800 x 480 display.
487                  * 109.6 mm x 66.4 mm display area.
488                  */
489                 .name           = "ET0500",
490                 .refresh        = 60,
491                 .xres           = 800,
492                 .yres           = 480,
493                 .pixclock       = KHZ2PICOS(33260),
494                 .left_margin    = 216 - 128,
495                 .hsync_len      = 128,
496                 .right_margin   = 1056 - 800 - 216,
497                 .upper_margin   = 35 - 2,
498                 .vsync_len      = 2,
499                 .lower_margin   = 525 - 480 - 35,
500                 .vmode          = FB_VMODE_NONINTERLACED,
501         },
502         {
503                 /* Emerging ETQ570G0DH6 320 x 240 display.
504                  * 115.2 mm x 86.4 mm display area.
505                  */
506                 .name           = "ETQ570",
507                 .refresh        = 60,
508                 .xres           = 320,
509                 .yres           = 240,
510                 .pixclock       = KHZ2PICOS(6400),
511                 .left_margin    = 38,
512                 .hsync_len      = 30,
513                 .right_margin   = 30,
514                 .upper_margin   = 16, /* 15 according to datasheet */
515                 .vsync_len      = 3, /* TVP -> 1>x>5 */
516                 .lower_margin   = 4, /* 4.5 according to datasheet */
517                 .vmode          = FB_VMODE_NONINTERLACED,
518         },
519         {
520                 /* Emerging ET0700G0DH6 800 x 480 display.
521                  * 152.4 mm x 91.44 mm display area.
522                  */
523                 .name           = "ET0700",
524                 .refresh        = 60,
525                 .xres           = 800,
526                 .yres           = 480,
527                 .pixclock       = KHZ2PICOS(33260),
528                 .left_margin    = 216 - 128,
529                 .hsync_len      = 128,
530                 .right_margin   = 1056 - 800 - 216,
531                 .upper_margin   = 35 - 2,
532                 .vsync_len      = 2,
533                 .lower_margin   = 525 - 480 - 35,
534                 .vmode          = FB_VMODE_NONINTERLACED,
535         },
536         {
537                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
538                 .vmode          = FB_VMODE_NONINTERLACED,
539         },
540 };
541
542 static int lcd_enabled = 1;
543 static int lcd_bl_polarity;
544
545 static int lcd_backlight_polarity(void)
546 {
547         return lcd_bl_polarity;
548 }
549
550 void lcd_enable(void)
551 {
552         /* HACK ALERT:
553          * global variable from common/lcd.c
554          * Set to 0 here to prevent messages from going to LCD
555          * rather than serial console
556          */
557         lcd_is_enabled = 0;
558
559         karo_load_splashimage(1);
560         if (lcd_enabled) {
561                 debug("Switching LCD on\n");
562                 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
563                 udelay(100);
564                 gpio_set_value(TX28_LCD_RST_GPIO, 1);
565                 udelay(300000);
566                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
567                         lcd_backlight_polarity());
568         }
569 }
570
571 void lcd_disable(void)
572 {
573 }
574
575 void lcd_panel_disable(void)
576 {
577         if (lcd_enabled) {
578                 debug("Switching LCD off\n");
579                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
580                         !lcd_backlight_polarity());
581                 gpio_set_value(TX28_LCD_RST_GPIO, 0);
582                 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
583         }
584 }
585
586 static const iomux_cfg_t stk5_lcd_pads[] = {
587         /* LCD RESET */
588         MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
589         /* LCD POWER_ENABLE */
590         MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
591         /* LCD Backlight (PWM) */
592         MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
593
594         /* Display */
595         MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
596         MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
597         MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
598         MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
599         MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
600         MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
601         MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
602         MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
603         MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
604         MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
605         MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
606         MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
607         MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
608         MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
609         MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
610         MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
611         MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
612         MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
613         MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
614         MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
615         MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
616         MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
617         MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
618         MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
619         MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
620         MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
621         MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
622         MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
623 };
624
625 static const struct gpio stk5_lcd_gpios[] = {
626         { TX28_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
627         { TX28_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
628         { TX28_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
629 };
630
631 void lcd_ctrl_init(void *lcdbase)
632 {
633         int color_depth = 24;
634         const char *video_mode = karo_get_vmode(getenv("video_mode"));
635         const char *vm;
636         unsigned long val;
637         int refresh = 60;
638         struct fb_videomode *p = tx28_fb_modes;
639         struct fb_videomode fb_mode;
640         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
641
642         if (!lcd_enabled) {
643                 debug("LCD disabled\n");
644                 return;
645         }
646
647         if (had_ctrlc()) {
648                 debug("Disabling LCD\n");
649                 lcd_enabled = 0;
650                 setenv("splashimage", NULL);
651                 return;
652         }
653
654         karo_fdt_move_fdt();
655         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
656
657         if (video_mode == NULL) {
658                 debug("Disabling LCD\n");
659                 lcd_enabled = 0;
660                 return;
661         }
662         vm = video_mode;
663         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
664                 p = &fb_mode;
665                 debug("Using video mode from FDT\n");
666                 vm += strlen(vm);
667                 if (fb_mode.xres > panel_info.vl_col ||
668                         fb_mode.yres > panel_info.vl_row) {
669                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
670                                 fb_mode.xres, fb_mode.yres,
671                                 panel_info.vl_col, panel_info.vl_row);
672                         lcd_enabled = 0;
673                         return;
674                 }
675         }
676         if (p->name != NULL)
677                 debug("Trying compiled-in video modes\n");
678         while (p->name != NULL) {
679                 if (strcmp(p->name, vm) == 0) {
680                         debug("Using video mode: '%s'\n", p->name);
681                         vm += strlen(vm);
682                         break;
683                 }
684                 p++;
685         }
686         if (*vm != '\0')
687                 debug("Trying to decode video_mode: '%s'\n", vm);
688         while (*vm != '\0') {
689                 if (*vm >= '0' && *vm <= '9') {
690                         char *end;
691
692                         val = simple_strtoul(vm, &end, 0);
693                         if (end > vm) {
694                                 if (!xres_set) {
695                                         if (val > panel_info.vl_col)
696                                                 val = panel_info.vl_col;
697                                         p->xres = val;
698                                         panel_info.vl_col = val;
699                                         xres_set = 1;
700                                 } else if (!yres_set) {
701                                         if (val > panel_info.vl_row)
702                                                 val = panel_info.vl_row;
703                                         p->yres = val;
704                                         panel_info.vl_row = val;
705                                         yres_set = 1;
706                                 } else if (!bpp_set) {
707                                         switch (val) {
708                                         case 8:
709                                         case 16:
710                                         case 18:
711                                         case 24:
712                                                 color_depth = val;
713                                                 break;
714
715                                         default:
716                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
717                                                         end - vm, vm, color_depth);
718                                         }
719                                         bpp_set = 1;
720                                 } else if (!refresh_set) {
721                                         refresh = val;
722                                         refresh_set = 1;
723                                 }
724                         }
725                         vm = end;
726                 }
727                 switch (*vm) {
728                 case '@':
729                         bpp_set = 1;
730                         /* fallthru */
731                 case '-':
732                         yres_set = 1;
733                         /* fallthru */
734                 case 'x':
735                         xres_set = 1;
736                         /* fallthru */
737                 case 'M':
738                 case 'R':
739                         vm++;
740                         break;
741
742                 default:
743                         if (*vm != '\0')
744                                 vm++;
745                 }
746         }
747         if (p->xres == 0 || p->yres == 0) {
748                 printf("Invalid video mode: %s\n", getenv("video_mode"));
749                 lcd_enabled = 0;
750                 printf("Supported video modes are:");
751                 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
752                         printf(" %s", p->name);
753                 }
754                 printf("\n");
755                 return;
756         }
757         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
758                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
759                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
760                 lcd_enabled = 0;
761                 return;
762         }
763         panel_info.vl_col = p->xres;
764         panel_info.vl_row = p->yres;
765
766         switch (color_depth) {
767         case 8:
768                 panel_info.vl_bpix = LCD_COLOR8;
769                 break;
770         case 16:
771                 panel_info.vl_bpix = LCD_COLOR16;
772                 break;
773         default:
774                 panel_info.vl_bpix = LCD_COLOR32;
775         }
776
777         p->pixclock = KHZ2PICOS(refresh *
778                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
779                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
780                                 1000);
781         debug("Pixel clock set to %lu.%03lu MHz\n",
782                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
783
784         if (p != &fb_mode) {
785                 int ret;
786
787                 debug("Creating new display-timing node from '%s'\n",
788                         video_mode);
789                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
790                 if (ret)
791                         printf("Failed to create new display-timing node from '%s': %d\n",
792                                 video_mode, ret);
793         }
794
795         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
796         mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
797                                 ARRAY_SIZE(stk5_lcd_pads));
798
799         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
800                 color_depth, refresh);
801
802         if (karo_load_splashimage(0) == 0) {
803                 char vmode[128];
804
805                 /* setup env variable for mxsfb display driver */
806                 snprintf(vmode, sizeof(vmode),
807                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
808                         p->xres, p->yres, p->left_margin, p->right_margin,
809                         p->upper_margin, p->lower_margin, p->hsync_len,
810                         p->vsync_len, p->sync, p->pixclock, color_depth);
811                 setenv("videomode", vmode);
812
813                 debug("Initializing LCD controller\n");
814                 video_hw_init();
815                 setenv("videomode", NULL);
816         } else {
817                 debug("Skipping initialization of LCD controller\n");
818         }
819 }
820 #else
821 #define lcd_enabled 0
822 #endif /* CONFIG_LCD */
823
824 static void stk5_board_init(void)
825 {
826         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
827         mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
828 }
829
830 static void stk5v3_board_init(void)
831 {
832         stk5_board_init();
833 }
834
835 static void stk5v5_board_init(void)
836 {
837         stk5_board_init();
838
839         /* init flexcan transceiver enable GPIO */
840         gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH,
841                         "Flexcan Transceiver");
842         mxs_iomux_setup_pad(STK5_CAN_XCVR_GPIO);
843 }
844
845 int board_late_init(void)
846 {
847         int ret = 0;
848         const char *baseboard;
849
850         env_cleanup();
851
852         if (had_ctrlc())
853                 setenv_ulong("safeboot", 1);
854         else
855                 karo_fdt_move_fdt();
856
857         baseboard = getenv("baseboard");
858         if (!baseboard)
859                 goto exit;
860
861         printf("Baseboard: %s\n", baseboard);
862
863         if (strncmp(baseboard, "stk5", 4) == 0) {
864                 if ((strlen(baseboard) == 4) ||
865                         strcmp(baseboard, "stk5-v3") == 0) {
866                         stk5v3_board_init();
867                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
868                         const char *otg_mode = getenv("otg_mode");
869
870                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
871                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
872                                         otg_mode, baseboard);
873                                 setenv("otg_mode", "none");
874                         }
875                         stk5v5_board_init();
876                 } else {
877                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
878                                 baseboard + 4);
879                 }
880         } else {
881                 printf("WARNING: Unsupported baseboard: '%s'\n",
882                         baseboard);
883                 if (!had_ctrlc())
884                         ret = -EINVAL;
885         }
886
887 exit:
888         tx28_init_mac();
889         clear_ctrlc();
890         return ret;
891 }
892
893 #define BOOT_CAUSE_MASK         (RTC_PERSISTENT0_EXTERNAL_RESET |       \
894                                 RTC_PERSISTENT0_ALARM_WAKE |            \
895                                 RTC_PERSISTENT0_THERMAL_RESET)
896
897 static void thermal_init(void)
898 {
899         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
900         struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
901
902         writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
903                 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
904                 &power_regs->hw_power_thermal);
905
906         writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
907                 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
908                 &clkctrl_regs->hw_clkctrl_reset);
909 }
910
911 int checkboard(void)
912 {
913         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
914         u32 pwr_sts = readl(&power_regs->hw_power_sts);
915         u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
916         const char *dlm = "";
917
918         printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
919                 CONFIG_SYS_SDRAM_SIZE / SZ_128M +
920                 CONFIG_SYS_NAND_BLOCKS / 2048 * 2);
921
922         printf("POWERUP Source: ");
923         if (pwrup_src & (3 << 0)) {
924                 printf("%sPSWITCH %s voltage", dlm,
925                         pwrup_src & (1 << 1) ? "HIGH" : "MID");
926                 dlm = " | ";
927         }
928         if (pwrup_src & (1 << 4)) {
929                 printf("%sRTC", dlm);
930                 dlm = " | ";
931         }
932         if (pwrup_src & (1 << 5)) {
933                 printf("%s5V", dlm);
934                 dlm = " | ";
935         }
936         printf("\n");
937
938         if (boot_cause & BOOT_CAUSE_MASK) {
939                 dlm="";
940                 printf("Last boot cause: ");
941                 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
942                         printf("%sEXTERNAL", dlm);
943                         dlm = " | ";
944                 }
945                 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
946                         printf("%sTHERMAL", dlm);
947                         dlm = " | ";
948                 }
949                 if (*dlm != '\0')
950                         printf(" RESET");
951                 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
952                         printf("%sALARM WAKE", dlm);
953                         dlm = " | ";
954                 }
955                 printf("\n");
956         }
957
958         while (pwr_sts & POWER_STS_THERMAL_WARNING) {
959                 static int first = 1;
960
961                 if (first) {
962                         printf("CPU too hot to boot\n");
963                         first = 0;
964                 }
965                 if (tstc())
966                         break;
967                 pwr_sts = readl(&power_regs->hw_power_sts);
968         }
969
970         if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
971                 thermal_init();
972
973         return 0;
974 }
975
976 #if defined(CONFIG_OF_BOARD_SETUP)
977 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
978 #include <jffs2/jffs2.h>
979 #include <mtd_node.h>
980 static struct node_info tx28_nand_nodes[] = {
981         { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
982 };
983 #else
984 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
985 #endif
986
987 static const char *tx28_touchpanels[] = {
988         "ti,tsc2007",
989         "edt,edt-ft5x06",
990         "fsl,imx28-lradc",
991 };
992
993 int ft_board_setup(void *blob, bd_t *bd)
994 {
995         const char *baseboard = getenv("baseboard");
996         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
997         const char *video_mode = karo_get_vmode(getenv("video_mode"));
998         int ret;
999
1000         ret = fdt_increase_size(blob, 4096);
1001         if (ret) {
1002                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1003                 return ret;
1004         }
1005 #ifdef CONFIG_TX28_S
1006         /* TX28-41xx (aka TX28S) has no external RTC
1007          * and no I2C GPIO extender
1008          */
1009         karo_fdt_remove_node(blob, "ds1339");
1010         karo_fdt_remove_node(blob, "gpio5");
1011 #endif
1012         if (stk5_v5)
1013                 karo_fdt_enable_node(blob, "stk5led", 0);
1014
1015         fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
1016
1017         karo_fdt_fixup_touchpanel(blob, tx28_touchpanels,
1018                                 ARRAY_SIZE(tx28_touchpanels));
1019         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1020         karo_fdt_fixup_flexcan(blob, stk5_v5);
1021         karo_fdt_update_fb_mode(blob, video_mode);
1022
1023         return 0;
1024 }
1025 #endif /* CONFIG_OF_BOARD_SETUP */