2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <fdt_support.h>
31 #include <imx_ssp_mmc.h>
32 #include <linux/list.h>
36 #include <asm/arch/iomux-mx28.h>
37 #include <asm/arch/clock.h>
38 #include <asm/arch/mxsfb.h>
39 #include <asm/arch/imx-regs.h>
40 #include <asm/arch/sys_proto.h>
42 #include "../common/karo.h"
44 DECLARE_GLOBAL_DATA_PTR;
46 #define MXS_GPIO_NR(p, o) (((p) << 5) | (o))
48 #define TX28_LCD_PWR_GPIO MX28_PAD_LCD_ENABLE__GPIO_1_31
49 #define TX28_LCD_RST_GPIO MX28_PAD_LCD_RESET__GPIO_3_30
50 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
52 #define TX28_USBH_VBUSEN_GPIO MX28_PAD_SPDIF__GPIO_3_27
53 #define TX28_USBH_OC_GPIO MX28_PAD_JTAG_RTCK__GPIO_4_20
54 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
55 #define TX28_USBOTG_OC_GPIO MX28_PAD_GPMI_CE3N__GPIO_0_19
56 #define TX28_USBOTG_ID_GPIO MX28_PAD_PWM2__GPIO_3_18
58 #define TX28_LED_GPIO MX28_PAD_ENET0_RXD3__GPIO_4_10
60 static const struct gpio tx28_gpios[] = {
61 { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
62 { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
63 { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
64 { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
65 { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
68 static const iomux_cfg_t tx28_pads[] = {
70 #if CONFIG_CONS_INDEX == 0
71 MX28_PAD_AUART0_RX__DUART_CTS,
72 MX28_PAD_AUART0_TX__DUART_RTS,
73 MX28_PAD_AUART0_CTS__DUART_RX,
74 MX28_PAD_AUART0_RTS__DUART_TX,
75 #elif CONFIG_CONS_INDEX == 1
76 MX28_PAD_AUART1_RX__AUART1_RX,
77 MX28_PAD_AUART1_TX__AUART1_TX,
78 MX28_PAD_AUART1_CTS__AUART1_CTS,
79 MX28_PAD_AUART1_RTS__AUART1_RTS,
80 #elif CONFIG_CONS_INDEX == 2
81 MX28_PAD_AUART3_RX__AUART3_RX,
82 MX28_PAD_AUART3_TX__AUART3_TX,
83 MX28_PAD_AUART3_CTS__AUART3_CTS,
84 MX28_PAD_AUART3_RTS__AUART3_RTS,
86 /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
87 MX28_PAD_I2C0_SCL__I2C0_SCL,
88 MX28_PAD_I2C0_SDA__I2C0_SDA,
91 MX28_PAD_SPDIF__GPIO_3_27,
92 MX28_PAD_JTAG_RTCK__GPIO_4_20,
94 /* USBOTG VBUSEN, OC, ID */
95 MX28_PAD_GPMI_CE2N__GPIO_0_18,
96 MX28_PAD_GPMI_CE3N__GPIO_0_19,
97 MX28_PAD_PWM2__GPIO_3_18,
103 int board_early_init_f(void)
105 /* IO0 clock at 480MHz */
106 mx28_set_ioclk(MXC_IOCLK0, 480000);
107 /* IO1 clock at 480MHz */
108 mx28_set_ioclk(MXC_IOCLK1, 480000);
110 /* SSP0 clock at 96MHz */
111 mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
112 /* SSP2 clock at 96MHz */
113 mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
115 gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
116 mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
122 /* Address of boot parameters */
123 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
129 return mx28_dram_init();
132 #ifdef CONFIG_CMD_MMC
133 static int tx28_mmc_wp(int dev_no)
138 int board_mmc_init(bd_t *bis)
140 return mxsmmc_initialize(bis, 0, tx28_mmc_wp);
142 #endif /* CONFIG_CMD_MMC */
144 #ifdef CONFIG_FEC_MXC
145 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
147 #ifdef CONFIG_FEC_MXC_MULTI
148 #define FEC_MAX_IDX 1
150 #define FEC_MAX_IDX 0
153 static int fec_get_mac_addr(int index)
157 struct mx28_ocotp_regs *ocotp_regs =
158 (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
159 u32 *cust = &ocotp_regs->hw_ocotp_cust0;
161 char env_name[] = "eth.addr";
163 if (index < 0 || index > FEC_MAX_IDX)
166 /* set this bit to open the OTP banks for reading */
167 writel(OCOTP_CTRL_RD_BANK_OPEN,
168 &ocotp_regs->hw_ocotp_ctrl_set);
170 /* wait until OTP contents are readable */
171 while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
177 val1 = readl(&cust[index * 8]);
178 val2 = readl(&cust[index * 8 + 4]);
179 if ((val1 | val2) == 0)
181 snprintf(mac, sizeof(mac), "%02x:%02x:%02x:%02x:%02x:%02x",
182 (val1 >> 24) & 0xFF, (val1 >> 16) & 0xFF,
183 (val1 >> 8) & 0xFF, (val1 >> 0) & 0xFF,
184 (val2 >> 24) & 0xFF, (val2 >> 16) & 0xFF);
186 snprintf(env_name, sizeof(env_name), "ethaddr");
188 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
190 setenv(env_name, mac);
193 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
195 static const iomux_cfg_t tx28_fec_pads[] = {
196 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
197 MX28_PAD_ENET0_RXD0__ENET0_RXD0,
198 MX28_PAD_ENET0_RXD1__ENET0_RXD1,
201 int board_eth_init(bd_t *bis)
205 /* Reset the external phy */
206 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
208 /* Power on the external phy */
209 gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
211 /* Pull strap pins to high */
212 gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
213 gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
214 gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
215 gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
218 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
221 mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
223 ret = cpu_eth_init(bis);
225 printf("cpu_eth_init() failed: %d\n", ret);
229 ret = fec_get_mac_addr(0);
231 printf("Failed to read FEC0 MAC address from OCOTP\n");
234 #ifdef CONFIG_FEC_MXC_MULTI
235 if (getenv("ethaddr")) {
236 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
238 printf("FEC MXS: Unable to init FEC0\n");
243 ret = fec_get_mac_addr(1);
245 printf("Failed to read FEC1 MAC address from OCOTP\n");
248 if (getenv("eth1addr")) {
249 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
251 printf("FEC MXS: Unable to init FEC1\n");
257 if (getenv("ethaddr")) {
258 ret = fecmxc_initialize(bis);
263 #endif /* CONFIG_FEC_MXC */
271 void show_activity(int arg)
273 static int led_state = LED_STATE_INIT;
276 if (led_state == LED_STATE_INIT) {
278 gpio_set_value(TX28_LED_GPIO, 1);
279 led_state = LED_STATE_ON;
281 if (get_timer(last) > CONFIG_SYS_HZ) {
283 if (led_state == LED_STATE_ON) {
284 gpio_set_value(TX28_LED_GPIO, 0);
286 gpio_set_value(TX28_LED_GPIO, 1);
288 led_state = 1 - led_state;
293 static const iomux_cfg_t stk5_pads[] = {
294 /* SW controlled LED on STK5 baseboard */
295 MX28_PAD_ENET0_RXD3__GPIO_4_10,
298 static const struct gpio stk5_gpios[] = {
302 static struct fb_videomode tx28_fb_modes[] = {
304 /* Standard VGA timing */
309 .pixclock = KHZ2PICOS(25175),
316 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
317 .vmode = FB_VMODE_NONINTERLACED,
320 /* Emerging ETV570 640 x 480 display. Syncs low active,
321 * DE high active, 115.2 mm x 86.4 mm display area
322 * VGA compatible timing
328 .pixclock = KHZ2PICOS(25175),
335 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
336 .vmode = FB_VMODE_NONINTERLACED,
339 /* Emerging ET0350G0DH6 320 x 240 display.
340 * 70.08 mm x 52.56 mm display area.
346 .pixclock = KHZ2PICOS(6500),
347 .left_margin = 68 - 34,
350 .upper_margin = 18 - 3,
353 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
354 .vmode = FB_VMODE_NONINTERLACED,
357 /* Emerging ET0430G0DH6 480 x 272 display.
358 * 95.04 mm x 53.856 mm display area.
364 .pixclock = KHZ2PICOS(9000),
371 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
372 .vmode = FB_VMODE_NONINTERLACED,
375 /* Emerging ET0500G0DH6 800 x 480 display.
376 * 109.6 mm x 66.4 mm display area.
382 .pixclock = KHZ2PICOS(33260),
383 .left_margin = 216 - 128,
385 .right_margin = 1056 - 800 - 216,
386 .upper_margin = 35 - 2,
388 .lower_margin = 525 - 480 - 35,
389 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
390 .vmode = FB_VMODE_NONINTERLACED,
393 /* Emerging ETQ570G0DH6 320 x 240 display.
394 * 115.2 mm x 86.4 mm display area.
400 .pixclock = KHZ2PICOS(6400),
404 .upper_margin = 16, /* 15 according to datasheet */
405 .vsync_len = 3, /* TVP -> 1>x>5 */
406 .lower_margin = 4, /* 4.5 according to datasheet */
407 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
408 .vmode = FB_VMODE_NONINTERLACED,
411 /* Emerging ET0700G0DH6 800 x 480 display.
412 * 152.4 mm x 91.44 mm display area.
418 .pixclock = KHZ2PICOS(33260),
419 .left_margin = 216 - 128,
421 .right_margin = 1056 - 800 - 216,
422 .upper_margin = 35 - 2,
424 .lower_margin = 525 - 480 - 35,
425 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
426 .vmode = FB_VMODE_NONINTERLACED,
429 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
430 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
431 .vmode = FB_VMODE_NONINTERLACED,
435 static int lcd_enabled = 1;
437 void lcd_enable(void)
440 * global variable from common/lcd.c
441 * Set to 0 here to prevent messages from going to LCD
442 * rather than serial console
446 karo_load_splashimage(1);
448 debug("Switching LCD on\n");
449 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
451 gpio_set_value(TX28_LCD_RST_GPIO, 1);
453 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 0);
457 void lcd_disable(void)
462 void lcd_panel_disable(void)
465 debug("Switching LCD off\n");
466 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 1);
467 gpio_set_value(TX28_LCD_RST_GPIO, 0);
468 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
472 static const iomux_cfg_t stk5_lcd_pads[] = {
474 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
475 /* LCD POWER_ENABLE */
476 MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
477 /* LCD Backlight (PWM) */
478 MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
481 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
482 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
483 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
484 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
485 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
486 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
487 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
488 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
489 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
490 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
491 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
492 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
493 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
494 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
495 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
496 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
497 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
498 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
499 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
500 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
501 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
502 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
503 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
504 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
505 MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
506 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
507 MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
508 MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
509 MX28_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
510 MX28_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
511 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
514 static const struct gpio stk5_lcd_gpios[] = {
515 { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
516 { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
517 { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
520 extern void video_hw_init(void *lcdbase);
522 void lcd_ctrl_init(void *lcdbase)
524 int color_depth = 24;
528 struct fb_videomode *p = &tx28_fb_modes[0];
529 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
532 debug("LCD disabled\n");
537 debug("Disabling LCD\n");
542 vm = getenv("video_mode");
544 debug("Disabling LCD\n");
548 while (p->name != NULL) {
549 if (strcmp(p->name, vm) == 0) {
550 printf("Using video mode: '%s'\n", p->name);
557 while (*vm != '\0') {
558 if (*vm >= '0' && *vm <= '9') {
561 val = simple_strtoul(vm, &end, 0);
564 if (val > panel_info.vl_col)
565 val = panel_info.vl_col;
568 } else if (!yres_set) {
569 if (val > panel_info.vl_row)
570 val = panel_info.vl_row;
573 } else if (!bpp_set) {
583 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
584 end - vm, vm, color_depth);
587 } else if (!refresh_set) {
614 if (p->xres == 0 || p->yres == 0) {
615 printf("Invalid video mode: %s\n", getenv("video_mode"));
617 printf("Supported video modes are:");
618 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
619 printf(" %s", p->name);
624 p->pixclock = KHZ2PICOS(refresh *
625 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
626 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
628 debug("Pixel clock set to %lu.%03lu MHz\n",
629 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
631 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
632 mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
633 ARRAY_SIZE(stk5_lcd_pads));
635 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
636 color_depth, refresh);
638 if (karo_load_splashimage(0) == 0) {
639 debug("Initializing LCD controller\n");
640 mxsfb_init(p, PIX_FMT_RGB24, color_depth);
641 video_hw_init(lcdbase);
643 debug("Skipping initialization of LCD controller\n");
647 #define lcd_enabled 0
648 #endif /* CONFIG_LCD */
650 static void stk5_board_init(void)
652 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
653 mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
656 static void stk5v3_board_init(void)
661 static void stk5v5_board_init(void)
665 /* init flexcan transceiver enable GPIO */
666 gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH,
667 "Flexcan Transceiver");
668 mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0);
671 int board_late_init(void)
673 const char *baseboard;
677 baseboard = getenv("baseboard");
681 if (strncmp(baseboard, "stk5", 4) == 0) {
682 printf("Baseboard: %s\n", baseboard);
683 if ((strlen(baseboard) == 4) ||
684 strcmp(baseboard, "stk5-v3") == 0) {
686 } else if (strcmp(baseboard, "stk5-v5") == 0) {
689 printf("WARNING: Unsupported STK5 board rev.: %s\n",
693 printf("WARNING: Unsupported baseboard: '%s'\n",
703 printf("Board: Ka-Ro TX28-4%sxx\n", TX28_MOD_SUFFIX);
707 #if defined(CONFIG_OF_BOARD_SETUP)
708 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
709 #include <jffs2/jffs2.h>
710 #include <mtd_node.h>
711 struct node_info tx28_nand_nodes[] = {
712 { "gpmi-nand", MTD_DEV_TYPE_NAND, },
715 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
718 static void tx28_fixup_flexcan(void *blob)
720 karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x80032000, "transceiver-switch");
721 karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x80034000, "transceiver-switch");
724 static void tx28_fixup_fec(void *blob)
726 karo_fdt_remove_node(blob, "ethernet1");
729 void ft_board_setup(void *blob, bd_t *bd)
731 const char *baseboard = getenv("baseboard");
734 /* TX28-41xx (aka TX28S) has no external RTC
735 * and no I2C GPIO extender
737 karo_fdt_remove_node(blob, "ds1339");
738 karo_fdt_remove_node(blob, "pca9554");
740 if (baseboard != NULL && strcmp(baseboard, "stk5-v5") == 0) {
741 const char *otg_mode = getenv("otg_mode");
743 if (otg_mode && strcmp(otg_mode, "host") == 0) {
744 printf("otg_mode=%s incompatible with baseboard %s\n",
745 otg_mode, baseboard);
746 setenv(otg_mode, "none");
748 karo_fdt_remove_node(blob, "stk5led");
750 tx28_fixup_flexcan(blob);
751 tx28_fixup_fec(blob);
754 if (baseboard != NULL && strcmp(baseboard, "stk5-v3") == 0) {
755 const char *otg_mode = getenv("otg_mode");
757 if (otg_mode && strcmp(otg_mode, "device") == 0)
758 karo_fdt_remove_node(blob, "can1");
761 fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
762 fdt_fixup_ethernet(blob);
764 karo_fdt_fixup_touchpanel(blob);
765 karo_fdt_fixup_usb_otg(blob);