board/karo/tx28/tx28.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <lcd.h>
  24 #include <netdev.h>
  25 #include <mmc.h>
  26 #include <mxcfb.h>
  27 #include <linux/list.h>
  28 #include <linux/fb.h>
  29 #include <asm/io.h>
  30 #include <asm/gpio.h>
  31 #include <asm/arch/iomux-mx28.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/imx-regs.h>
  34 #include <asm/arch/sys_proto.h>
  35
  36 #include "../common/karo.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define MXS_GPIO_NR(p, o)      (((p) << 5) | (o))
  41
  42 #define TX28_LCD_PWR_GPIO       MX28_PAD_LCD_ENABLE__GPIO_1_31
  43 #define TX28_LCD_RST_GPIO       MX28_PAD_LCD_RESET__GPIO_3_30
  44 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
  45
  46 #define TX28_USBH_VBUSEN_GPIO   MX28_PAD_SPDIF__GPIO_3_27
  47 #define TX28_USBH_OC_GPIO       MX28_PAD_JTAG_RTCK__GPIO_4_20
  48 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
  49 #define TX28_USBOTG_OC_GPIO     MX28_PAD_GPMI_CE3N__GPIO_0_19
  50 #define TX28_USBOTG_ID_GPIO     MX28_PAD_PWM2__GPIO_3_18
  51
  52 #define TX28_LED_GPIO           MX28_PAD_ENET0_RXD3__GPIO_4_10
  53
  54 static const struct gpio tx28_gpios[] = {
  55         { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
  56         { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
  57         { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
  58         { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
  59         { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
  60 };
  61
  62 static const iomux_cfg_t tx28_pads[] = {
  63         /* UART pads */
  64 #if CONFIG_CONS_INDEX == 0
  65         MX28_PAD_AUART0_RX__DUART_CTS,
  66         MX28_PAD_AUART0_TX__DUART_RTS,
  67         MX28_PAD_AUART0_CTS__DUART_RX,
  68         MX28_PAD_AUART0_RTS__DUART_TX,
  69 #elif CONFIG_CONS_INDEX == 1
  70         MX28_PAD_AUART1_RX__AUART1_RX,
  71         MX28_PAD_AUART1_TX__AUART1_TX,
  72         MX28_PAD_AUART1_CTS__AUART1_CTS,
  73         MX28_PAD_AUART1_RTS__AUART1_RTS,
  74 #elif CONFIG_CONS_INDEX == 2
  75         MX28_PAD_AUART3_RX__AUART3_RX,
  76         MX28_PAD_AUART3_TX__AUART3_TX,
  77         MX28_PAD_AUART3_CTS__AUART3_CTS,
  78         MX28_PAD_AUART3_RTS__AUART3_RTS,
  79 #endif
  80         /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
  81         MX28_PAD_I2C0_SCL__I2C0_SCL,
  82         MX28_PAD_I2C0_SDA__I2C0_SDA,
  83
  84         /* USBH VBUSEN, OC */
  85         MX28_PAD_SPDIF__GPIO_3_27,
  86         MX28_PAD_JTAG_RTCK__GPIO_4_20,
  87
  88         /* USBOTG VBUSEN, OC, ID */
  89         MX28_PAD_GPMI_CE2N__GPIO_0_18,
  90         MX28_PAD_GPMI_CE3N__GPIO_0_19,
  91         MX28_PAD_PWM2__GPIO_3_18,
  92 };
  93
  94 /*
  95  * Functions
  96  */
  97
  98 /* provide at least _some_ sort of randomness */
  99 #define MAX_LOOPS       100
 100
 101 static u32 random;
 102
 103 static inline void random_init(void)
 104 {
 105         struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
 106         u32 seed = 0;
 107         int i;
 108
 109         for (i = 0; i < MAX_LOOPS; i++) {
 110                 unsigned int usec = readl(&digctl_regs->hw_digctl_microseconds);
 111
 112                 seed = get_timer(usec + random + seed);
 113                 srand(seed);
 114                 random = rand();
 115         }
 116 }
 117
 118 #define RTC_PERSISTENT0_CLK32_MASK      (RTC_PERSISTENT0_CLOCKSOURCE |  \
 119                                         RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
 120 static u32 boot_cause __attribute__((section("data")));
 121
 122 int board_early_init_f(void)
 123 {
 124         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 125         u32 rtc_stat;
 126         int timeout = 5000;
 127
 128         random_init();
 129
 130         /* IO0 clock at 480MHz */
 131         mxs_set_ioclk(MXC_IOCLK0, 480000);
 132         /* IO1 clock at 480MHz */
 133         mxs_set_ioclk(MXC_IOCLK1, 480000);
 134
 135         /* SSP0 clock at 96MHz */
 136         mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 137         /* SSP2 clock at 96MHz */
 138         mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
 139
 140         gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
 141         mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
 142
 143         while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
 144                 RTC_STAT_STALE_REGS_PERSISTENT0) {
 145                 if (timeout-- < 0)
 146                         return 0;
 147                 udelay(1);
 148         }
 149         boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
 150         if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
 151                 RTC_PERSISTENT0_CLK32_MASK) {
 152                 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
 153                         goto rtc_err;
 154                 writel(RTC_PERSISTENT0_CLK32_MASK,
 155                         &rtc_regs->hw_rtc_persistent0_set);
 156         }
 157         return 0;
 158
 159 rtc_err:
 160         serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
 161         return 0;
 162 }
 163
 164 int board_init(void)
 165 {
 166         /* Address of boot parameters */
 167 #ifdef CONFIG_OF_LIBFDT
 168         gd->bd->bi_arch_number = -1;
 169 #endif
 170         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 171         return 0;
 172 }
 173
 174 int dram_init(void)
 175 {
 176         return mxs_dram_init();
 177 }
 178
 179 #ifdef  CONFIG_CMD_MMC
 180 static int tx28_mmc_wp(int dev_no)
 181 {
 182         return 0;
 183 }
 184
 185 int board_mmc_init(bd_t *bis)
 186 {
 187         return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
 188 }
 189 #endif /* CONFIG_CMD_MMC */
 190
 191 #ifdef CONFIG_FEC_MXC
 192 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
 193
 194 #ifdef CONFIG_FEC_MXC_MULTI
 195 #define FEC_MAX_IDX                     1
 196 #else
 197 #define FEC_MAX_IDX                     0
 198 #endif
 199 #ifndef ETH_ALEN
 200 #define ETH_ALEN                        6
 201 #endif
 202
 203 static int fec_get_mac_addr(int index)
 204 {
 205         int timeout = 1000;
 206         struct mxs_ocotp_regs *ocotp_regs =
 207                 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
 208         u32 *cust = &ocotp_regs->hw_ocotp_cust0;
 209         u8 mac[ETH_ALEN];
 210         char env_name[] = "eth.addr";
 211         u32 val = 0;
 212         int i;
 213
 214         if (index < 0 || index > FEC_MAX_IDX)
 215                 return -EINVAL;
 216
 217         /* set this bit to open the OTP banks for reading */
 218         writel(OCOTP_CTRL_RD_BANK_OPEN,
 219                 &ocotp_regs->hw_ocotp_ctrl_set);
 220
 221         /* wait until OTP contents are readable */
 222         while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
 223                 if (timeout-- < 0)
 224                         return -ETIMEDOUT;
 225                 udelay(100);
 226         }
 227
 228         for (i = 0; i < sizeof(mac); i++) {
 229                 int shift = 24 - i % 4 * 8;
 230
 231                 if (i % 4 == 0)
 232                         val = readl(&cust[index * 8 + i]);
 233                 mac[i] = val >> shift;
 234         }
 235         if (!is_valid_ether_addr(mac)) {
 236                 if (index == 0)
 237                         printf("No valid MAC address programmed\n");
 238                 return 0;
 239         }
 240
 241         if (index == 0) {
 242                 printf("MAC addr from fuse: %pM\n", mac);
 243                 snprintf(env_name, sizeof(env_name), "ethaddr");
 244         } else {
 245                 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
 246         }
 247         eth_setenv_enetaddr(env_name, mac);
 248         return 0;
 249 }
 250 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
 251
 252 static const iomux_cfg_t tx28_fec_pads[] = {
 253         MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
 254         MX28_PAD_ENET0_RXD0__ENET0_RXD0,
 255         MX28_PAD_ENET0_RXD1__ENET0_RXD1,
 256 };
 257
 258 int board_eth_init(bd_t *bis)
 259 {
 260         int ret;
 261
 262         /* Reset the external phy */
 263         gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
 264
 265         /* Power on the external phy */
 266         gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
 267
 268         /* Pull strap pins to high */
 269         gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
 270         gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
 271         gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
 272         gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
 273
 274         udelay(25000);
 275         gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
 276         udelay(100);
 277
 278         mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
 279
 280         ret = cpu_eth_init(bis);
 281         if (ret) {
 282                 printf("cpu_eth_init() failed: %d\n", ret);
 283                 return ret;
 284         }
 285
 286 #ifdef CONFIG_FEC_MXC_MULTI
 287         if (getenv("ethaddr")) {
 288                 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
 289                 if (ret) {
 290                         printf("FEC MXS: Unable to init FEC0\n");
 291                         return ret;
 292                 }
 293         }
 294
 295         if (getenv("eth1addr")) {
 296                 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
 297                 if (ret) {
 298                         printf("FEC MXS: Unable to init FEC1\n");
 299                         return ret;
 300                 }
 301         }
 302 #else
 303         if (getenv("ethaddr")) {
 304                 ret = fecmxc_initialize(bis);
 305                 if (ret) {
 306                         printf("FEC MXS: Unable to init FEC\n");
 307                         return ret;
 308                 }
 309         }
 310 #endif
 311         return 0;
 312 }
 313 #endif /* CONFIG_FEC_MXC */
 314
 315 enum {
 316         LED_STATE_INIT = -1,
 317         LED_STATE_OFF,
 318         LED_STATE_ON,
 319 };
 320
 321 void show_activity(int arg)
 322 {
 323         static int led_state = LED_STATE_INIT;
 324         static ulong last;
 325
 326         if (led_state == LED_STATE_INIT) {
 327                 last = get_timer(0);
 328                 gpio_set_value(TX28_LED_GPIO, 1);
 329                 led_state = LED_STATE_ON;
 330         } else {
 331                 if (get_timer(last) > CONFIG_SYS_HZ) {
 332                         last = get_timer(0);
 333                         if (led_state == LED_STATE_ON) {
 334                                 gpio_set_value(TX28_LED_GPIO, 0);
 335                         } else {
 336                                 gpio_set_value(TX28_LED_GPIO, 1);
 337                         }
 338                         led_state = 1 - led_state;
 339                 }
 340         }
 341 }
 342
 343 static const iomux_cfg_t stk5_pads[] = {
 344         /* SW controlled LED on STK5 baseboard */
 345         MX28_PAD_ENET0_RXD3__GPIO_4_10,
 346 };
 347
 348 static const struct gpio stk5_gpios[] = {
 349 };
 350
 351 #ifdef CONFIG_LCD
 352 static ushort tx28_cmap[256];
 353 vidinfo_t panel_info = {
 354         /* set to max. size supported by SoC */
 355         .vl_col = 1600,
 356         .vl_row = 1200,
 357
 358         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 359         .cmap = tx28_cmap,
 360 };
 361
 362 static struct fb_videomode tx28_fb_modes[] = {
 363         {
 364                 /* Standard VGA timing */
 365                 .name           = "VGA",
 366                 .refresh        = 60,
 367                 .xres           = 640,
 368                 .yres           = 480,
 369                 .pixclock       = KHZ2PICOS(25175),
 370                 .left_margin    = 48,
 371                 .hsync_len      = 96,
 372                 .right_margin   = 16,
 373                 .upper_margin   = 31,
 374                 .vsync_len      = 2,
 375                 .lower_margin   = 12,
 376                 .vmode          = FB_VMODE_NONINTERLACED,
 377         },
 378         {
 379                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 380                  * DE high active, 115.2 mm x 86.4 mm display area
 381                  * VGA compatible timing
 382                  */
 383                 .name           = "ETV570",
 384                 .refresh        = 60,
 385                 .xres           = 640,
 386                 .yres           = 480,
 387                 .pixclock       = KHZ2PICOS(25175),
 388                 .left_margin    = 114,
 389                 .hsync_len      = 30,
 390                 .right_margin   = 16,
 391                 .upper_margin   = 32,
 392                 .vsync_len      = 3,
 393                 .lower_margin   = 10,
 394                 .vmode          = FB_VMODE_NONINTERLACED,
 395         },
 396         {
 397                 /* Emerging ET0350G0DH6 320 x 240 display.
 398                  * 70.08 mm x 52.56 mm display area.
 399                  */
 400                 .name           = "ET0350",
 401                 .refresh        = 60,
 402                 .xres           = 320,
 403                 .yres           = 240,
 404                 .pixclock       = KHZ2PICOS(6500),
 405                 .left_margin    = 68 - 34,
 406                 .hsync_len      = 34,
 407                 .right_margin   = 20,
 408                 .upper_margin   = 18 - 3,
 409                 .vsync_len      = 3,
 410                 .lower_margin   = 4,
 411                 .vmode          = FB_VMODE_NONINTERLACED,
 412         },
 413         {
 414                 /* Emerging ET0430G0DH6 480 x 272 display.
 415                  * 95.04 mm x 53.856 mm display area.
 416                  */
 417                 .name           = "ET0430",
 418                 .refresh        = 60,
 419                 .xres           = 480,
 420                 .yres           = 272,
 421                 .pixclock       = KHZ2PICOS(9000),
 422                 .left_margin    = 2,
 423                 .hsync_len      = 41,
 424                 .right_margin   = 2,
 425                 .upper_margin   = 2,
 426                 .vsync_len      = 10,
 427                 .lower_margin   = 2,
 428                 .sync           = FB_SYNC_CLK_LAT_FALL,
 429                 .vmode          = FB_VMODE_NONINTERLACED,
 430         },
 431         {
 432                 /* Emerging ET0500G0DH6 800 x 480 display.
 433                  * 109.6 mm x 66.4 mm display area.
 434                  */
 435                 .name           = "ET0500",
 436                 .refresh        = 60,
 437                 .xres           = 800,
 438                 .yres           = 480,
 439                 .pixclock       = KHZ2PICOS(33260),
 440                 .left_margin    = 216 - 128,
 441                 .hsync_len      = 128,
 442                 .right_margin   = 1056 - 800 - 216,
 443                 .upper_margin   = 35 - 2,
 444                 .vsync_len      = 2,
 445                 .lower_margin   = 525 - 480 - 35,
 446                 .vmode          = FB_VMODE_NONINTERLACED,
 447         },
 448         {
 449                 /* Emerging ETQ570G0DH6 320 x 240 display.
 450                  * 115.2 mm x 86.4 mm display area.
 451                  */
 452                 .name           = "ETQ570",
 453                 .refresh        = 60,
 454                 .xres           = 320,
 455                 .yres           = 240,
 456                 .pixclock       = KHZ2PICOS(6400),
 457                 .left_margin    = 38,
 458                 .hsync_len      = 30,
 459                 .right_margin   = 30,
 460                 .upper_margin   = 16, /* 15 according to datasheet */
 461                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 462                 .lower_margin   = 4, /* 4.5 according to datasheet */
 463                 .vmode          = FB_VMODE_NONINTERLACED,
 464         },
 465         {
 466                 /* Emerging ET0700G0DH6 800 x 480 display.
 467                  * 152.4 mm x 91.44 mm display area.
 468                  */
 469                 .name           = "ET0700",
 470                 .refresh        = 60,
 471                 .xres           = 800,
 472                 .yres           = 480,
 473                 .pixclock       = KHZ2PICOS(33260),
 474                 .left_margin    = 216 - 128,
 475                 .hsync_len      = 128,
 476                 .right_margin   = 1056 - 800 - 216,
 477                 .upper_margin   = 35 - 2,
 478                 .vsync_len      = 2,
 479                 .lower_margin   = 525 - 480 - 35,
 480                 .vmode          = FB_VMODE_NONINTERLACED,
 481         },
 482         {
 483                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 484                 .vmode          = FB_VMODE_NONINTERLACED,
 485         },
 486 };
 487
 488 static int lcd_enabled = 1;
 489 static int lcd_bl_polarity;
 490
 491 static int lcd_backlight_polarity(void)
 492 {
 493         return lcd_bl_polarity;
 494 }
 495
 496 void lcd_enable(void)
 497 {
 498         /* HACK ALERT:
 499          * global variable from common/lcd.c
 500          * Set to 0 here to prevent messages from going to LCD
 501          * rather than serial console
 502          */
 503         lcd_is_enabled = 0;
 504
 505         karo_load_splashimage(1);
 506         if (lcd_enabled) {
 507                 debug("Switching LCD on\n");
 508                 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
 509                 udelay(100);
 510                 gpio_set_value(TX28_LCD_RST_GPIO, 1);
 511                 udelay(300000);
 512                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
 513                         lcd_backlight_polarity());
 514         }
 515 }
 516
 517 void lcd_disable(void)
 518 {
 519 }
 520
 521 void lcd_panel_disable(void)
 522 {
 523         if (lcd_enabled) {
 524                 debug("Switching LCD off\n");
 525                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
 526                         !lcd_backlight_polarity());
 527                 gpio_set_value(TX28_LCD_RST_GPIO, 0);
 528                 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
 529         }
 530 }
 531
 532 static const iomux_cfg_t stk5_lcd_pads[] = {
 533         /* LCD RESET */
 534         MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
 535         /* LCD POWER_ENABLE */
 536         MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
 537         /* LCD Backlight (PWM) */
 538         MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
 539
 540         /* Display */
 541         MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
 542         MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
 543         MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
 544         MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
 545         MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
 546         MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
 547         MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
 548         MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
 549         MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
 550         MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
 551         MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
 552         MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
 553         MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
 554         MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
 555         MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
 556         MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
 557         MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
 558         MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
 559         MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
 560         MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
 561         MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
 562         MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
 563         MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
 564         MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
 565         MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
 566         MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
 567         MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
 568         MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
 569 };
 570
 571 static const struct gpio stk5_lcd_gpios[] = {
 572         { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 573         { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 574         { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 575 };
 576
 577 extern void video_hw_init(void *lcdbase);
 578
 579 void lcd_ctrl_init(void *lcdbase)
 580 {
 581         int color_depth = 24;
 582         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 583         const char *vm;
 584         unsigned long val;
 585         int refresh = 60;
 586         struct fb_videomode *p = tx28_fb_modes;
 587         struct fb_videomode fb_mode;
 588         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 589
 590         if (!lcd_enabled) {
 591                 debug("LCD disabled\n");
 592                 return;
 593         }
 594
 595         if (had_ctrlc()) {
 596                 debug("Disabling LCD\n");
 597                 lcd_enabled = 0;
 598                 setenv("splashimage", NULL);
 599                 return;
 600         }
 601
 602         karo_fdt_move_fdt();
 603         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 604
 605         if (video_mode == NULL) {
 606                 debug("Disabling LCD\n");
 607                 lcd_enabled = 0;
 608                 return;
 609         }
 610         vm = video_mode;
 611         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 612                 p = &fb_mode;
 613                 debug("Using video mode from FDT\n");
 614                 vm += strlen(vm);
 615                 if (fb_mode.xres > panel_info.vl_col ||
 616                         fb_mode.yres > panel_info.vl_row) {
 617                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 618                                 fb_mode.xres, fb_mode.yres,
 619                                 panel_info.vl_col, panel_info.vl_row);
 620                         lcd_enabled = 0;
 621                         return;
 622                 }
 623         }
 624         if (p->name != NULL)
 625                 debug("Trying compiled-in video modes\n");
 626         while (p->name != NULL) {
 627                 if (strcmp(p->name, vm) == 0) {
 628                         debug("Using video mode: '%s'\n", p->name);
 629                         vm += strlen(vm);
 630                         break;
 631                 }
 632                 p++;
 633         }
 634         if (*vm != '\0')
 635                 debug("Trying to decode video_mode: '%s'\n", vm);
 636         while (*vm != '\0') {
 637                 if (*vm >= '0' && *vm <= '9') {
 638                         char *end;
 639
 640                         val = simple_strtoul(vm, &end, 0);
 641                         if (end > vm) {
 642                                 if (!xres_set) {
 643                                         if (val > panel_info.vl_col)
 644                                                 val = panel_info.vl_col;
 645                                         p->xres = val;
 646                                         panel_info.vl_col = val;
 647                                         xres_set = 1;
 648                                 } else if (!yres_set) {
 649                                         if (val > panel_info.vl_row)
 650                                                 val = panel_info.vl_row;
 651                                         p->yres = val;
 652                                         panel_info.vl_row = val;
 653                                         yres_set = 1;
 654                                 } else if (!bpp_set) {
 655                                         switch (val) {
 656                                         case 8:
 657                                         case 16:
 658                                         case 18:
 659                                         case 24:
 660                                                 color_depth = val;
 661                                                 break;
 662
 663                                         default:
 664                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 665                                                         end - vm, vm, color_depth);
 666                                         }
 667                                         bpp_set = 1;
 668                                 } else if (!refresh_set) {
 669                                         refresh = val;
 670                                         refresh_set = 1;
 671                                 }
 672                         }
 673                         vm = end;
 674                 }
 675                 switch (*vm) {
 676                 case '@':
 677                         bpp_set = 1;
 678                         /* fallthru */
 679                 case '-':
 680                         yres_set = 1;
 681                         /* fallthru */
 682                 case 'x':
 683                         xres_set = 1;
 684                         /* fallthru */
 685                 case 'M':
 686                 case 'R':
 687                         vm++;
 688                         break;
 689
 690                 default:
 691                         if (*vm != '\0')
 692                                 vm++;
 693                 }
 694         }
 695         if (p->xres == 0 || p->yres == 0) {
 696                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 697                 lcd_enabled = 0;
 698                 printf("Supported video modes are:");
 699                 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
 700                         printf(" %s", p->name);
 701                 }
 702                 printf("\n");
 703                 return;
 704         }
 705         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 706                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 707                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 708                 lcd_enabled = 0;
 709                 return;
 710         }
 711         panel_info.vl_col = p->xres;
 712         panel_info.vl_row = p->yres;
 713
 714         switch (color_depth) {
 715         case 8:
 716                 panel_info.vl_bpix = LCD_COLOR8;
 717                 break;
 718         case 16:
 719                 panel_info.vl_bpix = LCD_COLOR16;
 720                 break;
 721         default:
 722                 panel_info.vl_bpix = LCD_COLOR24;
 723         }
 724
 725         p->pixclock = KHZ2PICOS(refresh *
 726                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 727                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 728                                 1000);
 729         debug("Pixel clock set to %lu.%03lu MHz\n",
 730                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 731
 732         if (p != &fb_mode) {
 733                 int ret;
 734
 735                 debug("Creating new display-timing node from '%s'\n",
 736                         video_mode);
 737                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
 738                 if (ret)
 739                         printf("Failed to create new display-timing node from '%s': %d\n",
 740                                 video_mode, ret);
 741         }
 742
 743         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 744         mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
 745                                 ARRAY_SIZE(stk5_lcd_pads));
 746
 747         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
 748                 color_depth, refresh);
 749
 750         if (karo_load_splashimage(0) == 0) {
 751                 char vmode[128];
 752
 753                 /* setup env variable for mxsfb display driver */
 754                 snprintf(vmode, sizeof(vmode),
 755                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
 756                         p->xres, p->yres, p->left_margin, p->right_margin,
 757                         p->upper_margin, p->lower_margin, p->hsync_len,
 758                         p->vsync_len, p->sync, p->pixclock, color_depth);
 759                 setenv("videomode", vmode);
 760
 761                 debug("Initializing LCD controller\n");
 762                 video_hw_init(lcdbase);
 763                 setenv("videomode", NULL);
 764         } else {
 765                 debug("Skipping initialization of LCD controller\n");
 766         }
 767 }
 768 #else
 769 #define lcd_enabled 0
 770 #endif /* CONFIG_LCD */
 771
 772 static void stk5_board_init(void)
 773 {
 774         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 775         mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 776 }
 777
 778 static void stk5v3_board_init(void)
 779 {
 780         stk5_board_init();
 781 }
 782
 783 static void stk5v5_board_init(void)
 784 {
 785         stk5_board_init();
 786
 787         /* init flexcan transceiver enable GPIO */
 788         gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH,
 789                         "Flexcan Transceiver");
 790         mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0);
 791 }
 792
 793 int tx28_fec1_enabled(void)
 794 {
 795         const char *status;
 796         int off;
 797
 798         if (!gd->fdt_blob)
 799                 return 0;
 800
 801         off = fdt_path_offset(gd->fdt_blob, "ethernet1");
 802         if (off < 0)
 803                 return 0;
 804
 805         status = fdt_getprop(gd->fdt_blob, off, "status", NULL);
 806         return status && (strcmp(status, "okay") == 0);
 807 }
 808
 809 static void tx28_init_mac(void)
 810 {
 811         int ret;
 812
 813         ret = fec_get_mac_addr(0);
 814         if (ret < 0) {
 815                 printf("Failed to read FEC0 MAC address from OCOTP\n");
 816                 return;
 817         }
 818 #ifdef CONFIG_FEC_MXC_MULTI
 819         if (tx28_fec1_enabled()) {
 820                 ret = fec_get_mac_addr(1);
 821                 if (ret < 0) {
 822                         printf("Failed to read FEC1 MAC address from OCOTP\n");
 823                         return;
 824                 }
 825         }
 826 #endif
 827 }
 828
 829 int board_late_init(void)
 830 {
 831         int ret = 0;
 832         const char *baseboard;
 833
 834         karo_fdt_move_fdt();
 835
 836         baseboard = getenv("baseboard");
 837         if (!baseboard)
 838                 goto exit;
 839
 840         printf("Baseboard: %s\n", baseboard);
 841
 842         if (strncmp(baseboard, "stk5", 4) == 0) {
 843                 if ((strlen(baseboard) == 4) ||
 844                         strcmp(baseboard, "stk5-v3") == 0) {
 845                         stk5v3_board_init();
 846                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 847                         const char *otg_mode = getenv("otg_mode");
 848
 849                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
 850                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
 851                                         otg_mode, baseboard);
 852                                 setenv("otg_mode", "none");
 853                         }
 854                         stk5v5_board_init();
 855                 } else {
 856                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 857                                 baseboard + 4);
 858                 }
 859         } else {
 860                 printf("WARNING: Unsupported baseboard: '%s'\n",
 861                         baseboard);
 862                 ret = -EINVAL;
 863         }
 864
 865 exit:
 866         tx28_init_mac();
 867         clear_ctrlc();
 868         return ret;
 869 }
 870
 871 #define BOOT_CAUSE_MASK         (RTC_PERSISTENT0_EXTERNAL_RESET |       \
 872                                 RTC_PERSISTENT0_ALARM_WAKE |            \
 873                                 RTC_PERSISTENT0_THERMAL_RESET)
 874
 875 static void thermal_init(void)
 876 {
 877         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 878         struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
 879
 880         writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
 881                 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
 882                 &power_regs->hw_power_thermal);
 883
 884         writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
 885                 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
 886                 &clkctrl_regs->hw_clkctrl_reset);
 887 }
 888
 889 int checkboard(void)
 890 {
 891         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 892         u32 pwr_sts = readl(&power_regs->hw_power_sts);
 893         u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
 894         const char *dlm = "";
 895
 896         printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
 897                 CONFIG_SDRAM_SIZE / SZ_128M +
 898                 CONFIG_SYS_NAND_BLOCKS / 2048 * 2);
 899
 900         printf("POWERUP Source: ");
 901         if (pwrup_src & (3 << 0)) {
 902                 printf("%sPSWITCH %s voltage", dlm,
 903                         pwrup_src & (1 << 1) ? "HIGH" : "MID");
 904                 dlm = " | ";
 905         }
 906         if (pwrup_src & (1 << 4)) {
 907                 printf("%sRTC", dlm);
 908                 dlm = " | ";
 909         }
 910         if (pwrup_src & (1 << 5)) {
 911                 printf("%s5V", dlm);
 912                 dlm = " | ";
 913         }
 914         printf("\n");
 915
 916         if (boot_cause & BOOT_CAUSE_MASK) {
 917                 dlm="";
 918                 printf("Last boot cause: ");
 919                 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
 920                         printf("%sEXTERNAL", dlm);
 921                         dlm = " | ";
 922                 }
 923                 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
 924                         printf("%sTHERMAL", dlm);
 925                         dlm = " | ";
 926                 }
 927                 if (*dlm != '\0')
 928                         printf(" RESET");
 929                 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
 930                         printf("%sALARM WAKE", dlm);
 931                         dlm = " | ";
 932                 }
 933                 printf("\n");
 934         }
 935
 936         while (pwr_sts & POWER_STS_THERMAL_WARNING) {
 937                 static int first = 1;
 938
 939                 if (first) {
 940                         printf("CPU too hot to boot\n");
 941                         first = 0;
 942                 }
 943                 if (tstc())
 944                         break;
 945                 pwr_sts = readl(&power_regs->hw_power_sts);
 946         }
 947
 948         if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
 949                 thermal_init();
 950
 951         return 0;
 952 }
 953
 954 #if defined(CONFIG_OF_BOARD_SETUP)
 955 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 956 #include <jffs2/jffs2.h>
 957 #include <mtd_node.h>
 958 static struct node_info tx28_nand_nodes[] = {
 959         { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
 960 };
 961 #else
 962 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 963 #endif
 964
 965 static const char *tx28_touchpanels[] = {
 966         "ti,tsc2007",
 967         "edt,edt-ft5x06",
 968         "fsl,imx28-lradc",
 969 };
 970
 971 void ft_board_setup(void *blob, bd_t *bd)
 972 {
 973         const char *baseboard = getenv("baseboard");
 974         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
 975         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 976         int ret;
 977
 978         ret = fdt_increase_size(blob, 4096);
 979         if (ret)
 980                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
 981
 982 #ifdef CONFIG_TX28_S
 983         /* TX28-41xx (aka TX28S) has no external RTC
 984          * and no I2C GPIO extender
 985          */
 986         karo_fdt_remove_node(blob, "ds1339");
 987         karo_fdt_remove_node(blob, "gpio5");
 988 #endif
 989         if (stk5_v5)
 990                 karo_fdt_enable_node(blob, "stk5led", 0);
 991
 992         fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
 993         fdt_fixup_ethernet(blob);
 994
 995         karo_fdt_fixup_touchpanel(blob, tx28_touchpanels,
 996                                 ARRAY_SIZE(tx28_touchpanels));
 997         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
 998         karo_fdt_fixup_flexcan(blob, stk5_v5);
 999         karo_fdt_update_fb_mode(blob, video_mode);
1000 }
1001 #endif /* CONFIG_OF_BOARD_SETUP */