board/karo/tx28/tx28.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <lcd.h>
  24 #include <netdev.h>
  25 #include <mmc.h>
  26 #include <mxcfb.h>
  27 #include <linux/list.h>
  28 #include <linux/fb.h>
  29 #include <asm/io.h>
  30 #include <asm/gpio.h>
  31 #include <asm/arch/iomux-mx28.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/imx-regs.h>
  34 #include <asm/arch/sys_proto.h>
  35
  36 #include "../common/karo.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define MXS_GPIO_NR(p, o)      (((p) << 5) | (o))
  41
  42 #define TX28_LCD_PWR_GPIO       MX28_PAD_LCD_ENABLE__GPIO_1_31
  43 #define TX28_LCD_RST_GPIO       MX28_PAD_LCD_RESET__GPIO_3_30
  44 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
  45
  46 #define TX28_USBH_VBUSEN_GPIO   MX28_PAD_SPDIF__GPIO_3_27
  47 #define TX28_USBH_OC_GPIO       MX28_PAD_JTAG_RTCK__GPIO_4_20
  48 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
  49 #define TX28_USBOTG_OC_GPIO     MX28_PAD_GPMI_CE3N__GPIO_0_19
  50 #define TX28_USBOTG_ID_GPIO     MX28_PAD_PWM2__GPIO_3_18
  51
  52 #define TX28_LED_GPIO           MX28_PAD_ENET0_RXD3__GPIO_4_10
  53
  54 #define STK5_CAN_XCVR_GPIO      MX28_PAD_LCD_D00__GPIO_1_0
  55
  56 static const struct gpio tx28_gpios[] = {
  57         { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
  58         { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
  59         { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
  60         { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
  61         { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
  62 };
  63
  64 static const iomux_cfg_t tx28_pads[] = {
  65         /* UART pads */
  66 #if CONFIG_CONS_INDEX == 0
  67         MX28_PAD_AUART0_RX__DUART_CTS,
  68         MX28_PAD_AUART0_TX__DUART_RTS,
  69         MX28_PAD_AUART0_CTS__DUART_RX,
  70         MX28_PAD_AUART0_RTS__DUART_TX,
  71 #elif CONFIG_CONS_INDEX == 1
  72         MX28_PAD_AUART1_RX__AUART1_RX,
  73         MX28_PAD_AUART1_TX__AUART1_TX,
  74         MX28_PAD_AUART1_CTS__AUART1_CTS,
  75         MX28_PAD_AUART1_RTS__AUART1_RTS,
  76 #elif CONFIG_CONS_INDEX == 2
  77         MX28_PAD_AUART3_RX__AUART3_RX,
  78         MX28_PAD_AUART3_TX__AUART3_TX,
  79         MX28_PAD_AUART3_CTS__AUART3_CTS,
  80         MX28_PAD_AUART3_RTS__AUART3_RTS,
  81 #endif
  82         /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
  83         MX28_PAD_I2C0_SCL__I2C0_SCL,
  84         MX28_PAD_I2C0_SDA__I2C0_SDA,
  85
  86         /* USBH VBUSEN, OC */
  87         MX28_PAD_SPDIF__GPIO_3_27,
  88         MX28_PAD_JTAG_RTCK__GPIO_4_20,
  89
  90         /* USBOTG VBUSEN, OC, ID */
  91         MX28_PAD_GPMI_CE2N__GPIO_0_18,
  92         MX28_PAD_GPMI_CE3N__GPIO_0_19,
  93         MX28_PAD_PWM2__GPIO_3_18,
  94 };
  95
  96 /*
  97  * Functions
  98  */
  99
 100 /* provide at least _some_ sort of randomness */
 101 #define MAX_LOOPS       100
 102
 103 static u32 random;
 104
 105 static inline void random_init(void)
 106 {
 107         struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
 108         u32 seed = 0;
 109         int i;
 110
 111         for (i = 0; i < MAX_LOOPS; i++) {
 112                 u32 hclk = readl(&digctl_regs->hw_digctl_hclkcount);
 113                 u32 entropy = readl(&digctl_regs->hw_digctl_entropy);
 114                 u32 usec = readl(&digctl_regs->hw_digctl_microseconds);
 115
 116                 seed = get_timer(hclk ^ entropy ^ usec ^ random ^ seed);
 117                 srand(seed);
 118                 random = rand();
 119         }
 120 }
 121
 122 #define RTC_PERSISTENT0_CLK32_MASK      (RTC_PERSISTENT0_CLOCKSOURCE |  \
 123                                         RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
 124 static u32 boot_cause __attribute__((section("data")));
 125
 126 int board_early_init_f(void)
 127 {
 128         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 129         u32 rtc_stat;
 130         int timeout = 5000;
 131
 132         random_init();
 133
 134         /* IO0 clock at 480MHz */
 135         mxs_set_ioclk(MXC_IOCLK0, 480000);
 136         /* IO1 clock at 480MHz */
 137         mxs_set_ioclk(MXC_IOCLK1, 480000);
 138
 139         /* SSP0 clock at 96MHz */
 140         mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 141         /* SSP2 clock at 96MHz */
 142         mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
 143
 144         gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
 145         mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
 146
 147         while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
 148                 RTC_STAT_STALE_REGS_PERSISTENT0) {
 149                 if (timeout-- < 0)
 150                         return 0;
 151                 udelay(1);
 152         }
 153         boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
 154         if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
 155                 RTC_PERSISTENT0_CLK32_MASK) {
 156                 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
 157                         goto rtc_err;
 158                 writel(RTC_PERSISTENT0_CLK32_MASK,
 159                         &rtc_regs->hw_rtc_persistent0_set);
 160         }
 161         return 0;
 162
 163 rtc_err:
 164         serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
 165         return 0;
 166 }
 167
 168 int board_init(void)
 169 {
 170         /* Address of boot parameters */
 171 #ifdef CONFIG_OF_LIBFDT
 172         gd->bd->bi_arch_number = -1;
 173 #endif
 174         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 175         return 0;
 176 }
 177
 178 int dram_init(void)
 179 {
 180         return mxs_dram_init();
 181 }
 182
 183 #ifdef  CONFIG_CMD_MMC
 184 static int tx28_mmc_wp(int dev_no)
 185 {
 186         return 0;
 187 }
 188
 189 int board_mmc_init(bd_t *bis)
 190 {
 191         return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
 192 }
 193 #endif /* CONFIG_CMD_MMC */
 194
 195 #ifdef CONFIG_FEC_MXC
 196 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
 197
 198 #ifdef CONFIG_FEC_MXC_MULTI
 199 #define FEC_MAX_IDX                     1
 200 #else
 201 #define FEC_MAX_IDX                     0
 202 #endif
 203 #ifndef ETH_ALEN
 204 #define ETH_ALEN                        6
 205 #endif
 206
 207 static int fec_get_mac_addr(int index)
 208 {
 209         int timeout = 1000;
 210         struct mxs_ocotp_regs *ocotp_regs =
 211                 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
 212         u32 *cust = &ocotp_regs->hw_ocotp_cust0;
 213         u8 mac[ETH_ALEN];
 214         char env_name[] = "eth.addr";
 215         u32 val = 0;
 216         int i;
 217
 218         if (index < 0 || index > FEC_MAX_IDX)
 219                 return -EINVAL;
 220
 221         /* set this bit to open the OTP banks for reading */
 222         writel(OCOTP_CTRL_RD_BANK_OPEN,
 223                 &ocotp_regs->hw_ocotp_ctrl_set);
 224
 225         /* wait until OTP contents are readable */
 226         while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
 227                 if (timeout-- < 0)
 228                         return -ETIMEDOUT;
 229                 udelay(100);
 230         }
 231
 232         for (i = 0; i < sizeof(mac); i++) {
 233                 int shift = 24 - i % 4 * 8;
 234
 235                 if (i % 4 == 0)
 236                         val = readl(&cust[index * 8 + i]);
 237                 mac[i] = val >> shift;
 238         }
 239         if (!is_valid_ether_addr(mac)) {
 240                 if (index == 0)
 241                         printf("No valid MAC address programmed\n");
 242                 return 0;
 243         }
 244
 245         if (index == 0) {
 246                 printf("MAC addr from fuse: %pM\n", mac);
 247                 snprintf(env_name, sizeof(env_name), "ethaddr");
 248         } else {
 249                 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
 250         }
 251         eth_setenv_enetaddr(env_name, mac);
 252         return 0;
 253 }
 254 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
 255
 256 static const iomux_cfg_t tx28_fec_pads[] = {
 257         MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
 258         MX28_PAD_ENET0_RXD0__ENET0_RXD0,
 259         MX28_PAD_ENET0_RXD1__ENET0_RXD1,
 260 };
 261
 262 int board_eth_init(bd_t *bis)
 263 {
 264         int ret;
 265
 266         /* Reset the external phy */
 267         gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
 268
 269         /* Power on the external phy */
 270         gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
 271
 272         /* Pull strap pins to high */
 273         gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
 274         gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
 275         gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
 276         gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
 277
 278         udelay(25000);
 279         gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
 280         udelay(100);
 281
 282         mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
 283
 284         ret = cpu_eth_init(bis);
 285         if (ret) {
 286                 printf("cpu_eth_init() failed: %d\n", ret);
 287                 return ret;
 288         }
 289
 290 #ifdef CONFIG_FEC_MXC_MULTI
 291         if (getenv("ethaddr")) {
 292                 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
 293                 if (ret) {
 294                         printf("FEC MXS: Unable to init FEC0\n");
 295                         return ret;
 296                 }
 297         }
 298
 299         if (getenv("eth1addr")) {
 300                 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
 301                 if (ret) {
 302                         printf("FEC MXS: Unable to init FEC1\n");
 303                         return ret;
 304                 }
 305         }
 306 #else
 307         if (getenv("ethaddr")) {
 308                 ret = fecmxc_initialize(bis);
 309                 if (ret) {
 310                         printf("FEC MXS: Unable to init FEC\n");
 311                         return ret;
 312                 }
 313         }
 314 #endif
 315         return 0;
 316 }
 317 #endif /* CONFIG_FEC_MXC */
 318
 319 enum {
 320         LED_STATE_INIT = -1,
 321         LED_STATE_OFF,
 322         LED_STATE_ON,
 323 };
 324
 325 void show_activity(int arg)
 326 {
 327         static int led_state = LED_STATE_INIT;
 328         static ulong last;
 329
 330         if (led_state == LED_STATE_INIT) {
 331                 last = get_timer(0);
 332                 gpio_set_value(TX28_LED_GPIO, 1);
 333                 led_state = LED_STATE_ON;
 334         } else {
 335                 if (get_timer(last) > CONFIG_SYS_HZ) {
 336                         last = get_timer(0);
 337                         if (led_state == LED_STATE_ON) {
 338                                 gpio_set_value(TX28_LED_GPIO, 0);
 339                         } else {
 340                                 gpio_set_value(TX28_LED_GPIO, 1);
 341                         }
 342                         led_state = 1 - led_state;
 343                 }
 344         }
 345 }
 346
 347 static const iomux_cfg_t stk5_pads[] = {
 348         /* SW controlled LED on STK5 baseboard */
 349         MX28_PAD_ENET0_RXD3__GPIO_4_10,
 350 };
 351
 352 static const struct gpio stk5_gpios[] = {
 353 };
 354
 355 #ifdef CONFIG_LCD
 356 static ushort tx28_cmap[256];
 357 vidinfo_t panel_info = {
 358         /* set to max. size supported by SoC */
 359         .vl_col = 1600,
 360         .vl_row = 1200,
 361
 362         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 363         .cmap = tx28_cmap,
 364 };
 365
 366 static struct fb_videomode tx28_fb_modes[] = {
 367         {
 368                 /* Standard VGA timing */
 369                 .name           = "VGA",
 370                 .refresh        = 60,
 371                 .xres           = 640,
 372                 .yres           = 480,
 373                 .pixclock       = KHZ2PICOS(25175),
 374                 .left_margin    = 48,
 375                 .hsync_len      = 96,
 376                 .right_margin   = 16,
 377                 .upper_margin   = 31,
 378                 .vsync_len      = 2,
 379                 .lower_margin   = 12,
 380                 .vmode          = FB_VMODE_NONINTERLACED,
 381         },
 382         {
 383                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 384                  * DE high active, 115.2 mm x 86.4 mm display area
 385                  * VGA compatible timing
 386                  */
 387                 .name           = "ETV570",
 388                 .refresh        = 60,
 389                 .xres           = 640,
 390                 .yres           = 480,
 391                 .pixclock       = KHZ2PICOS(25175),
 392                 .left_margin    = 114,
 393                 .hsync_len      = 30,
 394                 .right_margin   = 16,
 395                 .upper_margin   = 32,
 396                 .vsync_len      = 3,
 397                 .lower_margin   = 10,
 398                 .vmode          = FB_VMODE_NONINTERLACED,
 399         },
 400         {
 401                 /* Emerging ET0350G0DH6 320 x 240 display.
 402                  * 70.08 mm x 52.56 mm display area.
 403                  */
 404                 .name           = "ET0350",
 405                 .refresh        = 60,
 406                 .xres           = 320,
 407                 .yres           = 240,
 408                 .pixclock       = KHZ2PICOS(6500),
 409                 .left_margin    = 68 - 34,
 410                 .hsync_len      = 34,
 411                 .right_margin   = 20,
 412                 .upper_margin   = 18 - 3,
 413                 .vsync_len      = 3,
 414                 .lower_margin   = 4,
 415                 .vmode          = FB_VMODE_NONINTERLACED,
 416         },
 417         {
 418                 /* Emerging ET0430G0DH6 480 x 272 display.
 419                  * 95.04 mm x 53.856 mm display area.
 420                  */
 421                 .name           = "ET0430",
 422                 .refresh        = 60,
 423                 .xres           = 480,
 424                 .yres           = 272,
 425                 .pixclock       = KHZ2PICOS(9000),
 426                 .left_margin    = 2,
 427                 .hsync_len      = 41,
 428                 .right_margin   = 2,
 429                 .upper_margin   = 2,
 430                 .vsync_len      = 10,
 431                 .lower_margin   = 2,
 432                 .sync           = FB_SYNC_CLK_LAT_FALL,
 433                 .vmode          = FB_VMODE_NONINTERLACED,
 434         },
 435         {
 436                 /* Emerging ET0500G0DH6 800 x 480 display.
 437                  * 109.6 mm x 66.4 mm display area.
 438                  */
 439                 .name           = "ET0500",
 440                 .refresh        = 60,
 441                 .xres           = 800,
 442                 .yres           = 480,
 443                 .pixclock       = KHZ2PICOS(33260),
 444                 .left_margin    = 216 - 128,
 445                 .hsync_len      = 128,
 446                 .right_margin   = 1056 - 800 - 216,
 447                 .upper_margin   = 35 - 2,
 448                 .vsync_len      = 2,
 449                 .lower_margin   = 525 - 480 - 35,
 450                 .vmode          = FB_VMODE_NONINTERLACED,
 451         },
 452         {
 453                 /* Emerging ETQ570G0DH6 320 x 240 display.
 454                  * 115.2 mm x 86.4 mm display area.
 455                  */
 456                 .name           = "ETQ570",
 457                 .refresh        = 60,
 458                 .xres           = 320,
 459                 .yres           = 240,
 460                 .pixclock       = KHZ2PICOS(6400),
 461                 .left_margin    = 38,
 462                 .hsync_len      = 30,
 463                 .right_margin   = 30,
 464                 .upper_margin   = 16, /* 15 according to datasheet */
 465                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 466                 .lower_margin   = 4, /* 4.5 according to datasheet */
 467                 .vmode          = FB_VMODE_NONINTERLACED,
 468         },
 469         {
 470                 /* Emerging ET0700G0DH6 800 x 480 display.
 471                  * 152.4 mm x 91.44 mm display area.
 472                  */
 473                 .name           = "ET0700",
 474                 .refresh        = 60,
 475                 .xres           = 800,
 476                 .yres           = 480,
 477                 .pixclock       = KHZ2PICOS(33260),
 478                 .left_margin    = 216 - 128,
 479                 .hsync_len      = 128,
 480                 .right_margin   = 1056 - 800 - 216,
 481                 .upper_margin   = 35 - 2,
 482                 .vsync_len      = 2,
 483                 .lower_margin   = 525 - 480 - 35,
 484                 .vmode          = FB_VMODE_NONINTERLACED,
 485         },
 486         {
 487                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 488                 .vmode          = FB_VMODE_NONINTERLACED,
 489         },
 490 };
 491
 492 static int lcd_enabled = 1;
 493 static int lcd_bl_polarity;
 494
 495 static int lcd_backlight_polarity(void)
 496 {
 497         return lcd_bl_polarity;
 498 }
 499
 500 void lcd_enable(void)
 501 {
 502         /* HACK ALERT:
 503          * global variable from common/lcd.c
 504          * Set to 0 here to prevent messages from going to LCD
 505          * rather than serial console
 506          */
 507         lcd_is_enabled = 0;
 508
 509         karo_load_splashimage(1);
 510         if (lcd_enabled) {
 511                 debug("Switching LCD on\n");
 512                 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
 513                 udelay(100);
 514                 gpio_set_value(TX28_LCD_RST_GPIO, 1);
 515                 udelay(300000);
 516                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
 517                         lcd_backlight_polarity());
 518         }
 519 }
 520
 521 void lcd_disable(void)
 522 {
 523 }
 524
 525 void lcd_panel_disable(void)
 526 {
 527         if (lcd_enabled) {
 528                 debug("Switching LCD off\n");
 529                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
 530                         !lcd_backlight_polarity());
 531                 gpio_set_value(TX28_LCD_RST_GPIO, 0);
 532                 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
 533         }
 534 }
 535
 536 static const iomux_cfg_t stk5_lcd_pads[] = {
 537         /* LCD RESET */
 538         MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
 539         /* LCD POWER_ENABLE */
 540         MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
 541         /* LCD Backlight (PWM) */
 542         MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
 543
 544         /* Display */
 545         MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
 546         MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
 547         MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
 548         MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
 549         MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
 550         MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
 551         MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
 552         MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
 553         MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
 554         MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
 555         MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
 556         MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
 557         MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
 558         MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
 559         MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
 560         MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
 561         MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
 562         MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
 563         MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
 564         MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
 565         MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
 566         MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
 567         MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
 568         MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
 569         MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
 570         MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
 571         MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
 572         MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
 573 };
 574
 575 static const struct gpio stk5_lcd_gpios[] = {
 576         { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 577         { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 578         { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 579 };
 580
 581 extern void video_hw_init(void *lcdbase);
 582
 583 void lcd_ctrl_init(void *lcdbase)
 584 {
 585         int color_depth = 24;
 586         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 587         const char *vm;
 588         unsigned long val;
 589         int refresh = 60;
 590         struct fb_videomode *p = tx28_fb_modes;
 591         struct fb_videomode fb_mode;
 592         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 593
 594         if (!lcd_enabled) {
 595                 debug("LCD disabled\n");
 596                 return;
 597         }
 598
 599         if (had_ctrlc()) {
 600                 debug("Disabling LCD\n");
 601                 lcd_enabled = 0;
 602                 setenv("splashimage", NULL);
 603                 return;
 604         }
 605
 606         karo_fdt_move_fdt();
 607         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 608
 609         if (video_mode == NULL) {
 610                 debug("Disabling LCD\n");
 611                 lcd_enabled = 0;
 612                 return;
 613         }
 614         vm = video_mode;
 615         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 616                 p = &fb_mode;
 617                 debug("Using video mode from FDT\n");
 618                 vm += strlen(vm);
 619                 if (fb_mode.xres > panel_info.vl_col ||
 620                         fb_mode.yres > panel_info.vl_row) {
 621                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 622                                 fb_mode.xres, fb_mode.yres,
 623                                 panel_info.vl_col, panel_info.vl_row);
 624                         lcd_enabled = 0;
 625                         return;
 626                 }
 627         }
 628         if (p->name != NULL)
 629                 debug("Trying compiled-in video modes\n");
 630         while (p->name != NULL) {
 631                 if (strcmp(p->name, vm) == 0) {
 632                         debug("Using video mode: '%s'\n", p->name);
 633                         vm += strlen(vm);
 634                         break;
 635                 }
 636                 p++;
 637         }
 638         if (*vm != '\0')
 639                 debug("Trying to decode video_mode: '%s'\n", vm);
 640         while (*vm != '\0') {
 641                 if (*vm >= '0' && *vm <= '9') {
 642                         char *end;
 643
 644                         val = simple_strtoul(vm, &end, 0);
 645                         if (end > vm) {
 646                                 if (!xres_set) {
 647                                         if (val > panel_info.vl_col)
 648                                                 val = panel_info.vl_col;
 649                                         p->xres = val;
 650                                         panel_info.vl_col = val;
 651                                         xres_set = 1;
 652                                 } else if (!yres_set) {
 653                                         if (val > panel_info.vl_row)
 654                                                 val = panel_info.vl_row;
 655                                         p->yres = val;
 656                                         panel_info.vl_row = val;
 657                                         yres_set = 1;
 658                                 } else if (!bpp_set) {
 659                                         switch (val) {
 660                                         case 8:
 661                                         case 16:
 662                                         case 18:
 663                                         case 24:
 664                                                 color_depth = val;
 665                                                 break;
 666
 667                                         default:
 668                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 669                                                         end - vm, vm, color_depth);
 670                                         }
 671                                         bpp_set = 1;
 672                                 } else if (!refresh_set) {
 673                                         refresh = val;
 674                                         refresh_set = 1;
 675                                 }
 676                         }
 677                         vm = end;
 678                 }
 679                 switch (*vm) {
 680                 case '@':
 681                         bpp_set = 1;
 682                         /* fallthru */
 683                 case '-':
 684                         yres_set = 1;
 685                         /* fallthru */
 686                 case 'x':
 687                         xres_set = 1;
 688                         /* fallthru */
 689                 case 'M':
 690                 case 'R':
 691                         vm++;
 692                         break;
 693
 694                 default:
 695                         if (*vm != '\0')
 696                                 vm++;
 697                 }
 698         }
 699         if (p->xres == 0 || p->yres == 0) {
 700                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 701                 lcd_enabled = 0;
 702                 printf("Supported video modes are:");
 703                 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
 704                         printf(" %s", p->name);
 705                 }
 706                 printf("\n");
 707                 return;
 708         }
 709         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 710                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 711                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 712                 lcd_enabled = 0;
 713                 return;
 714         }
 715         panel_info.vl_col = p->xres;
 716         panel_info.vl_row = p->yres;
 717
 718         switch (color_depth) {
 719         case 8:
 720                 panel_info.vl_bpix = LCD_COLOR8;
 721                 break;
 722         case 16:
 723                 panel_info.vl_bpix = LCD_COLOR16;
 724                 break;
 725         default:
 726                 panel_info.vl_bpix = LCD_COLOR24;
 727         }
 728
 729         p->pixclock = KHZ2PICOS(refresh *
 730                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 731                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 732                                 1000);
 733         debug("Pixel clock set to %lu.%03lu MHz\n",
 734                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 735
 736         if (p != &fb_mode) {
 737                 int ret;
 738
 739                 debug("Creating new display-timing node from '%s'\n",
 740                         video_mode);
 741                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
 742                 if (ret)
 743                         printf("Failed to create new display-timing node from '%s': %d\n",
 744                                 video_mode, ret);
 745         }
 746
 747         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 748         mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
 749                                 ARRAY_SIZE(stk5_lcd_pads));
 750
 751         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
 752                 color_depth, refresh);
 753
 754         if (karo_load_splashimage(0) == 0) {
 755                 char vmode[128];
 756
 757                 /* setup env variable for mxsfb display driver */
 758                 snprintf(vmode, sizeof(vmode),
 759                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
 760                         p->xres, p->yres, p->left_margin, p->right_margin,
 761                         p->upper_margin, p->lower_margin, p->hsync_len,
 762                         p->vsync_len, p->sync, p->pixclock, color_depth);
 763                 setenv("videomode", vmode);
 764
 765                 debug("Initializing LCD controller\n");
 766                 video_hw_init(lcdbase);
 767                 setenv("videomode", NULL);
 768         } else {
 769                 debug("Skipping initialization of LCD controller\n");
 770         }
 771 }
 772 #else
 773 #define lcd_enabled 0
 774 #endif /* CONFIG_LCD */
 775
 776 static void stk5_board_init(void)
 777 {
 778         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 779         mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 780 }
 781
 782 static void stk5v3_board_init(void)
 783 {
 784         stk5_board_init();
 785 }
 786
 787 static void stk5v5_board_init(void)
 788 {
 789         stk5_board_init();
 790
 791         /* init flexcan transceiver enable GPIO */
 792         gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOF_OUTPUT_INIT_HIGH,
 793                         "Flexcan Transceiver");
 794         mxs_iomux_setup_pad(STK5_CAN_XCVR_GPIO);
 795 }
 796
 797 int tx28_fec1_enabled(void)
 798 {
 799         const char *status;
 800         int off;
 801
 802         if (!gd->fdt_blob)
 803                 return 0;
 804
 805         off = fdt_path_offset(gd->fdt_blob, "ethernet1");
 806         if (off < 0)
 807                 return 0;
 808
 809         status = fdt_getprop(gd->fdt_blob, off, "status", NULL);
 810         return status && (strcmp(status, "okay") == 0);
 811 }
 812
 813 static void tx28_init_mac(void)
 814 {
 815         int ret;
 816
 817         ret = fec_get_mac_addr(0);
 818         if (ret < 0) {
 819                 printf("Failed to read FEC0 MAC address from OCOTP\n");
 820                 return;
 821         }
 822 #ifdef CONFIG_FEC_MXC_MULTI
 823         if (tx28_fec1_enabled()) {
 824                 ret = fec_get_mac_addr(1);
 825                 if (ret < 0) {
 826                         printf("Failed to read FEC1 MAC address from OCOTP\n");
 827                         return;
 828                 }
 829         }
 830 #endif
 831 }
 832
 833 int board_late_init(void)
 834 {
 835         int ret = 0;
 836         const char *baseboard;
 837
 838         karo_fdt_move_fdt();
 839
 840         baseboard = getenv("baseboard");
 841         if (!baseboard)
 842                 goto exit;
 843
 844         printf("Baseboard: %s\n", baseboard);
 845
 846         if (strncmp(baseboard, "stk5", 4) == 0) {
 847                 if ((strlen(baseboard) == 4) ||
 848                         strcmp(baseboard, "stk5-v3") == 0) {
 849                         stk5v3_board_init();
 850                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 851                         const char *otg_mode = getenv("otg_mode");
 852
 853                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
 854                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
 855                                         otg_mode, baseboard);
 856                                 setenv("otg_mode", "none");
 857                         }
 858                         stk5v5_board_init();
 859                 } else {
 860                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 861                                 baseboard + 4);
 862                 }
 863         } else {
 864                 printf("WARNING: Unsupported baseboard: '%s'\n",
 865                         baseboard);
 866                 ret = -EINVAL;
 867         }
 868
 869 exit:
 870         tx28_init_mac();
 871         clear_ctrlc();
 872         return ret;
 873 }
 874
 875 #define BOOT_CAUSE_MASK         (RTC_PERSISTENT0_EXTERNAL_RESET |       \
 876                                 RTC_PERSISTENT0_ALARM_WAKE |            \
 877                                 RTC_PERSISTENT0_THERMAL_RESET)
 878
 879 static void thermal_init(void)
 880 {
 881         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 882         struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
 883
 884         writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
 885                 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
 886                 &power_regs->hw_power_thermal);
 887
 888         writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
 889                 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
 890                 &clkctrl_regs->hw_clkctrl_reset);
 891 }
 892
 893 int checkboard(void)
 894 {
 895         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 896         u32 pwr_sts = readl(&power_regs->hw_power_sts);
 897         u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
 898         const char *dlm = "";
 899
 900         printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
 901                 CONFIG_SDRAM_SIZE / SZ_128M +
 902                 CONFIG_SYS_NAND_BLOCKS / 2048 * 2);
 903
 904         printf("POWERUP Source: ");
 905         if (pwrup_src & (3 << 0)) {
 906                 printf("%sPSWITCH %s voltage", dlm,
 907                         pwrup_src & (1 << 1) ? "HIGH" : "MID");
 908                 dlm = " | ";
 909         }
 910         if (pwrup_src & (1 << 4)) {
 911                 printf("%sRTC", dlm);
 912                 dlm = " | ";
 913         }
 914         if (pwrup_src & (1 << 5)) {
 915                 printf("%s5V", dlm);
 916                 dlm = " | ";
 917         }
 918         printf("\n");
 919
 920         if (boot_cause & BOOT_CAUSE_MASK) {
 921                 dlm="";
 922                 printf("Last boot cause: ");
 923                 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
 924                         printf("%sEXTERNAL", dlm);
 925                         dlm = " | ";
 926                 }
 927                 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
 928                         printf("%sTHERMAL", dlm);
 929                         dlm = " | ";
 930                 }
 931                 if (*dlm != '\0')
 932                         printf(" RESET");
 933                 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
 934                         printf("%sALARM WAKE", dlm);
 935                         dlm = " | ";
 936                 }
 937                 printf("\n");
 938         }
 939
 940         while (pwr_sts & POWER_STS_THERMAL_WARNING) {
 941                 static int first = 1;
 942
 943                 if (first) {
 944                         printf("CPU too hot to boot\n");
 945                         first = 0;
 946                 }
 947                 if (tstc())
 948                         break;
 949                 pwr_sts = readl(&power_regs->hw_power_sts);
 950         }
 951
 952         if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
 953                 thermal_init();
 954
 955         return 0;
 956 }
 957
 958 #if defined(CONFIG_OF_BOARD_SETUP)
 959 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 960 #include <jffs2/jffs2.h>
 961 #include <mtd_node.h>
 962 static struct node_info tx28_nand_nodes[] = {
 963         { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
 964 };
 965 #else
 966 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 967 #endif
 968
 969 static const char *tx28_touchpanels[] = {
 970         "ti,tsc2007",
 971         "edt,edt-ft5x06",
 972         "fsl,imx28-lradc",
 973 };
 974
 975 void ft_board_setup(void *blob, bd_t *bd)
 976 {
 977         const char *baseboard = getenv("baseboard");
 978         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
 979         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 980         int ret;
 981
 982         ret = fdt_increase_size(blob, 4096);
 983         if (ret)
 984                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
 985
 986 #ifdef CONFIG_TX28_S
 987         /* TX28-41xx (aka TX28S) has no external RTC
 988          * and no I2C GPIO extender
 989          */
 990         karo_fdt_remove_node(blob, "ds1339");
 991         karo_fdt_remove_node(blob, "gpio5");
 992 #endif
 993         if (stk5_v5)
 994                 karo_fdt_enable_node(blob, "stk5led", 0);
 995
 996         fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
 997         fdt_fixup_ethernet(blob);
 998
 999         karo_fdt_fixup_touchpanel(blob, tx28_touchpanels,
1000                                 ARRAY_SIZE(tx28_touchpanels));
1001         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1002         karo_fdt_fixup_flexcan(blob, stk5_v5);
1003         karo_fdt_update_fb_mode(blob, video_mode);
1004 }
1005 #endif /* CONFIG_OF_BOARD_SETUP */