board/karo/tx28/tx28.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <lcd.h>
  24 #include <netdev.h>
  25 #include <mmc.h>
  26 #include <mxcfb.h>
  27 #include <linux/list.h>
  28 #include <linux/fb.h>
  29 #include <asm/io.h>
  30 #include <asm/gpio.h>
  31 #include <asm/arch/iomux-mx28.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/imx-regs.h>
  34 #include <asm/arch/sys_proto.h>
  35
  36 #include "../common/karo.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define MXS_GPIO_NR(p, o)      (((p) << 5) | (o))
  41
  42 #define TX28_LCD_PWR_GPIO       MX28_PAD_LCD_ENABLE__GPIO_1_31
  43 #define TX28_LCD_RST_GPIO       MX28_PAD_LCD_RESET__GPIO_3_30
  44 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
  45
  46 #define TX28_USBH_VBUSEN_GPIO   MX28_PAD_SPDIF__GPIO_3_27
  47 #define TX28_USBH_OC_GPIO       MX28_PAD_JTAG_RTCK__GPIO_4_20
  48 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
  49 #define TX28_USBOTG_OC_GPIO     MX28_PAD_GPMI_CE3N__GPIO_0_19
  50 #define TX28_USBOTG_ID_GPIO     MX28_PAD_PWM2__GPIO_3_18
  51
  52 #define TX28_LED_GPIO           MX28_PAD_ENET0_RXD3__GPIO_4_10
  53
  54 #define STK5_CAN_XCVR_GPIO      MX28_PAD_LCD_D00__GPIO_1_0
  55
  56 static const struct gpio tx28_gpios[] = {
  57         { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
  58         { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
  59         { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
  60         { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
  61         { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
  62 };
  63
  64 static const iomux_cfg_t tx28_pads[] = {
  65         /* UART pads */
  66 #if CONFIG_CONS_INDEX == 0
  67         MX28_PAD_AUART0_RX__DUART_CTS,
  68         MX28_PAD_AUART0_TX__DUART_RTS,
  69         MX28_PAD_AUART0_CTS__DUART_RX,
  70         MX28_PAD_AUART0_RTS__DUART_TX,
  71 #elif CONFIG_CONS_INDEX == 1
  72         MX28_PAD_AUART1_RX__AUART1_RX,
  73         MX28_PAD_AUART1_TX__AUART1_TX,
  74         MX28_PAD_AUART1_CTS__AUART1_CTS,
  75         MX28_PAD_AUART1_RTS__AUART1_RTS,
  76 #elif CONFIG_CONS_INDEX == 2
  77         MX28_PAD_AUART3_RX__AUART3_RX,
  78         MX28_PAD_AUART3_TX__AUART3_TX,
  79         MX28_PAD_AUART3_CTS__AUART3_CTS,
  80         MX28_PAD_AUART3_RTS__AUART3_RTS,
  81 #endif
  82         /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
  83         MX28_PAD_I2C0_SCL__I2C0_SCL,
  84         MX28_PAD_I2C0_SDA__I2C0_SDA,
  85
  86         /* USBH VBUSEN, OC */
  87         MX28_PAD_SPDIF__GPIO_3_27,
  88         MX28_PAD_JTAG_RTCK__GPIO_4_20,
  89
  90         /* USBOTG VBUSEN, OC, ID */
  91         MX28_PAD_GPMI_CE2N__GPIO_0_18,
  92         MX28_PAD_GPMI_CE3N__GPIO_0_19,
  93         MX28_PAD_PWM2__GPIO_3_18,
  94 };
  95
  96 /*
  97  * Functions
  98  */
  99
 100 /* provide at least _some_ sort of randomness */
 101 #define MAX_LOOPS       100
 102
 103 static u32 random;
 104
 105 static inline void random_init(void)
 106 {
 107         struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
 108         u32 seed = 0;
 109         int i;
 110
 111         for (i = 0; i < MAX_LOOPS; i++) {
 112                 unsigned int usec = readl(&digctl_regs->hw_digctl_microseconds);
 113
 114                 seed = get_timer(usec + random + seed);
 115                 srand(seed);
 116                 random = rand();
 117         }
 118 }
 119
 120 #define RTC_PERSISTENT0_CLK32_MASK      (RTC_PERSISTENT0_CLOCKSOURCE |  \
 121                                         RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
 122 static u32 boot_cause __attribute__((section("data")));
 123
 124 int board_early_init_f(void)
 125 {
 126         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 127         u32 rtc_stat;
 128         int timeout = 5000;
 129
 130         random_init();
 131
 132         /* IO0 clock at 480MHz */
 133         mxs_set_ioclk(MXC_IOCLK0, 480000);
 134         /* IO1 clock at 480MHz */
 135         mxs_set_ioclk(MXC_IOCLK1, 480000);
 136
 137         /* SSP0 clock at 96MHz */
 138         mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 139         /* SSP2 clock at 96MHz */
 140         mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
 141
 142         gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
 143         mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
 144
 145         while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
 146                 RTC_STAT_STALE_REGS_PERSISTENT0) {
 147                 if (timeout-- < 0)
 148                         return 0;
 149                 udelay(1);
 150         }
 151         boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
 152         if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
 153                 RTC_PERSISTENT0_CLK32_MASK) {
 154                 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
 155                         goto rtc_err;
 156                 writel(RTC_PERSISTENT0_CLK32_MASK,
 157                         &rtc_regs->hw_rtc_persistent0_set);
 158         }
 159         return 0;
 160
 161 rtc_err:
 162         serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
 163         return 0;
 164 }
 165
 166 int board_init(void)
 167 {
 168         /* Address of boot parameters */
 169 #ifdef CONFIG_OF_LIBFDT
 170         gd->bd->bi_arch_number = -1;
 171 #endif
 172         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 173         return 0;
 174 }
 175
 176 int dram_init(void)
 177 {
 178         return mxs_dram_init();
 179 }
 180
 181 #ifdef  CONFIG_CMD_MMC
 182 static int tx28_mmc_wp(int dev_no)
 183 {
 184         return 0;
 185 }
 186
 187 int board_mmc_init(bd_t *bis)
 188 {
 189         return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
 190 }
 191 #endif /* CONFIG_CMD_MMC */
 192
 193 #ifdef CONFIG_FEC_MXC
 194 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
 195
 196 #ifdef CONFIG_FEC_MXC_MULTI
 197 #define FEC_MAX_IDX                     1
 198 #else
 199 #define FEC_MAX_IDX                     0
 200 #endif
 201 #ifndef ETH_ALEN
 202 #define ETH_ALEN                        6
 203 #endif
 204
 205 static int fec_get_mac_addr(int index)
 206 {
 207         int timeout = 1000;
 208         struct mxs_ocotp_regs *ocotp_regs =
 209                 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
 210         u32 *cust = &ocotp_regs->hw_ocotp_cust0;
 211         u8 mac[ETH_ALEN];
 212         char env_name[] = "eth.addr";
 213         u32 val = 0;
 214         int i;
 215
 216         if (index < 0 || index > FEC_MAX_IDX)
 217                 return -EINVAL;
 218
 219         /* set this bit to open the OTP banks for reading */
 220         writel(OCOTP_CTRL_RD_BANK_OPEN,
 221                 &ocotp_regs->hw_ocotp_ctrl_set);
 222
 223         /* wait until OTP contents are readable */
 224         while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
 225                 if (timeout-- < 0)
 226                         return -ETIMEDOUT;
 227                 udelay(100);
 228         }
 229
 230         for (i = 0; i < sizeof(mac); i++) {
 231                 int shift = 24 - i % 4 * 8;
 232
 233                 if (i % 4 == 0)
 234                         val = readl(&cust[index * 8 + i]);
 235                 mac[i] = val >> shift;
 236         }
 237         if (!is_valid_ether_addr(mac)) {
 238                 if (index == 0)
 239                         printf("No valid MAC address programmed\n");
 240                 return 0;
 241         }
 242
 243         if (index == 0) {
 244                 printf("MAC addr from fuse: %pM\n", mac);
 245                 snprintf(env_name, sizeof(env_name), "ethaddr");
 246         } else {
 247                 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
 248         }
 249         eth_setenv_enetaddr(env_name, mac);
 250         return 0;
 251 }
 252 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
 253
 254 static const iomux_cfg_t tx28_fec_pads[] = {
 255         MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
 256         MX28_PAD_ENET0_RXD0__ENET0_RXD0,
 257         MX28_PAD_ENET0_RXD1__ENET0_RXD1,
 258 };
 259
 260 int board_eth_init(bd_t *bis)
 261 {
 262         int ret;
 263
 264         /* Reset the external phy */
 265         gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
 266
 267         /* Power on the external phy */
 268         gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
 269
 270         /* Pull strap pins to high */
 271         gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
 272         gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
 273         gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
 274         gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
 275
 276         udelay(25000);
 277         gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
 278         udelay(100);
 279
 280         mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
 281
 282         ret = cpu_eth_init(bis);
 283         if (ret) {
 284                 printf("cpu_eth_init() failed: %d\n", ret);
 285                 return ret;
 286         }
 287
 288 #ifdef CONFIG_FEC_MXC_MULTI
 289         if (getenv("ethaddr")) {
 290                 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
 291                 if (ret) {
 292                         printf("FEC MXS: Unable to init FEC0\n");
 293                         return ret;
 294                 }
 295         }
 296
 297         if (getenv("eth1addr")) {
 298                 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
 299                 if (ret) {
 300                         printf("FEC MXS: Unable to init FEC1\n");
 301                         return ret;
 302                 }
 303         }
 304 #else
 305         if (getenv("ethaddr")) {
 306                 ret = fecmxc_initialize(bis);
 307                 if (ret) {
 308                         printf("FEC MXS: Unable to init FEC\n");
 309                         return ret;
 310                 }
 311         }
 312 #endif
 313         return 0;
 314 }
 315 #endif /* CONFIG_FEC_MXC */
 316
 317 enum {
 318         LED_STATE_INIT = -1,
 319         LED_STATE_OFF,
 320         LED_STATE_ON,
 321 };
 322
 323 void show_activity(int arg)
 324 {
 325         static int led_state = LED_STATE_INIT;
 326         static ulong last;
 327
 328         if (led_state == LED_STATE_INIT) {
 329                 last = get_timer(0);
 330                 gpio_set_value(TX28_LED_GPIO, 1);
 331                 led_state = LED_STATE_ON;
 332         } else {
 333                 if (get_timer(last) > CONFIG_SYS_HZ) {
 334                         last = get_timer(0);
 335                         if (led_state == LED_STATE_ON) {
 336                                 gpio_set_value(TX28_LED_GPIO, 0);
 337                         } else {
 338                                 gpio_set_value(TX28_LED_GPIO, 1);
 339                         }
 340                         led_state = 1 - led_state;
 341                 }
 342         }
 343 }
 344
 345 static const iomux_cfg_t stk5_pads[] = {
 346         /* SW controlled LED on STK5 baseboard */
 347         MX28_PAD_ENET0_RXD3__GPIO_4_10,
 348 };
 349
 350 static const struct gpio stk5_gpios[] = {
 351 };
 352
 353 #ifdef CONFIG_LCD
 354 static ushort tx28_cmap[256];
 355 vidinfo_t panel_info = {
 356         /* set to max. size supported by SoC */
 357         .vl_col = 1600,
 358         .vl_row = 1200,
 359
 360         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 361         .cmap = tx28_cmap,
 362 };
 363
 364 static struct fb_videomode tx28_fb_modes[] = {
 365         {
 366                 /* Standard VGA timing */
 367                 .name           = "VGA",
 368                 .refresh        = 60,
 369                 .xres           = 640,
 370                 .yres           = 480,
 371                 .pixclock       = KHZ2PICOS(25175),
 372                 .left_margin    = 48,
 373                 .hsync_len      = 96,
 374                 .right_margin   = 16,
 375                 .upper_margin   = 31,
 376                 .vsync_len      = 2,
 377                 .lower_margin   = 12,
 378                 .vmode          = FB_VMODE_NONINTERLACED,
 379         },
 380         {
 381                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 382                  * DE high active, 115.2 mm x 86.4 mm display area
 383                  * VGA compatible timing
 384                  */
 385                 .name           = "ETV570",
 386                 .refresh        = 60,
 387                 .xres           = 640,
 388                 .yres           = 480,
 389                 .pixclock       = KHZ2PICOS(25175),
 390                 .left_margin    = 114,
 391                 .hsync_len      = 30,
 392                 .right_margin   = 16,
 393                 .upper_margin   = 32,
 394                 .vsync_len      = 3,
 395                 .lower_margin   = 10,
 396                 .vmode          = FB_VMODE_NONINTERLACED,
 397         },
 398         {
 399                 /* Emerging ET0350G0DH6 320 x 240 display.
 400                  * 70.08 mm x 52.56 mm display area.
 401                  */
 402                 .name           = "ET0350",
 403                 .refresh        = 60,
 404                 .xres           = 320,
 405                 .yres           = 240,
 406                 .pixclock       = KHZ2PICOS(6500),
 407                 .left_margin    = 68 - 34,
 408                 .hsync_len      = 34,
 409                 .right_margin   = 20,
 410                 .upper_margin   = 18 - 3,
 411                 .vsync_len      = 3,
 412                 .lower_margin   = 4,
 413                 .vmode          = FB_VMODE_NONINTERLACED,
 414         },
 415         {
 416                 /* Emerging ET0430G0DH6 480 x 272 display.
 417                  * 95.04 mm x 53.856 mm display area.
 418                  */
 419                 .name           = "ET0430",
 420                 .refresh        = 60,
 421                 .xres           = 480,
 422                 .yres           = 272,
 423                 .pixclock       = KHZ2PICOS(9000),
 424                 .left_margin    = 2,
 425                 .hsync_len      = 41,
 426                 .right_margin   = 2,
 427                 .upper_margin   = 2,
 428                 .vsync_len      = 10,
 429                 .lower_margin   = 2,
 430                 .sync           = FB_SYNC_CLK_LAT_FALL,
 431                 .vmode          = FB_VMODE_NONINTERLACED,
 432         },
 433         {
 434                 /* Emerging ET0500G0DH6 800 x 480 display.
 435                  * 109.6 mm x 66.4 mm display area.
 436                  */
 437                 .name           = "ET0500",
 438                 .refresh        = 60,
 439                 .xres           = 800,
 440                 .yres           = 480,
 441                 .pixclock       = KHZ2PICOS(33260),
 442                 .left_margin    = 216 - 128,
 443                 .hsync_len      = 128,
 444                 .right_margin   = 1056 - 800 - 216,
 445                 .upper_margin   = 35 - 2,
 446                 .vsync_len      = 2,
 447                 .lower_margin   = 525 - 480 - 35,
 448                 .vmode          = FB_VMODE_NONINTERLACED,
 449         },
 450         {
 451                 /* Emerging ETQ570G0DH6 320 x 240 display.
 452                  * 115.2 mm x 86.4 mm display area.
 453                  */
 454                 .name           = "ETQ570",
 455                 .refresh        = 60,
 456                 .xres           = 320,
 457                 .yres           = 240,
 458                 .pixclock       = KHZ2PICOS(6400),
 459                 .left_margin    = 38,
 460                 .hsync_len      = 30,
 461                 .right_margin   = 30,
 462                 .upper_margin   = 16, /* 15 according to datasheet */
 463                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 464                 .lower_margin   = 4, /* 4.5 according to datasheet */
 465                 .vmode          = FB_VMODE_NONINTERLACED,
 466         },
 467         {
 468                 /* Emerging ET0700G0DH6 800 x 480 display.
 469                  * 152.4 mm x 91.44 mm display area.
 470                  */
 471                 .name           = "ET0700",
 472                 .refresh        = 60,
 473                 .xres           = 800,
 474                 .yres           = 480,
 475                 .pixclock       = KHZ2PICOS(33260),
 476                 .left_margin    = 216 - 128,
 477                 .hsync_len      = 128,
 478                 .right_margin   = 1056 - 800 - 216,
 479                 .upper_margin   = 35 - 2,
 480                 .vsync_len      = 2,
 481                 .lower_margin   = 525 - 480 - 35,
 482                 .vmode          = FB_VMODE_NONINTERLACED,
 483         },
 484         {
 485                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 486                 .vmode          = FB_VMODE_NONINTERLACED,
 487         },
 488 };
 489
 490 static int lcd_enabled = 1;
 491 static int lcd_bl_polarity;
 492
 493 static int lcd_backlight_polarity(void)
 494 {
 495         return lcd_bl_polarity;
 496 }
 497
 498 void lcd_enable(void)
 499 {
 500         /* HACK ALERT:
 501          * global variable from common/lcd.c
 502          * Set to 0 here to prevent messages from going to LCD
 503          * rather than serial console
 504          */
 505         lcd_is_enabled = 0;
 506
 507         karo_load_splashimage(1);
 508         if (lcd_enabled) {
 509                 debug("Switching LCD on\n");
 510                 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
 511                 udelay(100);
 512                 gpio_set_value(TX28_LCD_RST_GPIO, 1);
 513                 udelay(300000);
 514                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
 515                         lcd_backlight_polarity());
 516         }
 517 }
 518
 519 void lcd_disable(void)
 520 {
 521 }
 522
 523 void lcd_panel_disable(void)
 524 {
 525         if (lcd_enabled) {
 526                 debug("Switching LCD off\n");
 527                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
 528                         !lcd_backlight_polarity());
 529                 gpio_set_value(TX28_LCD_RST_GPIO, 0);
 530                 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
 531         }
 532 }
 533
 534 static const iomux_cfg_t stk5_lcd_pads[] = {
 535         /* LCD RESET */
 536         MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
 537         /* LCD POWER_ENABLE */
 538         MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
 539         /* LCD Backlight (PWM) */
 540         MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
 541
 542         /* Display */
 543         MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
 544         MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
 545         MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
 546         MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
 547         MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
 548         MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
 549         MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
 550         MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
 551         MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
 552         MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
 553         MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
 554         MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
 555         MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
 556         MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
 557         MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
 558         MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
 559         MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
 560         MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
 561         MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
 562         MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
 563         MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
 564         MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
 565         MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
 566         MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
 567         MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
 568         MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
 569         MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
 570         MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
 571 };
 572
 573 static const struct gpio stk5_lcd_gpios[] = {
 574         { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 575         { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 576         { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 577 };
 578
 579 extern void video_hw_init(void *lcdbase);
 580
 581 void lcd_ctrl_init(void *lcdbase)
 582 {
 583         int color_depth = 24;
 584         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 585         const char *vm;
 586         unsigned long val;
 587         int refresh = 60;
 588         struct fb_videomode *p = tx28_fb_modes;
 589         struct fb_videomode fb_mode;
 590         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 591
 592         if (!lcd_enabled) {
 593                 debug("LCD disabled\n");
 594                 return;
 595         }
 596
 597         if (had_ctrlc()) {
 598                 debug("Disabling LCD\n");
 599                 lcd_enabled = 0;
 600                 setenv("splashimage", NULL);
 601                 return;
 602         }
 603
 604         karo_fdt_move_fdt();
 605         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 606
 607         if (video_mode == NULL) {
 608                 debug("Disabling LCD\n");
 609                 lcd_enabled = 0;
 610                 return;
 611         }
 612         vm = video_mode;
 613         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 614                 p = &fb_mode;
 615                 debug("Using video mode from FDT\n");
 616                 vm += strlen(vm);
 617                 if (fb_mode.xres > panel_info.vl_col ||
 618                         fb_mode.yres > panel_info.vl_row) {
 619                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 620                                 fb_mode.xres, fb_mode.yres,
 621                                 panel_info.vl_col, panel_info.vl_row);
 622                         lcd_enabled = 0;
 623                         return;
 624                 }
 625         }
 626         if (p->name != NULL)
 627                 debug("Trying compiled-in video modes\n");
 628         while (p->name != NULL) {
 629                 if (strcmp(p->name, vm) == 0) {
 630                         debug("Using video mode: '%s'\n", p->name);
 631                         vm += strlen(vm);
 632                         break;
 633                 }
 634                 p++;
 635         }
 636         if (*vm != '\0')
 637                 debug("Trying to decode video_mode: '%s'\n", vm);
 638         while (*vm != '\0') {
 639                 if (*vm >= '0' && *vm <= '9') {
 640                         char *end;
 641
 642                         val = simple_strtoul(vm, &end, 0);
 643                         if (end > vm) {
 644                                 if (!xres_set) {
 645                                         if (val > panel_info.vl_col)
 646                                                 val = panel_info.vl_col;
 647                                         p->xres = val;
 648                                         panel_info.vl_col = val;
 649                                         xres_set = 1;
 650                                 } else if (!yres_set) {
 651                                         if (val > panel_info.vl_row)
 652                                                 val = panel_info.vl_row;
 653                                         p->yres = val;
 654                                         panel_info.vl_row = val;
 655                                         yres_set = 1;
 656                                 } else if (!bpp_set) {
 657                                         switch (val) {
 658                                         case 8:
 659                                         case 16:
 660                                         case 18:
 661                                         case 24:
 662                                                 color_depth = val;
 663                                                 break;
 664
 665                                         default:
 666                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 667                                                         end - vm, vm, color_depth);
 668                                         }
 669                                         bpp_set = 1;
 670                                 } else if (!refresh_set) {
 671                                         refresh = val;
 672                                         refresh_set = 1;
 673                                 }
 674                         }
 675                         vm = end;
 676                 }
 677                 switch (*vm) {
 678                 case '@':
 679                         bpp_set = 1;
 680                         /* fallthru */
 681                 case '-':
 682                         yres_set = 1;
 683                         /* fallthru */
 684                 case 'x':
 685                         xres_set = 1;
 686                         /* fallthru */
 687                 case 'M':
 688                 case 'R':
 689                         vm++;
 690                         break;
 691
 692                 default:
 693                         if (*vm != '\0')
 694                                 vm++;
 695                 }
 696         }
 697         if (p->xres == 0 || p->yres == 0) {
 698                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 699                 lcd_enabled = 0;
 700                 printf("Supported video modes are:");
 701                 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
 702                         printf(" %s", p->name);
 703                 }
 704                 printf("\n");
 705                 return;
 706         }
 707         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 708                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 709                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 710                 lcd_enabled = 0;
 711                 return;
 712         }
 713         panel_info.vl_col = p->xres;
 714         panel_info.vl_row = p->yres;
 715
 716         switch (color_depth) {
 717         case 8:
 718                 panel_info.vl_bpix = LCD_COLOR8;
 719                 break;
 720         case 16:
 721                 panel_info.vl_bpix = LCD_COLOR16;
 722                 break;
 723         default:
 724                 panel_info.vl_bpix = LCD_COLOR24;
 725         }
 726
 727         p->pixclock = KHZ2PICOS(refresh *
 728                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 729                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 730                                 1000);
 731         debug("Pixel clock set to %lu.%03lu MHz\n",
 732                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 733
 734         if (p != &fb_mode) {
 735                 int ret;
 736
 737                 debug("Creating new display-timing node from '%s'\n",
 738                         video_mode);
 739                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
 740                 if (ret)
 741                         printf("Failed to create new display-timing node from '%s': %d\n",
 742                                 video_mode, ret);
 743         }
 744
 745         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 746         mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
 747                                 ARRAY_SIZE(stk5_lcd_pads));
 748
 749         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
 750                 color_depth, refresh);
 751
 752         if (karo_load_splashimage(0) == 0) {
 753                 char vmode[128];
 754
 755                 /* setup env variable for mxsfb display driver */
 756                 snprintf(vmode, sizeof(vmode),
 757                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
 758                         p->xres, p->yres, p->left_margin, p->right_margin,
 759                         p->upper_margin, p->lower_margin, p->hsync_len,
 760                         p->vsync_len, p->sync, p->pixclock, color_depth);
 761                 setenv("videomode", vmode);
 762
 763                 debug("Initializing LCD controller\n");
 764                 video_hw_init(lcdbase);
 765                 setenv("videomode", NULL);
 766         } else {
 767                 debug("Skipping initialization of LCD controller\n");
 768         }
 769 }
 770 #else
 771 #define lcd_enabled 0
 772 #endif /* CONFIG_LCD */
 773
 774 static void stk5_board_init(void)
 775 {
 776         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 777         mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 778 }
 779
 780 static void stk5v3_board_init(void)
 781 {
 782         stk5_board_init();
 783 }
 784
 785 static void stk5v5_board_init(void)
 786 {
 787         stk5_board_init();
 788
 789         /* init flexcan transceiver enable GPIO */
 790         gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOF_OUTPUT_INIT_HIGH,
 791                         "Flexcan Transceiver");
 792         mxs_iomux_setup_pad(STK5_CAN_XCVR_GPIO);
 793 }
 794
 795 int tx28_fec1_enabled(void)
 796 {
 797         const char *status;
 798         int off;
 799
 800         if (!gd->fdt_blob)
 801                 return 0;
 802
 803         off = fdt_path_offset(gd->fdt_blob, "ethernet1");
 804         if (off < 0)
 805                 return 0;
 806
 807         status = fdt_getprop(gd->fdt_blob, off, "status", NULL);
 808         return status && (strcmp(status, "okay") == 0);
 809 }
 810
 811 static void tx28_init_mac(void)
 812 {
 813         int ret;
 814
 815         ret = fec_get_mac_addr(0);
 816         if (ret < 0) {
 817                 printf("Failed to read FEC0 MAC address from OCOTP\n");
 818                 return;
 819         }
 820 #ifdef CONFIG_FEC_MXC_MULTI
 821         if (tx28_fec1_enabled()) {
 822                 ret = fec_get_mac_addr(1);
 823                 if (ret < 0) {
 824                         printf("Failed to read FEC1 MAC address from OCOTP\n");
 825                         return;
 826                 }
 827         }
 828 #endif
 829 }
 830
 831 int board_late_init(void)
 832 {
 833         int ret = 0;
 834         const char *baseboard;
 835
 836         karo_fdt_move_fdt();
 837
 838         baseboard = getenv("baseboard");
 839         if (!baseboard)
 840                 goto exit;
 841
 842         printf("Baseboard: %s\n", baseboard);
 843
 844         if (strncmp(baseboard, "stk5", 4) == 0) {
 845                 if ((strlen(baseboard) == 4) ||
 846                         strcmp(baseboard, "stk5-v3") == 0) {
 847                         stk5v3_board_init();
 848                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 849                         const char *otg_mode = getenv("otg_mode");
 850
 851                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
 852                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
 853                                         otg_mode, baseboard);
 854                                 setenv("otg_mode", "none");
 855                         }
 856                         stk5v5_board_init();
 857                 } else {
 858                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 859                                 baseboard + 4);
 860                 }
 861         } else {
 862                 printf("WARNING: Unsupported baseboard: '%s'\n",
 863                         baseboard);
 864                 ret = -EINVAL;
 865         }
 866
 867 exit:
 868         tx28_init_mac();
 869         clear_ctrlc();
 870         return ret;
 871 }
 872
 873 #define BOOT_CAUSE_MASK         (RTC_PERSISTENT0_EXTERNAL_RESET |       \
 874                                 RTC_PERSISTENT0_ALARM_WAKE |            \
 875                                 RTC_PERSISTENT0_THERMAL_RESET)
 876
 877 static void thermal_init(void)
 878 {
 879         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 880         struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
 881
 882         writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
 883                 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
 884                 &power_regs->hw_power_thermal);
 885
 886         writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
 887                 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
 888                 &clkctrl_regs->hw_clkctrl_reset);
 889 }
 890
 891 int checkboard(void)
 892 {
 893         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 894         u32 pwr_sts = readl(&power_regs->hw_power_sts);
 895         u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
 896         const char *dlm = "";
 897
 898         printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
 899                 CONFIG_SDRAM_SIZE / SZ_128M +
 900                 CONFIG_SYS_NAND_BLOCKS / 2048 * 2);
 901
 902         printf("POWERUP Source: ");
 903         if (pwrup_src & (3 << 0)) {
 904                 printf("%sPSWITCH %s voltage", dlm,
 905                         pwrup_src & (1 << 1) ? "HIGH" : "MID");
 906                 dlm = " | ";
 907         }
 908         if (pwrup_src & (1 << 4)) {
 909                 printf("%sRTC", dlm);
 910                 dlm = " | ";
 911         }
 912         if (pwrup_src & (1 << 5)) {
 913                 printf("%s5V", dlm);
 914                 dlm = " | ";
 915         }
 916         printf("\n");
 917
 918         if (boot_cause & BOOT_CAUSE_MASK) {
 919                 dlm="";
 920                 printf("Last boot cause: ");
 921                 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
 922                         printf("%sEXTERNAL", dlm);
 923                         dlm = " | ";
 924                 }
 925                 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
 926                         printf("%sTHERMAL", dlm);
 927                         dlm = " | ";
 928                 }
 929                 if (*dlm != '\0')
 930                         printf(" RESET");
 931                 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
 932                         printf("%sALARM WAKE", dlm);
 933                         dlm = " | ";
 934                 }
 935                 printf("\n");
 936         }
 937
 938         while (pwr_sts & POWER_STS_THERMAL_WARNING) {
 939                 static int first = 1;
 940
 941                 if (first) {
 942                         printf("CPU too hot to boot\n");
 943                         first = 0;
 944                 }
 945                 if (tstc())
 946                         break;
 947                 pwr_sts = readl(&power_regs->hw_power_sts);
 948         }
 949
 950         if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
 951                 thermal_init();
 952
 953         return 0;
 954 }
 955
 956 #if defined(CONFIG_OF_BOARD_SETUP)
 957 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 958 #include <jffs2/jffs2.h>
 959 #include <mtd_node.h>
 960 static struct node_info tx28_nand_nodes[] = {
 961         { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
 962 };
 963 #else
 964 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 965 #endif
 966
 967 static const char *tx28_touchpanels[] = {
 968         "ti,tsc2007",
 969         "edt,edt-ft5x06",
 970         "fsl,imx28-lradc",
 971 };
 972
 973 void ft_board_setup(void *blob, bd_t *bd)
 974 {
 975         const char *baseboard = getenv("baseboard");
 976         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
 977         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 978         int ret;
 979
 980         ret = fdt_increase_size(blob, 4096);
 981         if (ret)
 982                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
 983
 984 #ifdef CONFIG_TX28_S
 985         /* TX28-41xx (aka TX28S) has no external RTC
 986          * and no I2C GPIO extender
 987          */
 988         karo_fdt_remove_node(blob, "ds1339");
 989         karo_fdt_remove_node(blob, "gpio5");
 990 #endif
 991         if (stk5_v5)
 992                 karo_fdt_enable_node(blob, "stk5led", 0);
 993
 994         fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
 995         fdt_fixup_ethernet(blob);
 996
 997         karo_fdt_fixup_touchpanel(blob, tx28_touchpanels,
 998                                 ARRAY_SIZE(tx28_touchpanels));
 999         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1000         karo_fdt_fixup_flexcan(blob, stk5_v5);
1001         karo_fdt_update_fb_mode(blob, video_mode);
1002 }
1003 #endif /* CONFIG_OF_BOARD_SETUP */