board/karo/tx28/tx28.c

   1 /*
   2  * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <common.h>
  21 #include <errno.h>
  22 #include <libfdt.h>
  23 #include <fdt_support.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <linux/list.h>
  28 #include <linux/fb.h>
  29 #include <asm/io.h>
  30 #include <asm/gpio.h>
  31 #include <asm/arch/iomux-mx28.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/imx-regs.h>
  34 #include <asm/arch/sys_proto.h>
  35
  36 #include "../common/karo.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define MXS_GPIO_NR(p, o)      (((p) << 5) | (o))
  41
  42 #define TX28_LCD_PWR_GPIO       MX28_PAD_LCD_ENABLE__GPIO_1_31
  43 #define TX28_LCD_RST_GPIO       MX28_PAD_LCD_RESET__GPIO_3_30
  44 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
  45
  46 #define TX28_USBH_VBUSEN_GPIO   MX28_PAD_SPDIF__GPIO_3_27
  47 #define TX28_USBH_OC_GPIO       MX28_PAD_JTAG_RTCK__GPIO_4_20
  48 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
  49 #define TX28_USBOTG_OC_GPIO     MX28_PAD_GPMI_CE3N__GPIO_0_19
  50 #define TX28_USBOTG_ID_GPIO     MX28_PAD_PWM2__GPIO_3_18
  51
  52 #define TX28_LED_GPIO           MX28_PAD_ENET0_RXD3__GPIO_4_10
  53
  54 static const struct gpio tx28_gpios[] = {
  55         { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
  56         { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
  57         { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
  58         { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
  59         { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
  60 };
  61
  62 static const iomux_cfg_t tx28_pads[] = {
  63         /* UART pads */
  64 #if CONFIG_CONS_INDEX == 0
  65         MX28_PAD_AUART0_RX__DUART_CTS,
  66         MX28_PAD_AUART0_TX__DUART_RTS,
  67         MX28_PAD_AUART0_CTS__DUART_RX,
  68         MX28_PAD_AUART0_RTS__DUART_TX,
  69 #elif CONFIG_CONS_INDEX == 1
  70         MX28_PAD_AUART1_RX__AUART1_RX,
  71         MX28_PAD_AUART1_TX__AUART1_TX,
  72         MX28_PAD_AUART1_CTS__AUART1_CTS,
  73         MX28_PAD_AUART1_RTS__AUART1_RTS,
  74 #elif CONFIG_CONS_INDEX == 2
  75         MX28_PAD_AUART3_RX__AUART3_RX,
  76         MX28_PAD_AUART3_TX__AUART3_TX,
  77         MX28_PAD_AUART3_CTS__AUART3_CTS,
  78         MX28_PAD_AUART3_RTS__AUART3_RTS,
  79 #endif
  80         /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
  81         MX28_PAD_I2C0_SCL__I2C0_SCL,
  82         MX28_PAD_I2C0_SDA__I2C0_SDA,
  83
  84         /* USBH VBUSEN, OC */
  85         MX28_PAD_SPDIF__GPIO_3_27,
  86         MX28_PAD_JTAG_RTCK__GPIO_4_20,
  87
  88         /* USBOTG VBUSEN, OC, ID */
  89         MX28_PAD_GPMI_CE2N__GPIO_0_18,
  90         MX28_PAD_GPMI_CE3N__GPIO_0_19,
  91         MX28_PAD_PWM2__GPIO_3_18,
  92 };
  93
  94 /*
  95  * Functions
  96  */
  97
  98 /* provide at least _some_ sort of randomness */
  99 #define MAX_LOOPS       100
 100
 101 static u32 random;
 102
 103 static inline void random_init(void)
 104 {
 105         struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
 106         u32 seed = 0;
 107         int i;
 108
 109         for (i = 0; i < MAX_LOOPS; i++) {
 110                 unsigned int usec = readl(&digctl_regs->hw_digctl_microseconds);
 111
 112                 seed = get_timer(usec + random + seed);
 113                 srand(seed);
 114                 random = rand();
 115         }
 116 }
 117
 118 #define RTC_PERSISTENT0_CLK32_MASK      (RTC_PERSISTENT0_CLOCKSOURCE |  \
 119                                         RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
 120 static u32 boot_cause __attribute__((section("data")));
 121
 122 int board_early_init_f(void)
 123 {
 124         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 125         u32 rtc_stat;
 126         int timeout = 5000;
 127
 128         random_init();
 129
 130         /* IO0 clock at 480MHz */
 131         mxs_set_ioclk(MXC_IOCLK0, 480000);
 132         /* IO1 clock at 480MHz */
 133         mxs_set_ioclk(MXC_IOCLK1, 480000);
 134
 135         /* SSP0 clock at 96MHz */
 136         mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 137         /* SSP2 clock at 96MHz */
 138         mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
 139
 140         gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
 141         mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
 142
 143         while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
 144                 RTC_STAT_STALE_REGS_PERSISTENT0) {
 145                 if (timeout-- < 0)
 146                         return 0;
 147                 udelay(1);
 148         }
 149         boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
 150         if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
 151                 RTC_PERSISTENT0_CLK32_MASK) {
 152                 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
 153                         goto rtc_err;
 154                 writel(RTC_PERSISTENT0_CLK32_MASK,
 155                         &rtc_regs->hw_rtc_persistent0_set);
 156         }
 157         return 0;
 158
 159 rtc_err:
 160         serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
 161         return 0;
 162 }
 163
 164 int board_init(void)
 165 {
 166         /* Address of boot parameters */
 167 #ifdef CONFIG_OF_LIBFDT
 168         gd->bd->bi_arch_number = -1;
 169 #endif
 170         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 171         return 0;
 172 }
 173
 174 int dram_init(void)
 175 {
 176         return mxs_dram_init();
 177 }
 178
 179 #ifdef  CONFIG_CMD_MMC
 180 static int tx28_mmc_wp(int dev_no)
 181 {
 182         return 0;
 183 }
 184
 185 int board_mmc_init(bd_t *bis)
 186 {
 187         return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
 188 }
 189 #endif /* CONFIG_CMD_MMC */
 190
 191 #ifdef CONFIG_FEC_MXC
 192 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
 193
 194 #ifdef CONFIG_FEC_MXC_MULTI
 195 #define FEC_MAX_IDX                     1
 196 #else
 197 #define FEC_MAX_IDX                     0
 198 #endif
 199 #ifndef ETH_ALEN
 200 #define ETH_ALEN                        6
 201 #endif
 202
 203 static int fec_get_mac_addr(int index)
 204 {
 205         int timeout = 1000;
 206         struct mxs_ocotp_regs *ocotp_regs =
 207                 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
 208         u32 *cust = &ocotp_regs->hw_ocotp_cust0;
 209         u8 mac[ETH_ALEN];
 210         char env_name[] = "eth.addr";
 211         u32 val = 0;
 212         int i;
 213
 214         if (index < 0 || index > FEC_MAX_IDX)
 215                 return -EINVAL;
 216
 217         /* set this bit to open the OTP banks for reading */
 218         writel(OCOTP_CTRL_RD_BANK_OPEN,
 219                 &ocotp_regs->hw_ocotp_ctrl_set);
 220
 221         /* wait until OTP contents are readable */
 222         while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
 223                 if (timeout-- < 0)
 224                         return -ETIMEDOUT;
 225                 udelay(100);
 226         }
 227
 228         for (i = 0; i < sizeof(mac); i++) {
 229                 int shift = 24 - i % 4 * 8;
 230
 231                 if (i % 4 == 0)
 232                         val = readl(&cust[index * 8 + i]);
 233                 mac[i] = val >> shift;
 234         }
 235         if (!is_valid_ether_addr(mac))
 236                 return 0;
 237
 238         if (index == 0)
 239                 snprintf(env_name, sizeof(env_name), "ethaddr");
 240         else
 241                 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
 242
 243         eth_setenv_enetaddr(env_name, mac);
 244         return 0;
 245 }
 246 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
 247
 248 static const iomux_cfg_t tx28_fec_pads[] = {
 249         MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
 250         MX28_PAD_ENET0_RXD0__ENET0_RXD0,
 251         MX28_PAD_ENET0_RXD1__ENET0_RXD1,
 252 };
 253
 254 int board_eth_init(bd_t *bis)
 255 {
 256         int ret;
 257
 258         /* Reset the external phy */
 259         gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
 260
 261         /* Power on the external phy */
 262         gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
 263
 264         /* Pull strap pins to high */
 265         gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
 266         gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
 267         gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
 268         gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
 269
 270         udelay(25000);
 271         gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
 272         udelay(100);
 273
 274         mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
 275
 276         ret = cpu_eth_init(bis);
 277         if (ret) {
 278                 printf("cpu_eth_init() failed: %d\n", ret);
 279                 return ret;
 280         }
 281
 282         ret = fec_get_mac_addr(0);
 283         if (ret < 0) {
 284                 printf("Failed to read FEC0 MAC address from OCOTP\n");
 285                 return ret;
 286         }
 287 #ifdef CONFIG_FEC_MXC_MULTI
 288         if (getenv("ethaddr")) {
 289                 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
 290                 if (ret) {
 291                         printf("FEC MXS: Unable to init FEC0\n");
 292                         return ret;
 293                 }
 294         }
 295
 296         ret = fec_get_mac_addr(1);
 297         if (ret < 0) {
 298                 printf("Failed to read FEC1 MAC address from OCOTP\n");
 299                 return ret;
 300         }
 301         if (getenv("eth1addr")) {
 302                 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
 303                 if (ret) {
 304                         printf("FEC MXS: Unable to init FEC1\n");
 305                         return ret;
 306                 }
 307         }
 308         return 0;
 309 #else
 310         if (getenv("ethaddr")) {
 311                 ret = fecmxc_initialize(bis);
 312         }
 313         return ret;
 314 #endif
 315 }
 316 #endif /* CONFIG_FEC_MXC */
 317
 318 enum {
 319         LED_STATE_INIT = -1,
 320         LED_STATE_OFF,
 321         LED_STATE_ON,
 322 };
 323
 324 void show_activity(int arg)
 325 {
 326         static int led_state = LED_STATE_INIT;
 327         static ulong last;
 328
 329         if (led_state == LED_STATE_INIT) {
 330                 last = get_timer(0);
 331                 gpio_set_value(TX28_LED_GPIO, 1);
 332                 led_state = LED_STATE_ON;
 333         } else {
 334                 if (get_timer(last) > CONFIG_SYS_HZ) {
 335                         last = get_timer(0);
 336                         if (led_state == LED_STATE_ON) {
 337                                 gpio_set_value(TX28_LED_GPIO, 0);
 338                         } else {
 339                                 gpio_set_value(TX28_LED_GPIO, 1);
 340                         }
 341                         led_state = 1 - led_state;
 342                 }
 343         }
 344 }
 345
 346 static const iomux_cfg_t stk5_pads[] = {
 347         /* SW controlled LED on STK5 baseboard */
 348         MX28_PAD_ENET0_RXD3__GPIO_4_10,
 349 };
 350
 351 static const struct gpio stk5_gpios[] = {
 352 };
 353
 354 #ifdef CONFIG_LCD
 355 static ushort tx28_cmap[256];
 356 vidinfo_t panel_info = {
 357         /* set to max. size supported by SoC */
 358         .vl_col = 1600,
 359         .vl_row = 1200,
 360
 361         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 362         .cmap = tx28_cmap,
 363 };
 364
 365 static struct fb_videomode tx28_fb_modes[] = {
 366         {
 367                 /* Standard VGA timing */
 368                 .name           = "VGA",
 369                 .refresh        = 60,
 370                 .xres           = 640,
 371                 .yres           = 480,
 372                 .pixclock       = KHZ2PICOS(25175),
 373                 .left_margin    = 48,
 374                 .hsync_len      = 96,
 375                 .right_margin   = 16,
 376                 .upper_margin   = 31,
 377                 .vsync_len      = 2,
 378                 .lower_margin   = 12,
 379                 .vmode          = FB_VMODE_NONINTERLACED,
 380         },
 381         {
 382                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 383                  * DE high active, 115.2 mm x 86.4 mm display area
 384                  * VGA compatible timing
 385                  */
 386                 .name           = "ETV570",
 387                 .refresh        = 60,
 388                 .xres           = 640,
 389                 .yres           = 480,
 390                 .pixclock       = KHZ2PICOS(25175),
 391                 .left_margin    = 114,
 392                 .hsync_len      = 30,
 393                 .right_margin   = 16,
 394                 .upper_margin   = 32,
 395                 .vsync_len      = 3,
 396                 .lower_margin   = 10,
 397                 .vmode          = FB_VMODE_NONINTERLACED,
 398         },
 399         {
 400                 /* Emerging ET0350G0DH6 320 x 240 display.
 401                  * 70.08 mm x 52.56 mm display area.
 402                  */
 403                 .name           = "ET0350",
 404                 .refresh        = 60,
 405                 .xres           = 320,
 406                 .yres           = 240,
 407                 .pixclock       = KHZ2PICOS(6500),
 408                 .left_margin    = 68 - 34,
 409                 .hsync_len      = 34,
 410                 .right_margin   = 20,
 411                 .upper_margin   = 18 - 3,
 412                 .vsync_len      = 3,
 413                 .lower_margin   = 4,
 414                 .vmode          = FB_VMODE_NONINTERLACED,
 415         },
 416         {
 417                 /* Emerging ET0430G0DH6 480 x 272 display.
 418                  * 95.04 mm x 53.856 mm display area.
 419                  */
 420                 .name           = "ET0430",
 421                 .refresh        = 60,
 422                 .xres           = 480,
 423                 .yres           = 272,
 424                 .pixclock       = KHZ2PICOS(9000),
 425                 .left_margin    = 2,
 426                 .hsync_len      = 41,
 427                 .right_margin   = 2,
 428                 .upper_margin   = 2,
 429                 .vsync_len      = 10,
 430                 .lower_margin   = 2,
 431                 .vmode          = FB_VMODE_NONINTERLACED,
 432         },
 433         {
 434                 /* Emerging ET0500G0DH6 800 x 480 display.
 435                  * 109.6 mm x 66.4 mm display area.
 436                  */
 437                 .name           = "ET0500",
 438                 .refresh        = 60,
 439                 .xres           = 800,
 440                 .yres           = 480,
 441                 .pixclock       = KHZ2PICOS(33260),
 442                 .left_margin    = 216 - 128,
 443                 .hsync_len      = 128,
 444                 .right_margin   = 1056 - 800 - 216,
 445                 .upper_margin   = 35 - 2,
 446                 .vsync_len      = 2,
 447                 .lower_margin   = 525 - 480 - 35,
 448                 .vmode          = FB_VMODE_NONINTERLACED,
 449         },
 450         {
 451                 /* Emerging ETQ570G0DH6 320 x 240 display.
 452                  * 115.2 mm x 86.4 mm display area.
 453                  */
 454                 .name           = "ETQ570",
 455                 .refresh        = 60,
 456                 .xres           = 320,
 457                 .yres           = 240,
 458                 .pixclock       = KHZ2PICOS(6400),
 459                 .left_margin    = 38,
 460                 .hsync_len      = 30,
 461                 .right_margin   = 30,
 462                 .upper_margin   = 16, /* 15 according to datasheet */
 463                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 464                 .lower_margin   = 4, /* 4.5 according to datasheet */
 465                 .vmode          = FB_VMODE_NONINTERLACED,
 466         },
 467         {
 468                 /* Emerging ET0700G0DH6 800 x 480 display.
 469                  * 152.4 mm x 91.44 mm display area.
 470                  */
 471                 .name           = "ET0700",
 472                 .refresh        = 60,
 473                 .xres           = 800,
 474                 .yres           = 480,
 475                 .pixclock       = KHZ2PICOS(33260),
 476                 .left_margin    = 216 - 128,
 477                 .hsync_len      = 128,
 478                 .right_margin   = 1056 - 800 - 216,
 479                 .upper_margin   = 35 - 2,
 480                 .vsync_len      = 2,
 481                 .lower_margin   = 525 - 480 - 35,
 482                 .vmode          = FB_VMODE_NONINTERLACED,
 483         },
 484         {
 485                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 486                 .vmode          = FB_VMODE_NONINTERLACED,
 487         },
 488 };
 489
 490 static int lcd_enabled = 1;
 491
 492 void lcd_enable(void)
 493 {
 494         /* HACK ALERT:
 495          * global variable from common/lcd.c
 496          * Set to 0 here to prevent messages from going to LCD
 497          * rather than serial console
 498          */
 499         lcd_is_enabled = 0;
 500
 501         karo_load_splashimage(1);
 502         if (lcd_enabled) {
 503                 debug("Switching LCD on\n");
 504                 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
 505                 udelay(100);
 506                 gpio_set_value(TX28_LCD_RST_GPIO, 1);
 507                 udelay(300000);
 508                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 0);
 509         }
 510 }
 511
 512 void lcd_disable(void)
 513 {
 514 }
 515
 516 void lcd_panel_disable(void)
 517 {
 518         if (lcd_enabled) {
 519                 debug("Switching LCD off\n");
 520                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 1);
 521                 gpio_set_value(TX28_LCD_RST_GPIO, 0);
 522                 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
 523         }
 524 }
 525
 526 static const iomux_cfg_t stk5_lcd_pads[] = {
 527         /* LCD RESET */
 528         MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
 529         /* LCD POWER_ENABLE */
 530         MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
 531         /* LCD Backlight (PWM) */
 532         MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
 533
 534         /* Display */
 535         MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
 536         MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
 537         MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
 538         MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
 539         MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
 540         MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
 541         MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
 542         MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
 543         MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
 544         MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
 545         MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
 546         MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
 547         MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
 548         MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
 549         MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
 550         MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
 551         MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
 552         MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
 553         MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
 554         MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
 555         MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
 556         MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
 557         MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
 558         MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
 559         MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
 560         MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
 561         MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
 562         MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
 563         MX28_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
 564         MX28_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
 565         MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
 566 };
 567
 568 static const struct gpio stk5_lcd_gpios[] = {
 569         { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 570         { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 571         { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 572 };
 573
 574 extern void video_hw_init(void *lcdbase);
 575
 576 void lcd_ctrl_init(void *lcdbase)
 577 {
 578         int color_depth = 24;
 579         char *vm;
 580         unsigned long val;
 581         int refresh = 60;
 582         struct fb_videomode *p = tx28_fb_modes;
 583         struct fb_videomode fb_mode;
 584         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 585
 586         if (!lcd_enabled) {
 587                 debug("LCD disabled\n");
 588                 return;
 589         }
 590
 591         if (tstc()) {
 592                 debug("Disabling LCD\n");
 593                 lcd_enabled = 0;
 594                 return;
 595         }
 596
 597         karo_fdt_move_fdt();
 598
 599         vm = getenv("video_mode");
 600         if (vm == NULL) {
 601                 debug("Disabling LCD\n");
 602                 lcd_enabled = 0;
 603                 return;
 604         }
 605         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 606                 p = &fb_mode;
 607                 debug("Using video mode from FDT\n");
 608                 vm += strlen(vm);
 609         }
 610         if (p->name != NULL)
 611                 debug("Trying compiled-in video modes\n");
 612         while (p->name != NULL) {
 613                 if (strcmp(p->name, vm) == 0) {
 614                         debug("Using video mode: '%s'\n", p->name);
 615                         vm += strlen(vm);
 616                         break;
 617                 }
 618                 p++;
 619         }
 620         if (*vm != '\0')
 621                 debug("Trying to decode video_mode: '%s'\n", vm);
 622         while (*vm != '\0') {
 623                 if (*vm >= '0' && *vm <= '9') {
 624                         char *end;
 625
 626                         val = simple_strtoul(vm, &end, 0);
 627                         if (end > vm) {
 628                                 if (!xres_set) {
 629                                         if (val > panel_info.vl_col)
 630                                                 val = panel_info.vl_col;
 631                                         p->xres = val;
 632                                         xres_set = 1;
 633                                 } else if (!yres_set) {
 634                                         if (val > panel_info.vl_row)
 635                                                 val = panel_info.vl_row;
 636                                         p->yres = val;
 637                                         yres_set = 1;
 638                                 } else if (!bpp_set) {
 639                                         switch (val) {
 640                                         case 8:
 641                                         case 16:
 642                                         case 18:
 643                                         case 24:
 644                                                 color_depth = val;
 645                                                 break;
 646
 647                                         default:
 648                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 649                                                         end - vm, vm, color_depth);
 650                                         }
 651                                         bpp_set = 1;
 652                                 } else if (!refresh_set) {
 653                                         refresh = val;
 654                                         refresh_set = 1;
 655                                 }
 656                         }
 657                         vm = end;
 658                 }
 659                 switch (*vm) {
 660                 case '@':
 661                         bpp_set = 1;
 662                         /* fallthru */
 663                 case '-':
 664                         yres_set = 1;
 665                         /* fallthru */
 666                 case 'x':
 667                         xres_set = 1;
 668                         /* fallthru */
 669                 case 'M':
 670                 case 'R':
 671                         vm++;
 672                         break;
 673
 674                 default:
 675                         if (*vm != '\0')
 676                                 vm++;
 677                 }
 678         }
 679         if (p->xres == 0 || p->yres == 0) {
 680                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 681                 lcd_enabled = 0;
 682                 printf("Supported video modes are:");
 683                 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
 684                         printf(" %s", p->name);
 685                 }
 686                 printf("\n");
 687                 return;
 688         }
 689         panel_info.vl_col = p->xres;
 690         panel_info.vl_row = p->yres;
 691
 692         switch (color_depth) {
 693         case 8:
 694                 panel_info.vl_bpix = LCD_COLOR8;
 695                 break;
 696         case 16:
 697                 panel_info.vl_bpix = LCD_COLOR16;
 698                 break;
 699         default:
 700                 panel_info.vl_bpix = LCD_COLOR24;
 701         }
 702
 703         p->pixclock = KHZ2PICOS(refresh *
 704                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 705                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 706                                 1000);
 707         debug("Pixel clock set to %lu.%03lu MHz\n",
 708                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 709
 710         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 711         mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
 712                                 ARRAY_SIZE(stk5_lcd_pads));
 713
 714         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
 715                 color_depth, refresh);
 716
 717         if (karo_load_splashimage(0) == 0) {
 718                 char vmode[32];
 719
 720                 /* setup env variable for mxsfb display driver */
 721                 snprintf(vmode, sizeof(vmode), "%dx%dMR-%d@%d",
 722                         p->xres, p->yres, color_depth, refresh);
 723                 setenv("videomode", vmode);
 724
 725                 debug("Initializing LCD controller\n");
 726                 video_hw_init(lcdbase);
 727                 setenv("videomode", NULL);
 728         } else {
 729                 debug("Skipping initialization of LCD controller\n");
 730         }
 731 }
 732 #else
 733 #define lcd_enabled 0
 734 #endif /* CONFIG_LCD */
 735
 736 static void stk5_board_init(void)
 737 {
 738         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 739         mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 740 }
 741
 742 static void stk5v3_board_init(void)
 743 {
 744         stk5_board_init();
 745 }
 746
 747 static void stk5v5_board_init(void)
 748 {
 749         stk5_board_init();
 750
 751         /* init flexcan transceiver enable GPIO */
 752         gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH,
 753                         "Flexcan Transceiver");
 754         mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0);
 755 }
 756
 757 int board_late_init(void)
 758 {
 759         const char *baseboard;
 760
 761         karo_fdt_move_fdt();
 762
 763         baseboard = getenv("baseboard");
 764         if (!baseboard)
 765                 return 0;
 766
 767         if (strncmp(baseboard, "stk5", 4) == 0) {
 768                 printf("Baseboard: %s\n", baseboard);
 769                 if ((strlen(baseboard) == 4) ||
 770                         strcmp(baseboard, "stk5-v3") == 0) {
 771                         stk5v3_board_init();
 772                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 773                         const char *otg_mode = getenv("otg_mode");
 774
 775                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
 776                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
 777                                         otg_mode, baseboard);
 778                                 setenv("otg_mode", "none");
 779                         }
 780                         stk5v5_board_init();
 781                 } else {
 782                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 783                                 baseboard + 4);
 784                 }
 785         } else {
 786                 printf("WARNING: Unsupported baseboard: '%s'\n",
 787                         baseboard);
 788                 return -EINVAL;
 789         }
 790
 791         return 0;
 792 }
 793
 794 #define BOOT_CAUSE_MASK         (RTC_PERSISTENT0_EXTERNAL_RESET |       \
 795                                 RTC_PERSISTENT0_ALARM_WAKE |            \
 796                                 RTC_PERSISTENT0_THERMAL_RESET)
 797
 798 static void thermal_init(void)
 799 {
 800         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 801         struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
 802
 803         writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
 804                 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
 805                 &power_regs->hw_power_thermal);
 806
 807         writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
 808                 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
 809                 &clkctrl_regs->hw_clkctrl_reset);
 810 }
 811
 812 int checkboard(void)
 813 {
 814         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 815         u32 pwr_sts = readl(&power_regs->hw_power_sts);
 816         u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
 817         const char *dlm = "";
 818
 819         printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
 820                 CONFIG_SDRAM_SIZE / SZ_128M);
 821
 822         printf("POWERUP Source: ");
 823         if (pwrup_src & (3 << 0)) {
 824                 printf("%sPSWITCH %s voltage", dlm,
 825                         pwrup_src & (1 << 1) ? "HIGH" : "MID");
 826                 dlm = " | ";
 827         }
 828         if (pwrup_src & (1 << 4)) {
 829                 printf("%sRTC", dlm);
 830                 dlm = " | ";
 831         }
 832         if (pwrup_src & (1 << 5)) {
 833                 printf("%s5V", dlm);
 834                 dlm = " | ";
 835         }
 836         printf("\n");
 837
 838         if (boot_cause & BOOT_CAUSE_MASK) {
 839                 dlm="";
 840                 printf("Last boot cause: ");
 841                 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
 842                         printf("%sEXTERNAL", dlm);
 843                         dlm = " | ";
 844                 }
 845                 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
 846                         printf("%sTHERMAL", dlm);
 847                         dlm = " | ";
 848                 }
 849                 if (*dlm != '\0')
 850                         printf(" RESET");
 851                 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
 852                         printf("%sALARM WAKE", dlm);
 853                         dlm = " | ";
 854                 }
 855                 printf("\n");
 856         }
 857
 858         while (pwr_sts & POWER_STS_THERMAL_WARNING) {
 859                 static int first = 1;
 860
 861                 if (first) {
 862                         printf("CPU too hot to boot\n");
 863                         first = 0;
 864                 }
 865                 if (tstc())
 866                         break;
 867                 pwr_sts = readl(&power_regs->hw_power_sts);
 868         }
 869
 870         if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
 871                 thermal_init();
 872
 873         return 0;
 874 }
 875
 876 #if defined(CONFIG_OF_BOARD_SETUP)
 877 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 878 #include <jffs2/jffs2.h>
 879 #include <mtd_node.h>
 880 struct node_info tx28_nand_nodes[] = {
 881         { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
 882 };
 883 #else
 884 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 885 #endif
 886
 887 static int flexcan_enabled(void *blob)
 888 {
 889         const char *status;
 890         int off = fdt_path_offset(blob, "can0");
 891
 892         if (off < 0) {
 893                 printf("node 'can0' not found\n");
 894         } else {
 895                 status = fdt_getprop(blob, off, "status", NULL);
 896                 if (status && strcmp(status, "okay") == 0) {
 897                         printf("can0 is enabled\n");
 898                         return 1;
 899                 }
 900         }
 901         off = fdt_path_offset(blob, "can1");
 902         if (off < 0) {
 903                 printf("node 'can1' not found\n");
 904                 return 0;
 905         }
 906         status = fdt_getprop(blob, off, "status", NULL);
 907         if (status && strcmp(status, "okay") == 0) {
 908                 printf("can1 is enabled\n");
 909                 return 1;
 910         }
 911         printf("can driver disabled\n");
 912         return 0;
 913 }
 914
 915 static void tx28_set_lcd_pins(void *blob, const char *name)
 916 {
 917         int off = fdt_path_offset(blob, name);
 918         u32 ph;
 919         const struct fdt_property *pc;
 920         int len;
 921
 922         if (off < 0)
 923                 return;
 924
 925         ph = fdt32_to_cpu(fdt_create_phandle(blob, off));
 926         if (!ph)
 927                 return;
 928
 929         off = fdt_path_offset(blob, "lcdif");
 930         if (off < 0)
 931                 return;
 932
 933         pc = fdt_get_property(blob, off, "pinctrl-0", &len);
 934         if (!pc || len < sizeof(ph))
 935                 return;
 936
 937         memcpy((void *)pc->data, &ph, sizeof(ph));
 938         fdt_setprop(blob, off, "pinctrl-0", pc->data, len);
 939 }
 940
 941 static void tx28_fixup_flexcan(void *blob, int stk5_v5)
 942 {
 943         const char *can_xcvr = "disabled";
 944
 945         if (stk5_v5) {
 946                 if (flexcan_enabled(blob)) {
 947                         tx28_set_lcd_pins(blob, "lcdif_23bit_pins_a");
 948                         can_xcvr = "okay";
 949                 } else {
 950                         tx28_set_lcd_pins(blob, "lcdif_24bit_pins_a");
 951                 }
 952         } else {
 953                 const char *otg_mode = getenv("otg_mode");
 954
 955                 if (otg_mode && (strcmp(otg_mode, "host") == 0))
 956                         karo_fdt_enable_node(blob, "can1", 0);
 957         }
 958         fdt_find_and_setprop(blob, "/regulators/can-xcvr", "status",
 959                         can_xcvr, strlen(can_xcvr) + 1, 1);
 960 }
 961
 962 static void tx28_fixup_fec(void *blob)
 963 {
 964         karo_fdt_enable_node(blob, "ethernet1", 0);
 965 }
 966
 967 void ft_board_setup(void *blob, bd_t *bd)
 968 {
 969         const char *baseboard = getenv("baseboard");
 970         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
 971
 972 #ifdef CONFIG_TX28_S
 973         /* TX28-41xx (aka TX28S) has no external RTC
 974          * and no I2C GPIO extender
 975          */
 976         karo_fdt_remove_node(blob, "ds1339");
 977         karo_fdt_remove_node(blob, "gpio5");
 978 #endif
 979         if (stk5_v5) {
 980                 karo_fdt_remove_node(blob, "stk5led");
 981         } else {
 982                 tx28_fixup_fec(blob);
 983         }
 984         tx28_fixup_flexcan(blob, stk5_v5);
 985
 986         fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
 987         fdt_fixup_ethernet(blob);
 988
 989         karo_fdt_fixup_touchpanel(blob);
 990         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
 991         karo_fdt_update_fb_mode(blob, getenv("video_mode"));
 992 }
 993 #endif