board/karo/tx28/tx28.c

   1 /*
   2  * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <common.h>
  21 #include <errno.h>
  22 #include <libfdt.h>
  23 #include <fdt_support.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <linux/list.h>
  28 #include <linux/fb.h>
  29 #include <asm/io.h>
  30 #include <asm/gpio.h>
  31 #include <asm/arch/iomux-mx28.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/imx-regs.h>
  34 #include <asm/arch/sys_proto.h>
  35
  36 #include "../common/karo.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define MXS_GPIO_NR(p, o)      (((p) << 5) | (o))
  41
  42 #define TX28_LCD_PWR_GPIO       MX28_PAD_LCD_ENABLE__GPIO_1_31
  43 #define TX28_LCD_RST_GPIO       MX28_PAD_LCD_RESET__GPIO_3_30
  44 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
  45
  46 #define TX28_USBH_VBUSEN_GPIO   MX28_PAD_SPDIF__GPIO_3_27
  47 #define TX28_USBH_OC_GPIO       MX28_PAD_JTAG_RTCK__GPIO_4_20
  48 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
  49 #define TX28_USBOTG_OC_GPIO     MX28_PAD_GPMI_CE3N__GPIO_0_19
  50 #define TX28_USBOTG_ID_GPIO     MX28_PAD_PWM2__GPIO_3_18
  51
  52 #define TX28_LED_GPIO           MX28_PAD_ENET0_RXD3__GPIO_4_10
  53
  54 static const struct gpio tx28_gpios[] = {
  55         { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
  56         { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
  57         { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
  58         { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
  59         { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
  60 };
  61
  62 static const iomux_cfg_t tx28_pads[] = {
  63         /* UART pads */
  64 #if CONFIG_CONS_INDEX == 0
  65         MX28_PAD_AUART0_RX__DUART_CTS,
  66         MX28_PAD_AUART0_TX__DUART_RTS,
  67         MX28_PAD_AUART0_CTS__DUART_RX,
  68         MX28_PAD_AUART0_RTS__DUART_TX,
  69 #elif CONFIG_CONS_INDEX == 1
  70         MX28_PAD_AUART1_RX__AUART1_RX,
  71         MX28_PAD_AUART1_TX__AUART1_TX,
  72         MX28_PAD_AUART1_CTS__AUART1_CTS,
  73         MX28_PAD_AUART1_RTS__AUART1_RTS,
  74 #elif CONFIG_CONS_INDEX == 2
  75         MX28_PAD_AUART3_RX__AUART3_RX,
  76         MX28_PAD_AUART3_TX__AUART3_TX,
  77         MX28_PAD_AUART3_CTS__AUART3_CTS,
  78         MX28_PAD_AUART3_RTS__AUART3_RTS,
  79 #endif
  80         /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
  81         MX28_PAD_I2C0_SCL__I2C0_SCL,
  82         MX28_PAD_I2C0_SDA__I2C0_SDA,
  83
  84         /* USBH VBUSEN, OC */
  85         MX28_PAD_SPDIF__GPIO_3_27,
  86         MX28_PAD_JTAG_RTCK__GPIO_4_20,
  87
  88         /* USBOTG VBUSEN, OC, ID */
  89         MX28_PAD_GPMI_CE2N__GPIO_0_18,
  90         MX28_PAD_GPMI_CE3N__GPIO_0_19,
  91         MX28_PAD_PWM2__GPIO_3_18,
  92 };
  93
  94 /*
  95  * Functions
  96  */
  97
  98 /* provide at least _some_ sort of randomness */
  99 #define MAX_LOOPS       100
 100
 101 static u32 random;
 102
 103 static inline void random_init(void)
 104 {
 105         struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
 106         u32 seed = 0;
 107         int i;
 108
 109         for (i = 0; i < MAX_LOOPS; i++) {
 110                 unsigned int usec = readl(&digctl_regs->hw_digctl_microseconds);
 111
 112                 seed = get_timer(usec + random + seed);
 113                 srand(seed);
 114                 random = rand();
 115         }
 116 }
 117
 118 #define RTC_PERSISTENT0_CLK32_MASK      (RTC_PERSISTENT0_CLOCKSOURCE |  \
 119                                         RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
 120 static u32 boot_cause __attribute__((section("data")));
 121
 122 int board_early_init_f(void)
 123 {
 124         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 125         u32 rtc_stat;
 126         int timeout = 5000;
 127
 128         random_init();
 129
 130         /* IO0 clock at 480MHz */
 131         mxs_set_ioclk(MXC_IOCLK0, 480000);
 132         /* IO1 clock at 480MHz */
 133         mxs_set_ioclk(MXC_IOCLK1, 480000);
 134
 135         /* SSP0 clock at 96MHz */
 136         mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 137         /* SSP2 clock at 96MHz */
 138         mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
 139
 140         gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
 141         mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
 142
 143         while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
 144                 RTC_STAT_STALE_REGS_PERSISTENT0) {
 145                 if (timeout-- < 0)
 146                         return 0;
 147                 udelay(1);
 148         }
 149         boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
 150         if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
 151                 RTC_PERSISTENT0_CLK32_MASK) {
 152                 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
 153                         goto rtc_err;
 154                 writel(RTC_PERSISTENT0_CLK32_MASK,
 155                         &rtc_regs->hw_rtc_persistent0_set);
 156         }
 157         return 0;
 158
 159 rtc_err:
 160         serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
 161         return 0;
 162 }
 163
 164 int board_init(void)
 165 {
 166         /* Address of boot parameters */
 167 #ifdef CONFIG_OF_LIBFDT
 168         gd->bd->bi_arch_number = -1;
 169 #endif
 170         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 171         return 0;
 172 }
 173
 174 int dram_init(void)
 175 {
 176         return mxs_dram_init();
 177 }
 178
 179 #ifdef  CONFIG_CMD_MMC
 180 static int tx28_mmc_wp(int dev_no)
 181 {
 182         return 0;
 183 }
 184
 185 int board_mmc_init(bd_t *bis)
 186 {
 187         return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
 188 }
 189 #endif /* CONFIG_CMD_MMC */
 190
 191 #ifdef CONFIG_FEC_MXC
 192 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
 193
 194 #ifdef CONFIG_FEC_MXC_MULTI
 195 #define FEC_MAX_IDX                     1
 196 #else
 197 #define FEC_MAX_IDX                     0
 198 #endif
 199 #ifndef ETH_ALEN
 200 #define ETH_ALEN                        6
 201 #endif
 202
 203 static int fec_get_mac_addr(int index)
 204 {
 205         int timeout = 1000;
 206         struct mxs_ocotp_regs *ocotp_regs =
 207                 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
 208         u32 *cust = &ocotp_regs->hw_ocotp_cust0;
 209         u8 mac[ETH_ALEN];
 210         char env_name[] = "eth.addr";
 211         u32 val = 0;
 212         int i;
 213
 214         if (index < 0 || index > FEC_MAX_IDX)
 215                 return -EINVAL;
 216
 217         /* set this bit to open the OTP banks for reading */
 218         writel(OCOTP_CTRL_RD_BANK_OPEN,
 219                 &ocotp_regs->hw_ocotp_ctrl_set);
 220
 221         /* wait until OTP contents are readable */
 222         while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
 223                 if (timeout-- < 0)
 224                         return -ETIMEDOUT;
 225                 udelay(100);
 226         }
 227
 228         for (i = 0; i < sizeof(mac); i++) {
 229                 int shift = 24 - i % 4 * 8;
 230
 231                 if (i % 4 == 0)
 232                         val = readl(&cust[index * 8 + i]);
 233                 mac[i] = val >> shift;
 234         }
 235         if (!is_valid_ether_addr(mac))
 236                 return 0;
 237
 238         if (index == 0) {
 239                 printf("MAC addr from fuse: %pM\n", mac);
 240                 snprintf(env_name, sizeof(env_name), "ethaddr");
 241         } else {
 242                 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
 243         }
 244         eth_setenv_enetaddr(env_name, mac);
 245         return 0;
 246 }
 247 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
 248
 249 static const iomux_cfg_t tx28_fec_pads[] = {
 250         MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
 251         MX28_PAD_ENET0_RXD0__ENET0_RXD0,
 252         MX28_PAD_ENET0_RXD1__ENET0_RXD1,
 253 };
 254
 255 int board_eth_init(bd_t *bis)
 256 {
 257         int ret;
 258
 259         /* Reset the external phy */
 260         gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
 261
 262         /* Power on the external phy */
 263         gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
 264
 265         /* Pull strap pins to high */
 266         gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
 267         gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
 268         gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
 269         gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
 270
 271         udelay(25000);
 272         gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
 273         udelay(100);
 274
 275         mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
 276
 277         ret = cpu_eth_init(bis);
 278         if (ret) {
 279                 printf("cpu_eth_init() failed: %d\n", ret);
 280                 return ret;
 281         }
 282
 283 #ifdef CONFIG_FEC_MXC_MULTI
 284         if (getenv("ethaddr")) {
 285                 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
 286                 if (ret) {
 287                         printf("FEC MXS: Unable to init FEC0\n");
 288                         return ret;
 289                 }
 290         }
 291
 292         if (getenv("eth1addr")) {
 293                 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
 294                 if (ret) {
 295                         printf("FEC MXS: Unable to init FEC1\n");
 296                         return ret;
 297                 }
 298         }
 299         return 0;
 300 #else
 301         if (getenv("ethaddr")) {
 302                 ret = fecmxc_initialize(bis);
 303         }
 304         return ret;
 305 #endif
 306 }
 307 #endif /* CONFIG_FEC_MXC */
 308
 309 enum {
 310         LED_STATE_INIT = -1,
 311         LED_STATE_OFF,
 312         LED_STATE_ON,
 313 };
 314
 315 void show_activity(int arg)
 316 {
 317         static int led_state = LED_STATE_INIT;
 318         static ulong last;
 319
 320         if (led_state == LED_STATE_INIT) {
 321                 last = get_timer(0);
 322                 gpio_set_value(TX28_LED_GPIO, 1);
 323                 led_state = LED_STATE_ON;
 324         } else {
 325                 if (get_timer(last) > CONFIG_SYS_HZ) {
 326                         last = get_timer(0);
 327                         if (led_state == LED_STATE_ON) {
 328                                 gpio_set_value(TX28_LED_GPIO, 0);
 329                         } else {
 330                                 gpio_set_value(TX28_LED_GPIO, 1);
 331                         }
 332                         led_state = 1 - led_state;
 333                 }
 334         }
 335 }
 336
 337 static const iomux_cfg_t stk5_pads[] = {
 338         /* SW controlled LED on STK5 baseboard */
 339         MX28_PAD_ENET0_RXD3__GPIO_4_10,
 340 };
 341
 342 static const struct gpio stk5_gpios[] = {
 343 };
 344
 345 #ifdef CONFIG_LCD
 346 static ushort tx28_cmap[256];
 347 vidinfo_t panel_info = {
 348         /* set to max. size supported by SoC */
 349         .vl_col = 1600,
 350         .vl_row = 1200,
 351
 352         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 353         .cmap = tx28_cmap,
 354 };
 355
 356 static struct fb_videomode tx28_fb_modes[] = {
 357         {
 358                 /* Standard VGA timing */
 359                 .name           = "VGA",
 360                 .refresh        = 60,
 361                 .xres           = 640,
 362                 .yres           = 480,
 363                 .pixclock       = KHZ2PICOS(25175),
 364                 .left_margin    = 48,
 365                 .hsync_len      = 96,
 366                 .right_margin   = 16,
 367                 .upper_margin   = 31,
 368                 .vsync_len      = 2,
 369                 .lower_margin   = 12,
 370                 .vmode          = FB_VMODE_NONINTERLACED,
 371         },
 372         {
 373                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 374                  * DE high active, 115.2 mm x 86.4 mm display area
 375                  * VGA compatible timing
 376                  */
 377                 .name           = "ETV570",
 378                 .refresh        = 60,
 379                 .xres           = 640,
 380                 .yres           = 480,
 381                 .pixclock       = KHZ2PICOS(25175),
 382                 .left_margin    = 114,
 383                 .hsync_len      = 30,
 384                 .right_margin   = 16,
 385                 .upper_margin   = 32,
 386                 .vsync_len      = 3,
 387                 .lower_margin   = 10,
 388                 .vmode          = FB_VMODE_NONINTERLACED,
 389         },
 390         {
 391                 /* Emerging ET0350G0DH6 320 x 240 display.
 392                  * 70.08 mm x 52.56 mm display area.
 393                  */
 394                 .name           = "ET0350",
 395                 .refresh        = 60,
 396                 .xres           = 320,
 397                 .yres           = 240,
 398                 .pixclock       = KHZ2PICOS(6500),
 399                 .left_margin    = 68 - 34,
 400                 .hsync_len      = 34,
 401                 .right_margin   = 20,
 402                 .upper_margin   = 18 - 3,
 403                 .vsync_len      = 3,
 404                 .lower_margin   = 4,
 405                 .vmode          = FB_VMODE_NONINTERLACED,
 406         },
 407         {
 408                 /* Emerging ET0430G0DH6 480 x 272 display.
 409                  * 95.04 mm x 53.856 mm display area.
 410                  */
 411                 .name           = "ET0430",
 412                 .refresh        = 60,
 413                 .xres           = 480,
 414                 .yres           = 272,
 415                 .pixclock       = KHZ2PICOS(9000),
 416                 .left_margin    = 2,
 417                 .hsync_len      = 41,
 418                 .right_margin   = 2,
 419                 .upper_margin   = 2,
 420                 .vsync_len      = 10,
 421                 .lower_margin   = 2,
 422                 .vmode          = FB_VMODE_NONINTERLACED,
 423         },
 424         {
 425                 /* Emerging ET0500G0DH6 800 x 480 display.
 426                  * 109.6 mm x 66.4 mm display area.
 427                  */
 428                 .name           = "ET0500",
 429                 .refresh        = 60,
 430                 .xres           = 800,
 431                 .yres           = 480,
 432                 .pixclock       = KHZ2PICOS(33260),
 433                 .left_margin    = 216 - 128,
 434                 .hsync_len      = 128,
 435                 .right_margin   = 1056 - 800 - 216,
 436                 .upper_margin   = 35 - 2,
 437                 .vsync_len      = 2,
 438                 .lower_margin   = 525 - 480 - 35,
 439                 .vmode          = FB_VMODE_NONINTERLACED,
 440         },
 441         {
 442                 /* Emerging ETQ570G0DH6 320 x 240 display.
 443                  * 115.2 mm x 86.4 mm display area.
 444                  */
 445                 .name           = "ETQ570",
 446                 .refresh        = 60,
 447                 .xres           = 320,
 448                 .yres           = 240,
 449                 .pixclock       = KHZ2PICOS(6400),
 450                 .left_margin    = 38,
 451                 .hsync_len      = 30,
 452                 .right_margin   = 30,
 453                 .upper_margin   = 16, /* 15 according to datasheet */
 454                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 455                 .lower_margin   = 4, /* 4.5 according to datasheet */
 456                 .vmode          = FB_VMODE_NONINTERLACED,
 457         },
 458         {
 459                 /* Emerging ET0700G0DH6 800 x 480 display.
 460                  * 152.4 mm x 91.44 mm display area.
 461                  */
 462                 .name           = "ET0700",
 463                 .refresh        = 60,
 464                 .xres           = 800,
 465                 .yres           = 480,
 466                 .pixclock       = KHZ2PICOS(33260),
 467                 .left_margin    = 216 - 128,
 468                 .hsync_len      = 128,
 469                 .right_margin   = 1056 - 800 - 216,
 470                 .upper_margin   = 35 - 2,
 471                 .vsync_len      = 2,
 472                 .lower_margin   = 525 - 480 - 35,
 473                 .vmode          = FB_VMODE_NONINTERLACED,
 474         },
 475         {
 476                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 477                 .vmode          = FB_VMODE_NONINTERLACED,
 478         },
 479 };
 480
 481 static int lcd_enabled = 1;
 482
 483 void lcd_enable(void)
 484 {
 485         /* HACK ALERT:
 486          * global variable from common/lcd.c
 487          * Set to 0 here to prevent messages from going to LCD
 488          * rather than serial console
 489          */
 490         lcd_is_enabled = 0;
 491
 492         karo_load_splashimage(1);
 493         if (lcd_enabled) {
 494                 debug("Switching LCD on\n");
 495                 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
 496                 udelay(100);
 497                 gpio_set_value(TX28_LCD_RST_GPIO, 1);
 498                 udelay(300000);
 499                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 0);
 500         }
 501 }
 502
 503 void lcd_disable(void)
 504 {
 505 }
 506
 507 void lcd_panel_disable(void)
 508 {
 509         if (lcd_enabled) {
 510                 debug("Switching LCD off\n");
 511                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 1);
 512                 gpio_set_value(TX28_LCD_RST_GPIO, 0);
 513                 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
 514         }
 515 }
 516
 517 static const iomux_cfg_t stk5_lcd_pads[] = {
 518         /* LCD RESET */
 519         MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
 520         /* LCD POWER_ENABLE */
 521         MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
 522         /* LCD Backlight (PWM) */
 523         MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
 524
 525         /* Display */
 526         MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
 527         MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
 528         MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
 529         MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
 530         MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
 531         MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
 532         MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
 533         MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
 534         MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
 535         MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
 536         MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
 537         MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
 538         MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
 539         MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
 540         MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
 541         MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
 542         MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
 543         MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
 544         MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
 545         MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
 546         MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
 547         MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
 548         MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
 549         MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
 550         MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
 551         MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
 552         MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
 553         MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
 554         MX28_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
 555         MX28_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
 556         MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
 557 };
 558
 559 static const struct gpio stk5_lcd_gpios[] = {
 560         { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 561         { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 562         { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 563 };
 564
 565 extern void video_hw_init(void *lcdbase);
 566
 567 void lcd_ctrl_init(void *lcdbase)
 568 {
 569         int color_depth = 24;
 570         char *vm;
 571         unsigned long val;
 572         int refresh = 60;
 573         struct fb_videomode *p = tx28_fb_modes;
 574         struct fb_videomode fb_mode;
 575         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 576
 577         if (!lcd_enabled) {
 578                 debug("LCD disabled\n");
 579                 return;
 580         }
 581
 582         if (tstc()) {
 583                 debug("Disabling LCD\n");
 584                 lcd_enabled = 0;
 585                 return;
 586         }
 587
 588         karo_fdt_move_fdt();
 589
 590         vm = getenv("video_mode");
 591         if (vm == NULL) {
 592                 debug("Disabling LCD\n");
 593                 lcd_enabled = 0;
 594                 return;
 595         }
 596         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 597                 p = &fb_mode;
 598                 debug("Using video mode from FDT\n");
 599                 vm += strlen(vm);
 600         }
 601         if (p->name != NULL)
 602                 debug("Trying compiled-in video modes\n");
 603         while (p->name != NULL) {
 604                 if (strcmp(p->name, vm) == 0) {
 605                         debug("Using video mode: '%s'\n", p->name);
 606                         vm += strlen(vm);
 607                         break;
 608                 }
 609                 p++;
 610         }
 611         if (*vm != '\0')
 612                 debug("Trying to decode video_mode: '%s'\n", vm);
 613         while (*vm != '\0') {
 614                 if (*vm >= '0' && *vm <= '9') {
 615                         char *end;
 616
 617                         val = simple_strtoul(vm, &end, 0);
 618                         if (end > vm) {
 619                                 if (!xres_set) {
 620                                         if (val > panel_info.vl_col)
 621                                                 val = panel_info.vl_col;
 622                                         p->xres = val;
 623                                         xres_set = 1;
 624                                 } else if (!yres_set) {
 625                                         if (val > panel_info.vl_row)
 626                                                 val = panel_info.vl_row;
 627                                         p->yres = val;
 628                                         yres_set = 1;
 629                                 } else if (!bpp_set) {
 630                                         switch (val) {
 631                                         case 8:
 632                                         case 16:
 633                                         case 18:
 634                                         case 24:
 635                                                 color_depth = val;
 636                                                 break;
 637
 638                                         default:
 639                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 640                                                         end - vm, vm, color_depth);
 641                                         }
 642                                         bpp_set = 1;
 643                                 } else if (!refresh_set) {
 644                                         refresh = val;
 645                                         refresh_set = 1;
 646                                 }
 647                         }
 648                         vm = end;
 649                 }
 650                 switch (*vm) {
 651                 case '@':
 652                         bpp_set = 1;
 653                         /* fallthru */
 654                 case '-':
 655                         yres_set = 1;
 656                         /* fallthru */
 657                 case 'x':
 658                         xres_set = 1;
 659                         /* fallthru */
 660                 case 'M':
 661                 case 'R':
 662                         vm++;
 663                         break;
 664
 665                 default:
 666                         if (*vm != '\0')
 667                                 vm++;
 668                 }
 669         }
 670         if (p->xres == 0 || p->yres == 0) {
 671                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 672                 lcd_enabled = 0;
 673                 printf("Supported video modes are:");
 674                 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
 675                         printf(" %s", p->name);
 676                 }
 677                 printf("\n");
 678                 return;
 679         }
 680         panel_info.vl_col = p->xres;
 681         panel_info.vl_row = p->yres;
 682
 683         switch (color_depth) {
 684         case 8:
 685                 panel_info.vl_bpix = LCD_COLOR8;
 686                 break;
 687         case 16:
 688                 panel_info.vl_bpix = LCD_COLOR16;
 689                 break;
 690         default:
 691                 panel_info.vl_bpix = LCD_COLOR24;
 692         }
 693
 694         p->pixclock = KHZ2PICOS(refresh *
 695                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 696                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 697                                 1000);
 698         debug("Pixel clock set to %lu.%03lu MHz\n",
 699                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 700
 701         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 702         mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
 703                                 ARRAY_SIZE(stk5_lcd_pads));
 704
 705         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
 706                 color_depth, refresh);
 707
 708         if (karo_load_splashimage(0) == 0) {
 709                 char vmode[32];
 710
 711                 /* setup env variable for mxsfb display driver */
 712                 snprintf(vmode, sizeof(vmode), "%dx%dMR-%d@%d",
 713                         p->xres, p->yres, color_depth, refresh);
 714                 setenv("videomode", vmode);
 715
 716                 debug("Initializing LCD controller\n");
 717                 video_hw_init(lcdbase);
 718                 setenv("videomode", NULL);
 719         } else {
 720                 debug("Skipping initialization of LCD controller\n");
 721         }
 722 }
 723 #else
 724 #define lcd_enabled 0
 725 #endif /* CONFIG_LCD */
 726
 727 static void stk5_board_init(void)
 728 {
 729         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 730         mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 731 }
 732
 733 static void stk5v3_board_init(void)
 734 {
 735         stk5_board_init();
 736 }
 737
 738 static void stk5v5_board_init(void)
 739 {
 740         stk5_board_init();
 741
 742         /* init flexcan transceiver enable GPIO */
 743         gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH,
 744                         "Flexcan Transceiver");
 745         mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0);
 746 }
 747
 748 int board_late_init(void)
 749 {
 750         int ret;
 751         const char *baseboard;
 752
 753         karo_fdt_move_fdt();
 754
 755         baseboard = getenv("baseboard");
 756         if (!baseboard)
 757                 return 0;
 758
 759         if (strncmp(baseboard, "stk5", 4) == 0) {
 760                 printf("Baseboard: %s\n", baseboard);
 761                 if ((strlen(baseboard) == 4) ||
 762                         strcmp(baseboard, "stk5-v3") == 0) {
 763                         stk5v3_board_init();
 764                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 765                         const char *otg_mode = getenv("otg_mode");
 766
 767                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
 768                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
 769                                         otg_mode, baseboard);
 770                                 setenv("otg_mode", "none");
 771                         }
 772                         stk5v5_board_init();
 773                 } else {
 774                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 775                                 baseboard + 4);
 776                 }
 777         } else {
 778                 printf("WARNING: Unsupported baseboard: '%s'\n",
 779                         baseboard);
 780                 return -EINVAL;
 781         }
 782
 783         ret = fec_get_mac_addr(0);
 784         if (ret < 0) {
 785                 printf("Failed to read FEC0 MAC address from OCOTP\n");
 786                 return ret;
 787         }
 788 #ifdef CONFIG_FEC_MXC_MULTI
 789         ret = fec_get_mac_addr(1);
 790         if (ret < 0) {
 791                 printf("Failed to read FEC1 MAC address from OCOTP\n");
 792                 return ret;
 793         }
 794 #endif
 795         return 0;
 796 }
 797
 798 #define BOOT_CAUSE_MASK         (RTC_PERSISTENT0_EXTERNAL_RESET |       \
 799                                 RTC_PERSISTENT0_ALARM_WAKE |            \
 800                                 RTC_PERSISTENT0_THERMAL_RESET)
 801
 802 static void thermal_init(void)
 803 {
 804         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 805         struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
 806
 807         writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
 808                 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
 809                 &power_regs->hw_power_thermal);
 810
 811         writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
 812                 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
 813                 &clkctrl_regs->hw_clkctrl_reset);
 814 }
 815
 816 int checkboard(void)
 817 {
 818         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 819         u32 pwr_sts = readl(&power_regs->hw_power_sts);
 820         u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
 821         const char *dlm = "";
 822
 823         printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
 824                 CONFIG_SDRAM_SIZE / SZ_128M);
 825
 826         printf("POWERUP Source: ");
 827         if (pwrup_src & (3 << 0)) {
 828                 printf("%sPSWITCH %s voltage", dlm,
 829                         pwrup_src & (1 << 1) ? "HIGH" : "MID");
 830                 dlm = " | ";
 831         }
 832         if (pwrup_src & (1 << 4)) {
 833                 printf("%sRTC", dlm);
 834                 dlm = " | ";
 835         }
 836         if (pwrup_src & (1 << 5)) {
 837                 printf("%s5V", dlm);
 838                 dlm = " | ";
 839         }
 840         printf("\n");
 841
 842         if (boot_cause & BOOT_CAUSE_MASK) {
 843                 dlm="";
 844                 printf("Last boot cause: ");
 845                 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
 846                         printf("%sEXTERNAL", dlm);
 847                         dlm = " | ";
 848                 }
 849                 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
 850                         printf("%sTHERMAL", dlm);
 851                         dlm = " | ";
 852                 }
 853                 if (*dlm != '\0')
 854                         printf(" RESET");
 855                 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
 856                         printf("%sALARM WAKE", dlm);
 857                         dlm = " | ";
 858                 }
 859                 printf("\n");
 860         }
 861
 862         while (pwr_sts & POWER_STS_THERMAL_WARNING) {
 863                 static int first = 1;
 864
 865                 if (first) {
 866                         printf("CPU too hot to boot\n");
 867                         first = 0;
 868                 }
 869                 if (tstc())
 870                         break;
 871                 pwr_sts = readl(&power_regs->hw_power_sts);
 872         }
 873
 874         if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
 875                 thermal_init();
 876
 877         return 0;
 878 }
 879
 880 #if defined(CONFIG_OF_BOARD_SETUP)
 881 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 882 #include <jffs2/jffs2.h>
 883 #include <mtd_node.h>
 884 struct node_info tx28_nand_nodes[] = {
 885         { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
 886 };
 887 #else
 888 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 889 #endif
 890
 891 static int flexcan_enabled(void *blob)
 892 {
 893         const char *status;
 894         int off = fdt_path_offset(blob, "can0");
 895
 896         if (off < 0) {
 897                 printf("node 'can0' not found\n");
 898         } else {
 899                 status = fdt_getprop(blob, off, "status", NULL);
 900                 if (status && strcmp(status, "okay") == 0) {
 901                         printf("can0 is enabled\n");
 902                         return 1;
 903                 }
 904         }
 905         off = fdt_path_offset(blob, "can1");
 906         if (off < 0) {
 907                 printf("node 'can1' not found\n");
 908                 return 0;
 909         }
 910         status = fdt_getprop(blob, off, "status", NULL);
 911         if (status && strcmp(status, "okay") == 0) {
 912                 printf("can1 is enabled\n");
 913                 return 1;
 914         }
 915         printf("can driver disabled\n");
 916         return 0;
 917 }
 918
 919 static void tx28_set_lcd_pins(void *blob, const char *name)
 920 {
 921         int off = fdt_path_offset(blob, name);
 922         u32 ph;
 923         const struct fdt_property *pc;
 924         int len;
 925
 926         if (off < 0)
 927                 return;
 928
 929         ph = fdt32_to_cpu(fdt_create_phandle(blob, off));
 930         if (!ph)
 931                 return;
 932
 933         off = fdt_path_offset(blob, "lcdif");
 934         if (off < 0)
 935                 return;
 936
 937         pc = fdt_get_property(blob, off, "pinctrl-0", &len);
 938         if (!pc || len < sizeof(ph))
 939                 return;
 940
 941         memcpy((void *)pc->data, &ph, sizeof(ph));
 942         fdt_setprop(blob, off, "pinctrl-0", pc->data, len);
 943 }
 944
 945 static void tx28_fixup_flexcan(void *blob, int stk5_v5)
 946 {
 947         const char *can_xcvr = "disabled";
 948
 949         if (stk5_v5) {
 950                 if (flexcan_enabled(blob)) {
 951                         tx28_set_lcd_pins(blob, "lcdif_23bit_pins_a");
 952                         can_xcvr = "okay";
 953                 } else {
 954                         tx28_set_lcd_pins(blob, "lcdif_24bit_pins_a");
 955                 }
 956         } else {
 957                 const char *otg_mode = getenv("otg_mode");
 958
 959                 if (otg_mode && (strcmp(otg_mode, "host") == 0))
 960                         karo_fdt_enable_node(blob, "can1", 0);
 961         }
 962         fdt_find_and_setprop(blob, "/regulators/can-xcvr", "status",
 963                         can_xcvr, strlen(can_xcvr) + 1, 1);
 964 }
 965
 966 static void tx28_fixup_fec(void *blob)
 967 {
 968         karo_fdt_enable_node(blob, "ethernet1", 0);
 969 }
 970
 971 void ft_board_setup(void *blob, bd_t *bd)
 972 {
 973         const char *baseboard = getenv("baseboard");
 974         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
 975
 976 #ifdef CONFIG_TX28_S
 977         /* TX28-41xx (aka TX28S) has no external RTC
 978          * and no I2C GPIO extender
 979          */
 980         karo_fdt_remove_node(blob, "ds1339");
 981         karo_fdt_remove_node(blob, "gpio5");
 982 #endif
 983         if (stk5_v5) {
 984                 karo_fdt_remove_node(blob, "stk5led");
 985         } else {
 986                 tx28_fixup_fec(blob);
 987         }
 988         tx28_fixup_flexcan(blob, stk5_v5);
 989
 990         fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
 991         fdt_fixup_ethernet(blob);
 992
 993         karo_fdt_fixup_touchpanel(blob);
 994         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
 995         karo_fdt_update_fb_mode(blob, getenv("video_mode"));
 996 }
 997 #endif