2 * Copyright (C) 2012-2013 Lothar Waßmann <LW@KARO-electronics.de>
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
24 #include <fdt_support.h>
27 #include <linux/mtd/nand.h>
30 #include <asm/cache.h>
32 #include <asm/arch/cpu.h>
33 #include <asm/arch/hardware.h>
34 #include <asm/arch/mmc_host_def.h>
35 #include <asm/arch/mux.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/clock.h>
39 #include <asm/arch/da8xx-fb.h>
41 #include "../common/karo.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
46 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
47 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
48 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
49 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
50 #define TX48_MMC_CD_GPIO AM33XX_GPIO_NR(3, 15)
52 #define NO_OF_MAC_ADDR 1
62 #define PAD_CTRL_BASE 0x800
63 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
67 * Configure the pin mux for the module
69 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
74 for (i = 0; i < num_pins; i++)
75 writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
78 #define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
79 #define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
80 #define PRM_RSTST_WDT1_RST (1 << 4)
81 #define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
82 #define PRM_RSTST_ICEPICK_RST (1 << 9)
84 static u32 prm_rstst __attribute__((section(".data")));
87 * Basic board specific setup
89 static const struct pin_mux tx48_pads[] = {
90 { OFFSET(i2c0_sda), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
91 { OFFSET(i2c0_scl), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
92 { OFFSET(emu1), MODE(7), }, /* ETH PHY Reset */
95 static const struct pin_mux tx48_i2c_pads[] = {
96 { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
97 { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
100 static const struct gpio tx48_gpios[] = {
101 { AM33XX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "I2C1_SDA", },
102 { AM33XX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "I2C1_SCL", },
103 { AM33XX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "ETH_PHY_RESET", },
106 static const struct pin_mux stk5_pads[] = {
108 { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
110 { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
111 /* LCD POWER_ENABLE */
112 { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
113 /* LCD Backlight (PWM) */
114 { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
116 { OFFSET(mcasp0_fsx), MODE(7) | PULLUDEN | PULLUP_EN, },
119 static const struct gpio stk5_gpios[] = {
120 { TX48_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
121 { TX48_MMC_CD_GPIO, GPIOFLAG_INPUT, "MMC0 CD", },
124 static const struct pin_mux stk5_lcd_pads[] = {
126 { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
127 { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
128 { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
129 { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
130 { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
131 { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
132 { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
133 { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
134 { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
135 { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
136 { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
137 { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
138 { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
139 { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
140 { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
141 { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
142 /* LCD control signals */
143 { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
144 { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
145 { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
146 { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
149 static const struct gpio stk5_lcd_gpios[] = {
150 { AM33XX_GPIO_NR(1, 19), GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
151 { AM33XX_GPIO_NR(1, 22), GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
152 { AM33XX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
155 static const struct pin_mux stk5v5_pads[] = {
156 /* CAN transceiver control */
157 { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
160 static const struct gpio stk5v5_gpios[] = {
161 { AM33XX_GPIO_NR(0, 22), GPIOFLAG_OUTPUT_INIT_HIGH, "CAN XCVR", },
165 static u16 tx48_cmap[256];
166 vidinfo_t panel_info = {
167 /* set to max. size supported by SoC */
171 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
175 static struct lcd_ctrl_config lcd_cfg = {
179 #define FB_SYNC_OE_LOW_ACT (1 << 31)
180 #define FB_SYNC_CLK_LAT_FALL (1 << 30)
182 static struct fb_videomode tx48_fb_modes[] = {
184 /* Standard VGA timing */
189 .pixclock = KHZ2PICOS(25175),
196 .sync = FB_SYNC_CLK_LAT_FALL,
199 /* Emerging ETV570 640 x 480 display. Syncs low active,
200 * DE high active, 115.2 mm x 86.4 mm display area
201 * VGA compatible timing
207 .pixclock = KHZ2PICOS(25175),
214 .sync = FB_SYNC_CLK_LAT_FALL,
217 /* Emerging ET0350G0DH6 320 x 240 display.
218 * 70.08 mm x 52.56 mm display area.
224 .pixclock = KHZ2PICOS(6500),
225 .left_margin = 68 - 34,
228 .upper_margin = 18 - 3,
231 .sync = FB_SYNC_CLK_LAT_FALL,
234 /* Emerging ET0430G0DH6 480 x 272 display.
235 * 95.04 mm x 53.856 mm display area.
241 .pixclock = KHZ2PICOS(9000),
250 /* Emerging ET0500G0DH6 800 x 480 display.
251 * 109.6 mm x 66.4 mm display area.
257 .pixclock = KHZ2PICOS(33260),
258 .left_margin = 216 - 128,
260 .right_margin = 1056 - 800 - 216,
261 .upper_margin = 35 - 2,
263 .lower_margin = 525 - 480 - 35,
264 .sync = FB_SYNC_CLK_LAT_FALL,
267 /* Emerging ETQ570G0DH6 320 x 240 display.
268 * 115.2 mm x 86.4 mm display area.
274 .pixclock = KHZ2PICOS(6400),
278 .upper_margin = 16, /* 15 according to datasheet */
279 .vsync_len = 3, /* TVP -> 1>x>5 */
280 .lower_margin = 4, /* 4.5 according to datasheet */
281 .sync = FB_SYNC_CLK_LAT_FALL,
284 /* Emerging ET0700G0DH6 800 x 480 display.
285 * 152.4 mm x 91.44 mm display area.
291 .pixclock = KHZ2PICOS(33260),
292 .left_margin = 216 - 128,
294 .right_margin = 1056 - 800 - 216,
295 .upper_margin = 35 - 2,
297 .lower_margin = 525 - 480 - 35,
298 .sync = FB_SYNC_CLK_LAT_FALL,
301 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
309 .sync = FB_SYNC_CLK_LAT_FALL,
313 void *lcd_base; /* Start of framebuffer memory */
314 void *lcd_console_address; /* Start of console buffer */
322 static int lcd_enabled = 1;
323 static int lcd_bl_polarity;
325 static int lcd_backlight_polarity(void)
327 return lcd_bl_polarity;
330 void lcd_initcolregs(void)
334 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
338 void lcd_enable(void)
341 * global variable from common/lcd.c
342 * Set to 0 here to prevent messages from going to LCD
343 * rather than serial console
348 karo_load_splashimage(1);
350 debug("Switching LCD on\n");
351 gpio_set_value(TX48_LCD_PWR_GPIO, 1);
353 gpio_set_value(TX48_LCD_RST_GPIO, 1);
355 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
356 lcd_backlight_polarity());
360 void lcd_disable(void)
363 printf("Disabling LCD\n");
369 static void tx48_lcd_panel_setup(struct da8xx_panel *p,
370 struct fb_videomode *fb)
372 p->pxl_clk = PICOS2KHZ(fb->pixclock) * 1000;
375 p->hbp = fb->left_margin;
376 p->hsw = fb->hsync_len;
377 p->hfp = fb->right_margin;
379 p->height = fb->yres;
380 p->vbp = fb->upper_margin;
381 p->vsw = fb->vsync_len;
382 p->vfp = fb->lower_margin;
384 p->invert_pxl_clk = !!(fb->sync & FB_SYNC_CLK_LAT_FALL);
387 void lcd_panel_disable(void)
390 debug("Switching LCD off\n");
391 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
392 !lcd_backlight_polarity());
393 gpio_set_value(TX48_LCD_PWR_GPIO, 0);
394 gpio_set_value(TX48_LCD_RST_GPIO, 0);
398 void lcd_ctrl_init(void *lcdbase)
400 int color_depth = 24;
401 const char *video_mode = karo_get_vmode(getenv("video_mode"));
405 struct fb_videomode *p = &tx48_fb_modes[0];
406 struct fb_videomode fb_mode;
407 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
410 debug("LCD disabled\n");
414 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
415 debug("Disabling LCD\n");
417 setenv("splashimage", NULL);
423 if (video_mode == NULL) {
424 debug("Disabling LCD\n");
429 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
431 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
433 debug("Using video mode from FDT\n");
435 if (fb_mode.xres > panel_info.vl_col ||
436 fb_mode.yres > panel_info.vl_row) {
437 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
438 fb_mode.xres, fb_mode.yres,
439 panel_info.vl_col, panel_info.vl_row);
445 debug("Trying compiled-in video modes\n");
446 while (p->name != NULL) {
447 if (strcmp(p->name, vm) == 0) {
448 debug("Using video mode: '%s'\n", p->name);
455 debug("Trying to decode video_mode: '%s'\n", vm);
456 while (*vm != '\0') {
457 if (*vm >= '0' && *vm <= '9') {
460 val = simple_strtoul(vm, &end, 0);
463 if (val > panel_info.vl_col)
464 val = panel_info.vl_col;
466 panel_info.vl_col = val;
468 } else if (!yres_set) {
469 if (val > panel_info.vl_row)
470 val = panel_info.vl_row;
472 panel_info.vl_row = val;
474 } else if (!bpp_set) {
483 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
484 end - vm, vm, color_depth);
487 } else if (!refresh_set) {
514 if (p->xres == 0 || p->yres == 0) {
515 printf("Invalid video mode: %s\n", getenv("video_mode"));
517 printf("Supported video modes are:");
518 for (p = &tx48_fb_modes[0]; p->name != NULL; p++) {
519 printf(" %s", p->name);
524 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
525 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
526 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
530 panel_info.vl_col = p->xres;
531 panel_info.vl_row = p->yres;
533 switch (color_depth) {
535 panel_info.vl_bpix = LCD_COLOR8;
538 panel_info.vl_bpix = LCD_COLOR16;
541 panel_info.vl_bpix = LCD_COLOR32;
544 p->pixclock = KHZ2PICOS(refresh *
545 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
546 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
548 debug("Pixel clock set to %lu.%03lu MHz\n",
549 PICOS2KHZ(p->pixclock) / 1000,
550 PICOS2KHZ(p->pixclock) % 1000);
555 debug("Creating new display-timing node from '%s'\n",
557 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
559 printf("Failed to create new display-timing node from '%s': %d\n",
563 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
564 tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
566 if (karo_load_splashimage(0) == 0) {
567 struct da8xx_panel da8xx_panel = { };
569 debug("Initializing FB driver\n");
570 tx48_lcd_panel_setup(&da8xx_panel, p);
571 da8xx_video_init(&da8xx_panel, &lcd_cfg, color_depth);
573 debug("Initializing LCD controller\n");
576 debug("Skipping initialization of LCD controller\n");
580 #define lcd_enabled 0
581 #endif /* CONFIG_LCD */
583 static void stk5_board_init(void)
585 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
586 tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
589 static void stk5v3_board_init(void)
594 static void stk5v5_board_init(void)
598 gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
599 tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
602 /* called with default environment! */
607 /* mach type passed to kernel */
608 #ifdef CONFIG_OF_LIBFDT
609 gd->bd->bi_arch_number = -1;
611 /* address of boot parameters */
612 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
614 if (ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
615 if (prm_rstst & PRM_RSTST_WDT1_RST)
616 printf("WDOG RESET detected\n");
618 printf("<CTRL-C> detected; safeboot enabled\n");
621 gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
622 tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_pads));
624 for (i = 0; i < ARRAY_SIZE(tx48_gpios); i++) {
625 int gpio = tx48_gpios[i].gpio;
627 if (gpio_get_value(gpio) == 0)
628 gpio_direction_output(gpio, 1);
631 tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_i2c_pads));
635 static void show_reset_cause(u32 prm_rstst)
637 const char *dlm = "";
639 printf("RESET cause: ");
640 if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
641 printf("%sPOR", dlm);
644 if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
648 if (prm_rstst & PRM_RSTST_WDT1_RST) {
649 printf("%sWATCHDOG", dlm);
652 if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
653 printf("%sWARM", dlm);
656 if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
657 printf("%sJTAG", dlm);
666 /* called with default environment! */
669 prm_rstst = readl(PRM_RSTST);
670 show_reset_cause(prm_rstst);
672 printf("Board: Ka-Ro TX48-7020\n");
678 static void tx48_set_cpu_clock(void)
680 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
681 unsigned long act_cpu_clk;
683 if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000)
686 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
687 printf("%s detected; skipping cpu clock change\n",
688 (prm_rstst & PRM_RSTST_WDT1_RST) ?
689 "WDOG RESET" : "<CTRL-C>");
693 mpu_pll_config_val(cpu_clk);
695 act_cpu_clk = mpu_clk_rate();
696 if (cpu_clk * 1000000 != act_cpu_clk) {
697 printf("Failed to set CPU clock to %lu MHz; using %lu.%03lu MHz instead\n",
698 cpu_clk, act_cpu_clk / 1000000,
699 act_cpu_clk / 1000 % 1000);
701 printf("CPU clock set to %lu.%03lu MHz\n",
702 act_cpu_clk / 1000000, act_cpu_clk / 1000 % 1000);
706 static void tx48_init_mac(void)
708 uint8_t mac_addr[ETH_ALEN];
709 uint32_t mac_hi, mac_lo;
711 /* try reading mac address from efuse */
712 mac_lo = __raw_readl(MAC_ID0_LO);
713 mac_hi = __raw_readl(MAC_ID0_HI);
715 mac_addr[0] = mac_hi & 0xFF;
716 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
717 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
718 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
719 mac_addr[4] = mac_lo & 0xFF;
720 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
722 if (!is_valid_ethaddr(mac_addr)) {
723 printf("No valid MAC address programmed\n");
726 printf("MAC addr from fuse: %pM\n", mac_addr);
727 eth_setenv_enetaddr("ethaddr", mac_addr);
730 /* called with environment from NAND or MMC */
731 int board_late_init(void)
734 const char *baseboard;
738 tx48_set_cpu_clock();
741 setenv_ulong("safeboot", 1);
742 else if (prm_rstst & PRM_RSTST_WDT1_RST)
743 setenv_ulong("wdreset", 1);
747 baseboard = getenv("baseboard");
751 if (strncmp(baseboard, "stk5", 4) == 0) {
752 printf("Baseboard: %s\n", baseboard);
753 if ((strlen(baseboard) == 4) ||
754 strcmp(baseboard, "stk5-v3") == 0) {
756 } else if (strcmp(baseboard, "stk5-v5") == 0) {
759 printf("WARNING: Unsupported STK5 board rev.: %s\n",
763 printf("WARNING: Unsupported baseboard: '%s'\n",
774 #ifdef CONFIG_DRIVER_TI_CPSW
775 static void tx48_phy_init(void)
777 debug("%s: Resetting ethernet PHY\n", __func__);
779 gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
784 gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
786 /* Wait for PHY internal POR signal to deassert */
790 static void cpsw_control(int enabled)
792 /* nothing for now */
793 /* TODO : VTP was here before */
796 static struct cpsw_slave_data cpsw_slaves[] = {
798 .slave_reg_ofs = 0x208,
799 .sliver_reg_ofs = 0xd80,
801 .phy_if = PHY_INTERFACE_MODE_RMII,
807 /* Nothing to be done here */
810 static struct cpsw_platform_data cpsw_data = {
811 .mdio_base = CPSW_MDIO_BASE,
812 .cpsw_base = CPSW_BASE,
815 .cpdma_reg_ofs = 0x800,
816 .slaves = ARRAY_SIZE(cpsw_slaves),
817 .slave_data = cpsw_slaves,
818 .ale_reg_ofs = 0xd00,
820 .host_port_reg_ofs = 0x108,
821 .hw_stats_reg_ofs = 0x900,
822 .mac_control = (1 << 5) /* MIIEN */,
823 .control = cpsw_control,
825 .version = CPSW_CTRL_VERSION_2,
828 int board_eth_init(bd_t *bis)
830 __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
832 return cpsw_register(&cpsw_data);
834 #endif /* CONFIG_DRIVER_TI_CPSW */
836 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
837 int cpu_mmc_init(bd_t *bis)
839 return omap_mmc_init(1, 0, 0, TX48_MMC_CD_GPIO, -1);
843 void tx48_disable_watchdog(void)
845 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
847 while (readl(&wdtimer->wdtwwps) & (1 << 4))
849 writel(0xaaaa, &wdtimer->wdtwspr);
850 while (readl(&wdtimer->wdtwwps) & (1 << 4))
852 writel(0x5555, &wdtimer->wdtwspr);
861 void show_activity(int arg)
863 static int led_state = LED_STATE_INIT;
866 if (led_state == LED_STATE_INIT) {
868 gpio_set_value(TX48_LED_GPIO, 1);
869 led_state = LED_STATE_ON;
871 if (get_timer(last) > CONFIG_SYS_HZ) {
873 if (led_state == LED_STATE_ON) {
874 gpio_set_value(TX48_LED_GPIO, 0);
876 gpio_set_value(TX48_LED_GPIO, 1);
878 led_state = 1 - led_state;
883 #ifdef CONFIG_OF_BOARD_SETUP
884 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
885 #include <jffs2/jffs2.h>
886 #include <mtd_node.h>
887 static struct node_info nodes[] = {
888 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
889 { "ti,am3352-gpmc", MTD_DEV_TYPE_NAND, },
893 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
894 #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
896 static const char *tx48_touchpanels[] = {
902 int ft_board_setup(void *blob, bd_t *bd)
904 const char *baseboard = getenv("baseboard");
905 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
906 const char *video_mode = karo_get_vmode(getenv("video_mode"));
909 ret = fdt_increase_size(blob, 4096);
911 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
914 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
915 fdt_fixup_ethernet(blob);
917 karo_fdt_fixup_touchpanel(blob, tx48_touchpanels,
918 ARRAY_SIZE(tx48_touchpanels));
919 karo_fdt_fixup_usb_otg(blob, "usb0", "phys", "vcc-supply");
920 karo_fdt_fixup_flexcan(blob, stk5_v5);
922 karo_fdt_update_fb_mode(blob, video_mode);
924 tx48_disable_watchdog();
926 if (get_cpu_rev() == 0) {
927 karo_fdt_del_prop(blob, "lltc,ltc3589-2", 0x34, "interrupts");
928 karo_fdt_del_prop(blob, "lltc,ltc3589-2", 0x34,
934 #endif /* CONFIG_OF_BOARD_SETUP */