karo: tx48: only print message about cpu_clk, if it was actually changed
[karo-tx-uboot.git] / board / karo / tx48 / tx48.c
1 /*
2  * Copyright (C) 2012-2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * based on evm.c
5  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
16
17 #include <common.h>
18 #include <errno.h>
19 #include <miiphy.h>
20 #include <netdev.h>
21 #include <serial.h>
22 #include <libfdt.h>
23 #include <lcd.h>
24 #include <fdt_support.h>
25 #include <nand.h>
26 #include <net.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/fb.h>
29 #include <asm/gpio.h>
30 #include <asm/cache.h>
31 #include <asm/omap_common.h>
32 #include <asm/io.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/hardware.h>
35 #include <asm/arch/mmc_host_def.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/clock.h>
38 #include <video_fb.h>
39 #include <asm/arch/da8xx-fb.h>
40
41 #include "../common/karo.h"
42
43 DECLARE_GLOBAL_DATA_PTR;
44
45 #define TX48_LED_GPIO           AM33XX_GPIO_NR(1, 26)
46 #define TX48_ETH_PHY_RST_GPIO   AM33XX_GPIO_NR(3, 8)
47 #define TX48_LCD_RST_GPIO       AM33XX_GPIO_NR(1, 19)
48 #define TX48_LCD_PWR_GPIO       AM33XX_GPIO_NR(1, 22)
49 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
50 #define TX48_MMC_CD_GPIO        AM33XX_GPIO_NR(3, 15)
51
52 #define GMII_SEL                (CTRL_BASE + 0x650)
53
54 /* UART Defines */
55 #define UART_SYSCFG_OFFSET      0x54
56 #define UART_SYSSTS_OFFSET      0x58
57
58 #define UART_RESET              (0x1 << 1)
59 #define UART_CLK_RUNNING_MASK   0x1
60 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
61
62 /* Timer Defines */
63 #define TSICR_REG               0x54
64 #define TIOCP_CFG_REG           0x10
65 #define TCLR_REG                0x38
66
67 /* RGMII mode define */
68 #define RGMII_MODE_ENABLE       0xA
69 #define RMII_MODE_ENABLE        0x5
70 #define MII_MODE_ENABLE         0x0
71
72 #define NO_OF_MAC_ADDR          1
73 #define ETH_ALEN                6
74
75 /* PAD Control Fields */
76 #define SLEWCTRL        (0x1 << 6)
77 #define RXACTIVE        (0x1 << 5)
78 #define PULLUP_EN       (0x1 << 4) /* Pull UP Selection */
79 #define PULLUDEN        (0x0 << 3) /* Pull up enabled */
80 #define PULLUDDIS       (0x1 << 3) /* Pull up disabled */
81 #define MODE(val)       (val)
82
83 /*
84  * PAD CONTROL OFFSETS
85  * Field names corresponds to the pad signal name
86  */
87 struct pad_signals {
88         int gpmc_ad0;
89         int gpmc_ad1;
90         int gpmc_ad2;
91         int gpmc_ad3;
92         int gpmc_ad4;
93         int gpmc_ad5;
94         int gpmc_ad6;
95         int gpmc_ad7;
96         int gpmc_ad8;
97         int gpmc_ad9;
98         int gpmc_ad10;
99         int gpmc_ad11;
100         int gpmc_ad12;
101         int gpmc_ad13;
102         int gpmc_ad14;
103         int gpmc_ad15;
104         int gpmc_a0;
105         int gpmc_a1;
106         int gpmc_a2;
107         int gpmc_a3;
108         int gpmc_a4;
109         int gpmc_a5;
110         int gpmc_a6;
111         int gpmc_a7;
112         int gpmc_a8;
113         int gpmc_a9;
114         int gpmc_a10;
115         int gpmc_a11;
116         int gpmc_wait0;
117         int gpmc_wpn;
118         int gpmc_be1n;
119         int gpmc_csn0;
120         int gpmc_csn1;
121         int gpmc_csn2;
122         int gpmc_csn3;
123         int gpmc_clk;
124         int gpmc_advn_ale;
125         int gpmc_oen_ren;
126         int gpmc_wen;
127         int gpmc_be0n_cle;
128         int lcd_data0;
129         int lcd_data1;
130         int lcd_data2;
131         int lcd_data3;
132         int lcd_data4;
133         int lcd_data5;
134         int lcd_data6;
135         int lcd_data7;
136         int lcd_data8;
137         int lcd_data9;
138         int lcd_data10;
139         int lcd_data11;
140         int lcd_data12;
141         int lcd_data13;
142         int lcd_data14;
143         int lcd_data15;
144         int lcd_vsync;
145         int lcd_hsync;
146         int lcd_pclk;
147         int lcd_ac_bias_en;
148         int mmc0_dat3;
149         int mmc0_dat2;
150         int mmc0_dat1;
151         int mmc0_dat0;
152         int mmc0_clk;
153         int mmc0_cmd;
154         int mii1_col;
155         int mii1_crs;
156         int mii1_rxerr;
157         int mii1_txen;
158         int mii1_rxdv;
159         int mii1_txd3;
160         int mii1_txd2;
161         int mii1_txd1;
162         int mii1_txd0;
163         int mii1_txclk;
164         int mii1_rxclk;
165         int mii1_rxd3;
166         int mii1_rxd2;
167         int mii1_rxd1;
168         int mii1_rxd0;
169         int rmii1_refclk;
170         int mdio_data;
171         int mdio_clk;
172         int spi0_sclk;
173         int spi0_d0;
174         int spi0_d1;
175         int spi0_cs0;
176         int spi0_cs1;
177         int ecap0_in_pwm0_out;
178         int uart0_ctsn;
179         int uart0_rtsn;
180         int uart0_rxd;
181         int uart0_txd;
182         int uart1_ctsn;
183         int uart1_rtsn;
184         int uart1_rxd;
185         int uart1_txd;
186         int i2c0_sda;
187         int i2c0_scl;
188         int mcasp0_aclkx;
189         int mcasp0_fsx;
190         int mcasp0_axr0;
191         int mcasp0_ahclkr;
192         int mcasp0_aclkr;
193         int mcasp0_fsr;
194         int mcasp0_axr1;
195         int mcasp0_ahclkx;
196         int xdma_event_intr0;
197         int xdma_event_intr1;
198         int nresetin_out;
199         int porz;
200         int nnmi;
201         int osc0_in;
202         int osc0_out;
203         int rsvd1;
204         int tms;
205         int tdi;
206         int tdo;
207         int tck;
208         int ntrst;
209         int emu0;
210         int emu1;
211         int osc1_in;
212         int osc1_out;
213         int pmic_power_en;
214         int rtc_porz;
215         int rsvd2;
216         int ext_wakeup;
217         int enz_kaldo_1p8v;
218         int usb0_dm;
219         int usb0_dp;
220         int usb0_ce;
221         int usb0_id;
222         int usb0_vbus;
223         int usb0_drvvbus;
224         int usb1_dm;
225         int usb1_dp;
226         int usb1_ce;
227         int usb1_id;
228         int usb1_vbus;
229         int usb1_drvvbus;
230         int ddr_resetn;
231         int ddr_csn0;
232         int ddr_cke;
233         int ddr_ck;
234         int ddr_nck;
235         int ddr_casn;
236         int ddr_rasn;
237         int ddr_wen;
238         int ddr_ba0;
239         int ddr_ba1;
240         int ddr_ba2;
241         int ddr_a0;
242         int ddr_a1;
243         int ddr_a2;
244         int ddr_a3;
245         int ddr_a4;
246         int ddr_a5;
247         int ddr_a6;
248         int ddr_a7;
249         int ddr_a8;
250         int ddr_a9;
251         int ddr_a10;
252         int ddr_a11;
253         int ddr_a12;
254         int ddr_a13;
255         int ddr_a14;
256         int ddr_a15;
257         int ddr_odt;
258         int ddr_d0;
259         int ddr_d1;
260         int ddr_d2;
261         int ddr_d3;
262         int ddr_d4;
263         int ddr_d5;
264         int ddr_d6;
265         int ddr_d7;
266         int ddr_d8;
267         int ddr_d9;
268         int ddr_d10;
269         int ddr_d11;
270         int ddr_d12;
271         int ddr_d13;
272         int ddr_d14;
273         int ddr_d15;
274         int ddr_dqm0;
275         int ddr_dqm1;
276         int ddr_dqs0;
277         int ddr_dqsn0;
278         int ddr_dqs1;
279         int ddr_dqsn1;
280         int ddr_vref;
281         int ddr_vtp;
282         int ddr_strben0;
283         int ddr_strben1;
284         int ain7;
285         int ain6;
286         int ain5;
287         int ain4;
288         int ain3;
289         int ain2;
290         int ain1;
291         int ain0;
292         int vrefp;
293         int vrefn;
294 };
295
296 struct pin_mux {
297         short reg_offset;
298         uint8_t val;
299 };
300
301 #define PAD_CTRL_BASE   0x800
302 #define OFFSET(x)       (unsigned int) (&((struct pad_signals *) \
303                                 (PAD_CTRL_BASE))->x)
304
305 /*
306  * Configure the pin mux for the module
307  */
308 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
309                         int num_pins)
310 {
311         int i;
312
313         for (i = 0; i < num_pins; i++)
314                 writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
315 }
316
317 #define PRM_RSTST_GLOBAL_COLD_RST       (1 << 0)
318 #define PRM_RSTST_GLOBAL_WARM_SW_RST    (1 << 1)
319 #define PRM_RSTST_WDT1_RST              (1 << 4)
320 #define PRM_RSTST_EXTERNAL_WARM_RST     (1 << 5)
321 #define PRM_RSTST_ICEPICK_RST           (1 << 9)
322
323 static u32 prm_rstst __attribute__((section(".data")));
324
325 /*
326  * Basic board specific setup
327  */
328 static const struct pin_mux stk5_pads[] = {
329         /* heartbeat LED */
330         { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
331         /* LCD RESET */
332         { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
333         /* LCD POWER_ENABLE */
334         { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
335         /* LCD Backlight (PWM) */
336         { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
337         /* MMC CD */
338         { OFFSET(mcasp0_fsx), MODE(7) | PULLUDEN | PULLUP_EN, },
339 };
340
341 static const struct gpio stk5_gpios[] = {
342         { TX48_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
343         { TX48_MMC_CD_GPIO, GPIOF_INPUT, "MMC0 CD", },
344 };
345
346 static const struct pin_mux stk5_lcd_pads[] = {
347         /* LCD data bus */
348         { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
349         { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
350         { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
351         { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
352         { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
353         { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
354         { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
355         { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
356         { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
357         { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
358         { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
359         { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
360         { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
361         { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
362         { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
363         { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
364         /* LCD control signals */
365         { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
366         { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
367         { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
368         { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
369 };
370
371 static const struct gpio stk5_lcd_gpios[] = {
372         { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
373         { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
374         { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
375 };
376
377 static const struct pin_mux stk5v5_pads[] = {
378         /* CAN transceiver control */
379         { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
380 };
381
382 static const struct gpio stk5v5_gpios[] = {
383         { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", },
384 };
385
386 #ifdef CONFIG_LCD
387 static u16 tx48_cmap[256];
388 vidinfo_t panel_info = {
389         /* set to max. size supported by SoC */
390         .vl_col = 1366,
391         .vl_row = 768,
392
393         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
394         .cmap = tx48_cmap,
395 };
396
397 #define FB_SYNC_OE_LOW_ACT      (1 << 31)
398 #define FB_SYNC_CLK_LAT_FALL    (1 << 30)
399
400 static struct fb_videomode tx48_fb_modes[] = {
401         {
402                 /* Standard VGA timing */
403                 .name           = "VGA",
404                 .refresh        = 60,
405                 .xres           = 640,
406                 .yres           = 480,
407                 .pixclock       = KHZ2PICOS(25175),
408                 .left_margin    = 48,
409                 .hsync_len      = 96,
410                 .right_margin   = 16,
411                 .upper_margin   = 31,
412                 .vsync_len      = 2,
413                 .lower_margin   = 12,
414                 .sync           = FB_SYNC_CLK_LAT_FALL,
415         },
416         {
417                 /* Emerging ETV570 640 x 480 display. Syncs low active,
418                  * DE high active, 115.2 mm x 86.4 mm display area
419                  * VGA compatible timing
420                  */
421                 .name           = "ETV570",
422                 .refresh        = 60,
423                 .xres           = 640,
424                 .yres           = 480,
425                 .pixclock       = KHZ2PICOS(25175),
426                 .left_margin    = 114,
427                 .hsync_len      = 30,
428                 .right_margin   = 16,
429                 .upper_margin   = 32,
430                 .vsync_len      = 3,
431                 .lower_margin   = 10,
432                 .sync           = FB_SYNC_CLK_LAT_FALL,
433         },
434         {
435                 /* Emerging ET0350G0DH6 320 x 240 display.
436                  * 70.08 mm x 52.56 mm display area.
437                  */
438                 .name           = "ET0350",
439                 .refresh        = 60,
440                 .xres           = 320,
441                 .yres           = 240,
442                 .pixclock       = KHZ2PICOS(6500),
443                 .left_margin    = 68 - 34,
444                 .hsync_len      = 34,
445                 .right_margin   = 20,
446                 .upper_margin   = 18 - 3,
447                 .vsync_len      = 3,
448                 .lower_margin   = 4,
449                 .sync           = FB_SYNC_CLK_LAT_FALL,
450         },
451         {
452                 /* Emerging ET0430G0DH6 480 x 272 display.
453                  * 95.04 mm x 53.856 mm display area.
454                  */
455                 .name           = "ET0430",
456                 .refresh        = 60,
457                 .xres           = 480,
458                 .yres           = 272,
459                 .pixclock       = KHZ2PICOS(9000),
460                 .left_margin    = 2,
461                 .hsync_len      = 41,
462                 .right_margin   = 2,
463                 .upper_margin   = 2,
464                 .vsync_len      = 10,
465                 .lower_margin   = 2,
466         },
467         {
468                 /* Emerging ET0500G0DH6 800 x 480 display.
469                  * 109.6 mm x 66.4 mm display area.
470                  */
471                 .name           = "ET0500",
472                 .refresh        = 60,
473                 .xres           = 800,
474                 .yres           = 480,
475                 .pixclock       = KHZ2PICOS(33260),
476                 .left_margin    = 216 - 128,
477                 .hsync_len      = 128,
478                 .right_margin   = 1056 - 800 - 216,
479                 .upper_margin   = 35 - 2,
480                 .vsync_len      = 2,
481                 .lower_margin   = 525 - 480 - 35,
482                 .sync           = FB_SYNC_CLK_LAT_FALL,
483         },
484         {
485                 /* Emerging ETQ570G0DH6 320 x 240 display.
486                  * 115.2 mm x 86.4 mm display area.
487                  */
488                 .name           = "ETQ570",
489                 .refresh        = 60,
490                 .xres           = 320,
491                 .yres           = 240,
492                 .pixclock       = KHZ2PICOS(6400),
493                 .left_margin    = 38,
494                 .hsync_len      = 30,
495                 .right_margin   = 30,
496                 .upper_margin   = 16, /* 15 according to datasheet */
497                 .vsync_len      = 3, /* TVP -> 1>x>5 */
498                 .lower_margin   = 4, /* 4.5 according to datasheet */
499                 .sync           = FB_SYNC_CLK_LAT_FALL,
500         },
501         {
502                 /* Emerging ET0700G0DH6 800 x 480 display.
503                  * 152.4 mm x 91.44 mm display area.
504                  */
505                 .name           = "ET0700",
506                 .refresh        = 60,
507                 .xres           = 800,
508                 .yres           = 480,
509                 .pixclock       = KHZ2PICOS(33260),
510                 .left_margin    = 216 - 128,
511                 .hsync_len      = 128,
512                 .right_margin   = 1056 - 800 - 216,
513                 .upper_margin   = 35 - 2,
514                 .vsync_len      = 2,
515                 .lower_margin   = 525 - 480 - 35,
516                 .sync           = FB_SYNC_CLK_LAT_FALL,
517         },
518         {
519                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
520                 .refresh        = 60,
521                 .left_margin    = 48,
522                 .hsync_len      = 96,
523                 .right_margin   = 16,
524                 .upper_margin   = 31,
525                 .vsync_len      = 2,
526                 .lower_margin   = 12,
527                 .sync           = FB_SYNC_CLK_LAT_FALL,
528         },
529 };
530
531 void *lcd_base;                 /* Start of framebuffer memory  */
532 void *lcd_console_address;      /* Start of console buffer      */
533
534 int lcd_color_fg;
535 int lcd_color_bg;
536
537 short console_col;
538 short console_row;
539
540 static int lcd_enabled = 1;
541 static int lcd_bl_polarity;
542
543 static int lcd_backlight_polarity(void)
544 {
545         return lcd_bl_polarity;
546 }
547
548 void lcd_initcolregs(void)
549 {
550 }
551
552 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
553 {
554 }
555
556 void lcd_enable(void)
557 {
558         /* HACK ALERT:
559          * global variable from common/lcd.c
560          * Set to 0 here to prevent messages from going to LCD
561          * rather than serial console
562          */
563         lcd_is_enabled = 0;
564
565         if (lcd_enabled) {
566                 karo_load_splashimage(1);
567
568                 debug("Switching LCD on\n");
569                 gpio_set_value(TX48_LCD_PWR_GPIO, 1);
570                 udelay(100);
571                 gpio_set_value(TX48_LCD_RST_GPIO, 1);
572                 udelay(300000);
573                 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
574                         lcd_backlight_polarity());
575         }
576 }
577
578 void lcd_disable(void)
579 {
580         if (lcd_enabled) {
581                 printf("Disabling LCD\n");
582                 da8xx_fb_disable();
583                 lcd_enabled = 0;
584         }
585 }
586
587 static void tx48_lcd_panel_setup(struct da8xx_panel *p,
588                                 struct fb_videomode *fb)
589 {
590         p->pxl_clk = PICOS2KHZ(fb->pixclock) * 1000;
591
592         p->width = fb->xres;
593         p->hbp = fb->left_margin;
594         p->hsw = fb->hsync_len;
595         p->hfp = fb->right_margin;
596
597         p->height = fb->yres;
598         p->vbp = fb->upper_margin;
599         p->vsw = fb->vsync_len;
600         p->vfp = fb->lower_margin;
601
602         p->invert_pxl_clk = !!(fb->sync & FB_SYNC_CLK_LAT_FALL);
603 }
604
605 void lcd_panel_disable(void)
606 {
607         if (lcd_enabled) {
608                 debug("Switching LCD off\n");
609                 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
610                         !lcd_backlight_polarity());
611                 gpio_set_value(TX48_LCD_PWR_GPIO, 0);
612                 gpio_set_value(TX48_LCD_RST_GPIO, 0);
613         }
614 }
615
616 void lcd_ctrl_init(void *lcdbase)
617 {
618         int color_depth = 24;
619         const char *video_mode = karo_get_vmode(getenv("video_mode"));
620         const char *vm;
621         unsigned long val;
622         int refresh = 60;
623         struct fb_videomode *p = &tx48_fb_modes[0];
624         struct fb_videomode fb_mode;
625         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
626
627         if (!lcd_enabled) {
628                 debug("LCD disabled\n");
629                 return;
630         }
631
632         if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
633                 debug("Disabling LCD\n");
634                 lcd_enabled = 0;
635                 setenv("splashimage", NULL);
636                 return;
637         }
638
639         karo_fdt_move_fdt();
640         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
641
642         if (video_mode == NULL) {
643                 debug("Disabling LCD\n");
644                 lcd_enabled = 0;
645                 return;
646         }
647         vm = video_mode;
648         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
649                 p = &fb_mode;
650                 debug("Using video mode from FDT\n");
651                 vm += strlen(vm);
652                 if (fb_mode.xres > panel_info.vl_col ||
653                         fb_mode.yres > panel_info.vl_row) {
654                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
655                                 fb_mode.xres, fb_mode.yres,
656                                 panel_info.vl_col, panel_info.vl_row);
657                         lcd_enabled = 0;
658                         return;
659                 }
660         }
661         if (p->name != NULL)
662                 debug("Trying compiled-in video modes\n");
663         while (p->name != NULL) {
664                 if (strcmp(p->name, vm) == 0) {
665                         debug("Using video mode: '%s'\n", p->name);
666                         vm += strlen(vm);
667                         break;
668                 }
669                 p++;
670         }
671         if (*vm != '\0')
672                 debug("Trying to decode video_mode: '%s'\n", vm);
673         while (*vm != '\0') {
674                 if (*vm >= '0' && *vm <= '9') {
675                         char *end;
676
677                         val = simple_strtoul(vm, &end, 0);
678                         if (end > vm) {
679                                 if (!xres_set) {
680                                         if (val > panel_info.vl_col)
681                                                 val = panel_info.vl_col;
682                                         p->xres = val;
683                                         panel_info.vl_col = val;
684                                         xres_set = 1;
685                                 } else if (!yres_set) {
686                                         if (val > panel_info.vl_row)
687                                                 val = panel_info.vl_row;
688                                         p->yres = val;
689                                         panel_info.vl_row = val;
690                                         yres_set = 1;
691                                 } else if (!bpp_set) {
692                                         switch (val) {
693                                         case 24:
694                                         case 16:
695                                         case 8:
696                                                 color_depth = val;
697                                                 break;
698
699                                         default:
700                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
701                                                         end - vm, vm, color_depth);
702                                         }
703                                         bpp_set = 1;
704                                 } else if (!refresh_set) {
705                                         refresh = val;
706                                         refresh_set = 1;
707                                 }
708                         }
709                         vm = end;
710                 }
711                 switch (*vm) {
712                 case '@':
713                         bpp_set = 1;
714                         /* fallthru */
715                 case '-':
716                         yres_set = 1;
717                         /* fallthru */
718                 case 'x':
719                         xres_set = 1;
720                         /* fallthru */
721                 case 'M':
722                 case 'R':
723                         vm++;
724                         break;
725
726                 default:
727                         if (*vm != '\0')
728                                 vm++;
729                 }
730         }
731         if (p->xres == 0 || p->yres == 0) {
732                 printf("Invalid video mode: %s\n", getenv("video_mode"));
733                 lcd_enabled = 0;
734                 printf("Supported video modes are:");
735                 for (p = &tx48_fb_modes[0]; p->name != NULL; p++) {
736                         printf(" %s", p->name);
737                 }
738                 printf("\n");
739                 return;
740         }
741         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
742                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
743                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
744                 lcd_enabled = 0;
745                 return;
746         }
747         panel_info.vl_col = p->xres;
748         panel_info.vl_row = p->yres;
749
750         switch (color_depth) {
751         case 8:
752                 panel_info.vl_bpix = LCD_COLOR8;
753                 break;
754         case 16:
755                 panel_info.vl_bpix = LCD_COLOR16;
756                 break;
757         default:
758                 panel_info.vl_bpix = LCD_COLOR24;
759         }
760
761         p->pixclock = KHZ2PICOS(refresh *
762                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
763                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
764                 / 1000);
765         debug("Pixel clock set to %lu.%03lu MHz\n",
766                 PICOS2KHZ(p->pixclock) / 1000,
767                 PICOS2KHZ(p->pixclock) % 1000);
768
769         if (p != &fb_mode) {
770                 int ret;
771
772                 debug("Creating new display-timing node from '%s'\n",
773                         video_mode);
774                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
775                 if (ret)
776                         printf("Failed to create new display-timing node from '%s': %d\n",
777                                 video_mode, ret);
778         }
779
780         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
781         tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
782
783         if (karo_load_splashimage(0) == 0) {
784                 struct da8xx_panel da8xx_panel = { };
785
786                 debug("Initializing FB driver\n");
787                 tx48_lcd_panel_setup(&da8xx_panel, p);
788                 da8xx_video_init(&da8xx_panel, color_depth);
789
790                 debug("Initializing LCD controller\n");
791                 video_hw_init();
792         } else {
793                 debug("Skipping initialization of LCD controller\n");
794         }
795 }
796 #else
797 #define lcd_enabled 0
798 #endif /* CONFIG_LCD */
799
800 static void stk5_board_init(void)
801 {
802         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
803         tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
804 }
805
806 static void stk5v3_board_init(void)
807 {
808         stk5_board_init();
809 }
810
811 static void stk5v5_board_init(void)
812 {
813         stk5_board_init();
814
815         gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
816         tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
817 }
818
819 /* called with default environment! */
820 int board_init(void)
821 {
822         /* mach type passed to kernel */
823 #ifdef CONFIG_OF_LIBFDT
824         gd->bd->bi_arch_number = -1;
825 #endif
826         /* address of boot parameters */
827         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
828
829         if (ctrlc())
830                 printf("CTRL-C detected\n");
831
832         return 0;
833 }
834
835 static void show_reset_cause(u32 prm_rstst)
836 {
837         const char *dlm = "";
838
839         printf("RESET cause: ");
840         if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
841                 printf("%sPOR", dlm);
842                 dlm = " | ";
843         }
844         if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
845                 printf("%sSW", dlm);
846                 dlm = " | ";
847         }
848         if (prm_rstst & PRM_RSTST_WDT1_RST) {
849                 printf("%sWATCHDOG", dlm);
850                 dlm = " | ";
851         }
852         if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
853                 printf("%sWARM", dlm);
854                 dlm = " | ";
855         }
856         if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
857                 printf("%sJTAG", dlm);
858                 dlm = " | ";
859         }
860         if (*dlm == '\0')
861                 printf("unknown");
862
863         printf(" RESET\n");
864 }
865
866 /* called with default environment! */
867 int checkboard(void)
868 {
869         prm_rstst = readl(PRM_RSTST);
870         show_reset_cause(prm_rstst);
871
872         printf("Board: Ka-Ro TX48-7020\n");
873
874         timer_init();
875         return 0;
876 }
877
878 static void tx48_set_cpu_clock(void)
879 {
880         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
881         unsigned long act_cpu_clk;
882
883         if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000)
884                 return;
885
886         if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
887                 if (prm_rstst & PRM_RSTST_WDT1_RST) {
888                         printf("Watchdog reset detected; skipping cpu clock change\n");
889                 } else {
890                         printf("<CTRL-C> detected; skipping cpu clock change\n");
891                 }
892                 return;
893         }
894
895         mpu_pll_config_val(cpu_clk);
896
897         act_cpu_clk = mpu_clk_rate();
898         if (cpu_clk * 1000000 != act_cpu_clk) {
899                 printf("Failed to set CPU clock to %lu MHz; using %lu.%03lu MHz instead\n",
900                         cpu_clk, act_cpu_clk / 1000000,
901                         act_cpu_clk / 1000 % 1000);
902         } else {
903                 printf("CPU clock set to %lu.%03lu MHz\n",
904                         act_cpu_clk / 1000000, act_cpu_clk / 1000 % 1000);
905         }
906 }
907
908 static void tx48_init_mac(void)
909 {
910         uint8_t mac_addr[ETH_ALEN];
911         uint32_t mac_hi, mac_lo;
912
913         /* try reading mac address from efuse */
914         mac_lo = __raw_readl(MAC_ID0_LO);
915         mac_hi = __raw_readl(MAC_ID0_HI);
916
917         mac_addr[0] = mac_hi & 0xFF;
918         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
919         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
920         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
921         mac_addr[4] = mac_lo & 0xFF;
922         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
923
924         if (!is_valid_ether_addr(mac_addr)) {
925                 printf("No valid MAC address programmed\n");
926                 return;
927         }
928         printf("MAC addr from fuse: %pM\n", mac_addr);
929         eth_setenv_enetaddr("ethaddr", mac_addr);
930 }
931
932 /* called with environment from NAND or MMC */
933 int board_late_init(void)
934 {
935         int ret = 0;
936         const char *baseboard;
937
938         tx48_set_cpu_clock();
939         karo_fdt_move_fdt();
940
941         baseboard = getenv("baseboard");
942         if (!baseboard)
943                 goto exit;
944
945         if (strncmp(baseboard, "stk5", 4) == 0) {
946                 printf("Baseboard: %s\n", baseboard);
947                 if ((strlen(baseboard) == 4) ||
948                         strcmp(baseboard, "stk5-v3") == 0) {
949                         stk5v3_board_init();
950                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
951                         stk5v5_board_init();
952                 } else {
953                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
954                                 baseboard + 4);
955                 }
956         } else {
957                 printf("WARNING: Unsupported baseboard: '%s'\n",
958                         baseboard);
959                 ret = -EINVAL;
960         }
961
962 exit:
963         tx48_init_mac();
964         clear_ctrlc();
965         return ret;
966 }
967
968 #ifdef CONFIG_DRIVER_TI_CPSW
969 static void tx48_phy_init(char *name, int addr)
970 {
971         debug("%s: Resetting ethernet PHY\n", __func__);
972
973         gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
974
975         udelay(100);
976
977         /* Release nRST */
978         gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
979
980         /* Wait for PHY internal POR signal to deassert */
981         udelay(25000);
982 }
983
984 static void cpsw_control(int enabled)
985 {
986         /* nothing for now */
987         /* TODO : VTP was here before */
988 }
989
990 static struct cpsw_slave_data cpsw_slaves[] = {
991         {
992                 .slave_reg_ofs  = 0x208,
993                 .sliver_reg_ofs = 0xd80,
994                 .phy_id         = 0,
995                 .phy_if         = PHY_INTERFACE_MODE_RMII,
996         },
997 };
998
999 void s_init(void)
1000 {
1001         /* Nothing to be done here */
1002 }
1003
1004 static struct cpsw_platform_data cpsw_data = {
1005         .mdio_base              = CPSW_MDIO_BASE,
1006         .cpsw_base              = CPSW_BASE,
1007         .mdio_div               = 0xff,
1008         .channels               = 8,
1009         .cpdma_reg_ofs          = 0x800,
1010         .slaves                 = ARRAY_SIZE(cpsw_slaves),
1011         .slave_data             = cpsw_slaves,
1012         .ale_reg_ofs            = 0xd00,
1013         .ale_entries            = 1024,
1014         .host_port_reg_ofs      = 0x108,
1015         .hw_stats_reg_ofs       = 0x900,
1016         .mac_control            = (1 << 5) /* MIIEN */,
1017         .control                = cpsw_control,
1018         .phy_init               = tx48_phy_init,
1019         .gigabit_en             = 0,
1020         .host_port_num          = 0,
1021         .version                = CPSW_CTRL_VERSION_2,
1022 };
1023
1024 int board_eth_init(bd_t *bis)
1025 {
1026         __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
1027         __raw_writel(0x5D, GMII_SEL);
1028         return cpsw_register(&cpsw_data);
1029 }
1030 #endif /* CONFIG_DRIVER_TI_CPSW */
1031
1032 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
1033 int cpu_mmc_init(bd_t *bis)
1034 {
1035         return omap_mmc_init(1, 0, 0, TX48_MMC_CD_GPIO, -1);
1036 }
1037 #endif
1038
1039 void tx48_disable_watchdog(void)
1040 {
1041         struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
1042
1043         while (readl(&wdtimer->wdtwwps) & (1 << 4))
1044                 ;
1045         writel(0xaaaa, &wdtimer->wdtwspr);
1046         while (readl(&wdtimer->wdtwwps) & (1 << 4))
1047                 ;
1048         writel(0x5555, &wdtimer->wdtwspr);
1049 }
1050
1051 enum {
1052         LED_STATE_INIT = -1,
1053         LED_STATE_OFF,
1054         LED_STATE_ON,
1055 };
1056
1057 void show_activity(int arg)
1058 {
1059         static int led_state = LED_STATE_INIT;
1060         static ulong last;
1061
1062         if (led_state == LED_STATE_INIT) {
1063                 last = get_timer(0);
1064                 gpio_set_value(TX48_LED_GPIO, 1);
1065                 led_state = LED_STATE_ON;
1066         } else {
1067                 if (get_timer(last) > CONFIG_SYS_HZ) {
1068                         last = get_timer(0);
1069                         if (led_state == LED_STATE_ON) {
1070                                 gpio_set_value(TX48_LED_GPIO, 0);
1071                         } else {
1072                                 gpio_set_value(TX48_LED_GPIO, 1);
1073                         }
1074                         led_state = 1 - led_state;
1075                 }
1076         }
1077 }
1078
1079 #ifdef CONFIG_OF_BOARD_SETUP
1080 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1081 #include <jffs2/jffs2.h>
1082 #include <mtd_node.h>
1083 static struct node_info nodes[] = {
1084         { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
1085         { "ti,am3352-gpmc", MTD_DEV_TYPE_NAND, },
1086 };
1087
1088 #else
1089 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1090 #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
1091
1092 static const char *tx48_touchpanels[] = {
1093         "ti,tsc2007",
1094         "edt,edt-ft5x06",
1095         "ti,am3359-tscadc",
1096 };
1097
1098 void ft_board_setup(void *blob, bd_t *bd)
1099 {
1100         const char *baseboard = getenv("baseboard");
1101         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1102         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1103         int ret;
1104
1105         ret = fdt_increase_size(blob, 4096);
1106         if (ret)
1107                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1108
1109         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1110         fdt_fixup_ethernet(blob);
1111
1112         karo_fdt_fixup_touchpanel(blob, tx48_touchpanels,
1113                                 ARRAY_SIZE(tx48_touchpanels));
1114         karo_fdt_fixup_usb_otg(blob, "usb0", "phys", "vcc-supply");
1115         karo_fdt_fixup_flexcan(blob, stk5_v5);
1116
1117         karo_fdt_update_fb_mode(blob, video_mode);
1118
1119         tx48_disable_watchdog();
1120 }
1121 #endif /* CONFIG_OF_BOARD_SETUP */