3 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
6 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
25 #include <fdt_support.h>
28 #include <linux/mtd/nand.h>
30 #include <asm/cache.h>
31 #include <asm/omap_common.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/hardware.h>
35 #include <asm/arch/mmc_host_def.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/nand.h>
38 #include <asm/arch/clock.h>
39 #include <asm/arch/common_def.h>
41 #include <asm/arch/da8xx-fb.h>
43 #include "../common/karo.h"
45 DECLARE_GLOBAL_DATA_PTR;
47 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
48 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
49 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
50 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
51 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
53 #define GMII_SEL (CTRL_BASE + 0x650)
56 #define UART_SYSCFG_OFFSET 0x54
57 #define UART_SYSSTS_OFFSET 0x58
59 #define UART_RESET (0x1 << 1)
60 #define UART_CLK_RUNNING_MASK 0x1
61 #define UART_SMART_IDLE_EN (0x1 << 0x3)
64 #define TSICR_REG 0x54
65 #define TIOCP_CFG_REG 0x10
68 /* RGMII mode define */
69 #define RGMII_MODE_ENABLE 0xA
70 #define RMII_MODE_ENABLE 0x5
71 #define MII_MODE_ENABLE 0x0
73 #define NO_OF_MAC_ADDR 1
76 #define MUX_CFG(value, offset) { \
77 __raw_writel(value, (CTRL_BASE + (offset))); \
80 /* PAD Control Fields */
81 #define SLEWCTRL (0x1 << 6)
82 #define RXACTIVE (0x1 << 5)
83 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
84 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
85 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
86 #define MODE(val) (val)
90 * Field names corresponds to the pad signal name
182 int ecap0_in_pwm0_out;
201 int xdma_event_intr0;
202 int xdma_event_intr1;
306 #define PAD_CTRL_BASE 0x800
307 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
310 * Configure the pin mux for the module
312 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
317 for (i = 0; i < num_pins; i++)
318 MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset);
321 #define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
322 #define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
323 #define PRM_RSTST_WDT1_RST (1 << 4)
324 #define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
325 #define PRM_RSTST_ICEPICK_RST (1 << 9)
328 unsigned int prmrstctrl; /* offset 0x00 */
329 unsigned int prmrsttime; /* offset 0x04 */
330 unsigned int prmrstst; /* offset 0x08 */
334 static u32 prm_rstst __attribute__((section(".data")));
337 * Basic board specific setup
339 static const struct pin_mux stk5_pads[] = {
341 { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
343 { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
344 /* LCD POWER_ENABLE */
345 { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
346 /* LCD Backlight (PWM) */
347 { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
350 static const struct pin_mux stk5_lcd_pads[] = {
352 { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
353 { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
354 { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
355 { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
356 { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
357 { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
358 { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
359 { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
360 { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
361 { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
362 { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
363 { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
364 { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
365 { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
366 { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
367 { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
368 /* LCD control signals */
369 { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
370 { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
371 { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
372 { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
375 static const struct gpio stk5_gpios[] = {
376 { AM33XX_GPIO_NR(1, 26), GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
379 static const struct gpio stk5_lcd_gpios[] = {
380 { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
381 { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
382 { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
385 static const struct pin_mux stk5v5_pads[] = {
386 /* CAN transceiver control */
387 { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
390 static const struct gpio stk5v5_gpios[] = {
391 { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", },
395 vidinfo_t panel_info = {
396 /* set to max. size supported by SoC */
400 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
403 static struct da8xx_panel tx48_lcd_panel = {
404 .name = "640x480MR@60",
417 void *lcd_base; /* Start of framebuffer memory */
418 void *lcd_console_address; /* Start of console buffer */
427 static int lcd_enabled = 1;
429 void lcd_initcolregs(void)
433 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
437 void lcd_enable(void)
440 * global variable from common/lcd.c
441 * Set to 0 here to prevent messages from going to LCD
442 * rather than serial console
447 karo_load_splashimage(1);
449 gpio_set_value(TX48_LCD_PWR_GPIO, 1);
450 gpio_set_value(TX48_LCD_RST_GPIO, 1);
452 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 0);
456 void lcd_disable(void)
461 void lcd_panel_disable(void)
464 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 1);
465 gpio_set_value(TX48_LCD_PWR_GPIO, 0);
466 gpio_set_value(TX48_LCD_RST_GPIO, 0);
470 void lcd_ctrl_init(void *lcdbase)
472 int color_depth = 24;
475 struct da8xx_panel *p = &tx48_lcd_panel;
479 printf("LCD disabled\n");
483 if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
488 vm = getenv("video_mode");
494 strncpy((char *)p->name, vm, sizeof(p->name));
496 val = simple_strtoul(vm, &vm, 0);
498 if (val > panel_info.vl_col)
499 val = panel_info.vl_col;
501 panel_info.vl_col = val;
504 val = simple_strtoul(vm + 1, &vm, 0);
505 if (val > panel_info.vl_row)
506 val = panel_info.vl_row;
508 panel_info.vl_row = val;
510 while (*vm != '\0') {
518 color_depth = simple_strtoul(vm + 1, &vm, 10);
522 refresh = simple_strtoul(vm + 1, &vm, 10);
526 debug("Ignoring '%c'\n", *vm);
530 switch (color_depth) {
532 panel_info.vl_bpix = 3;
536 panel_info.vl_bpix = 4;
540 panel_info.vl_bpix = 5;
544 printf("Invalid color_depth %u from video_mode '%s'; using default: %u\n",
545 color_depth, getenv("video_mode"), 24);
547 lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col;
548 p->pxl_clk = refresh *
549 (p->width + p->hfp + p->hbp + p->hsw) *
550 (p->height + p->vfp + p->vbp + p->vsw);
551 debug("Pixel clock set to %u.%03uMHz\n",
552 p->pxl_clk / 1000000, p->pxl_clk / 1000 % 1000);
554 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
555 tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
556 debug("Initializing FB driver\n");
557 da8xx_video_init(&tx48_lcd_panel, color_depth);
559 if (karo_load_splashimage(0) == 0) {
560 debug("Initializing LCD controller\n");
563 debug("Skipping initialization of LCD controller\n");
567 #define lcd_enabled 0
568 #endif /* CONFIG_LCD */
570 static void stk5_board_init(void)
572 tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
575 static void stk5v3_board_init(void)
580 static void stk5v5_board_init(void)
583 tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
584 gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
587 /* called with default environment! */
590 /* mach type passed to kernel */
591 #ifdef CONFIG_OF_LIBFDT
592 gd->bd->bi_arch_number = -1;
594 /* address of boot parameters */
595 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
600 static void show_reset_cause(u32 prm_rstst)
602 const char *dlm = "";
604 printf("RESET cause: ");
605 if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
606 printf("%sPOR", dlm);
609 if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
613 if (prm_rstst & PRM_RSTST_WDT1_RST) {
614 printf("%sWATCHDOG", dlm);
617 if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
618 printf("%sWARM", dlm);
621 if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
622 printf("%sJTAG", dlm);
631 /* called with default environment! */
634 struct prm_device *prmdev = (struct prm_device *)PRM_DEVICE;
636 prm_rstst = readl(&prmdev->prmrstst);
637 show_reset_cause(prm_rstst);
639 #ifdef CONFIG_OF_LIBFDT
640 printf("Board: Ka-Ro TX48-7020 with FDT support\n");
642 printf("Board: Ka-Ro TX48-7020\n");
648 /* called with environment from NAND or MMC */
649 int board_late_init(void)
651 const char *baseboard;
653 #ifdef CONFIG_OF_BOARD_SETUP
656 baseboard = getenv("baseboard");
660 if (strncmp(baseboard, "stk5", 4) == 0) {
661 printf("Baseboard: %s\n", baseboard);
662 if ((strlen(baseboard) == 4) ||
663 strcmp(baseboard, "stk5-v3") == 0) {
665 } else if (strcmp(baseboard, "stk5-v5") == 0) {
668 printf("WARNING: Unsupported STK5 board rev.: %s\n",
672 printf("WARNING: Unsupported baseboard: '%s'\n",
680 #ifdef CONFIG_DRIVER_TI_CPSW
681 static void tx48_phy_init(char *name, int addr)
683 debug("%s: Resetting ethernet PHY\n", __func__);
685 gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
690 gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
692 /* Wait for PHY internal POR signal to deassert */
696 static void cpsw_control(int enabled)
698 /* nothing for now */
699 /* TODO : VTP was here before */
702 static struct cpsw_slave_data cpsw_slaves[] = {
704 .slave_reg_ofs = 0x208,
705 .sliver_reg_ofs = 0xd80,
710 static struct cpsw_platform_data cpsw_data = {
711 .mdio_base = CPSW_MDIO_BASE,
712 .cpsw_base = CPSW_BASE,
715 .cpdma_reg_ofs = 0x800,
716 .slaves = ARRAY_SIZE(cpsw_slaves),
717 .slave_data = cpsw_slaves,
718 .ale_reg_ofs = 0xd00,
720 .host_port_reg_ofs = 0x108,
721 .hw_stats_reg_ofs = 0x900,
722 .mac_control = (1 << 5) /* MIIEN */,
723 .control = cpsw_control,
724 .phy_init = tx48_phy_init,
727 .version = CPSW_CTRL_VERSION_2,
730 int board_eth_init(bd_t *bis)
732 uint8_t mac_addr[ETH_ALEN];
733 uint32_t mac_hi, mac_lo;
735 /* try reading mac address from efuse */
736 mac_lo = __raw_readl(MAC_ID0_LO);
737 mac_hi = __raw_readl(MAC_ID0_HI);
739 mac_addr[0] = mac_hi & 0xFF;
740 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
741 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
742 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
743 mac_addr[4] = mac_lo & 0xFF;
744 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
746 if (is_valid_ether_addr(mac_addr)) {
747 debug("MAC addr set to: %02x:%02x:%02x:%02x:%02x:%02x\n",
748 mac_addr[0], mac_addr[1], mac_addr[2],
749 mac_addr[3], mac_addr[4], mac_addr[5]);
750 eth_setenv_enetaddr("ethaddr", mac_addr);
752 printf("ERROR: Did not find a valid mac address in e-fuse\n");
755 __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
756 __raw_writel(0x5D, GMII_SEL);
757 return cpsw_register(&cpsw_data);
759 #endif /* CONFIG_DRIVER_TI_CPSW */
761 #if defined(CONFIG_NAND_AM33XX) && defined(CONFIG_CMD_SWITCH_ECC)
762 /******************************************************************************
763 * Command to switch between NAND HW and SW ecc
764 *****************************************************************************/
765 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
772 if (strncmp(argv[1], "hw", 2) == 0) {
774 type = simple_strtoul(argv[2], NULL, 10);
775 am33xx_nand_switch_ecc(NAND_ECC_HW, type);
777 else if (strncmp(argv[1], "sw", 2) == 0)
778 am33xx_nand_switch_ecc(NAND_ECC_SOFT, 0);
785 printf("Usage: nandecc %s\n", cmdtp->usage);
790 nandecc, 3, 1, do_switch_ecc,
791 "Switch NAND ECC calculation algorithm b/w hardware and software",
792 "[sw|hw <hw_type>] \n"
793 " [sw|hw]- Switch b/w hardware(hw) & software(sw) ecc algorithm\n"
794 " hw_type- 0 for Hamming code\n"
799 #endif /* CONFIG_NAND_AM33XX && CONFIG_CMD_SWITCH_ECC */
807 void show_activity(int arg)
809 static int led_state = LED_STATE_INIT;
812 if (led_state == LED_STATE_INIT) {
814 gpio_set_value(TX48_LED_GPIO, 1);
815 led_state = LED_STATE_ON;
817 if (get_timer(last) > CONFIG_SYS_HZ) {
819 if (led_state == LED_STATE_ON) {
820 gpio_set_value(TX48_LED_GPIO, 0);
822 gpio_set_value(TX48_LED_GPIO, 1);
824 led_state = 1 - led_state;
829 #ifdef CONFIG_OF_BOARD_SETUP
830 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
831 #include <jffs2/jffs2.h>
832 #include <mtd_node.h>
833 struct node_info nodes[] = {
834 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
838 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
839 #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
841 static void tx48_fixup_flexcan(void *blob)
843 const char *baseboard = getenv("baseboard");
845 if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
848 karo_fdt_del_prop(blob, "ti,dcan", 0x481cc000, "can-xcvr-enable");
849 karo_fdt_del_prop(blob, "ti,dcan", 0x481d0000, "can-xcvr-enable");
852 void ft_board_setup(void *blob, bd_t *bd)
854 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
855 fdt_fixup_ethernet(blob);
857 karo_fdt_fixup_touchpanel(blob);
858 tx48_fixup_flexcan(blob);
860 #endif /* CONFIG_OF_BOARD_SETUP */