3 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
6 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
25 #include <fdt_support.h>
28 #include <linux/mtd/nand.h>
31 #include <asm/cache.h>
32 #include <asm/omap_common.h>
34 #include <asm/arch/cpu.h>
35 #include <asm/arch/hardware.h>
36 #include <asm/arch/mmc_host_def.h>
37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/nand.h>
39 #include <asm/arch/clock.h>
41 #include <asm/arch/da8xx-fb.h>
43 #include "../common/karo.h"
45 DECLARE_GLOBAL_DATA_PTR;
47 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
48 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
49 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
50 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
51 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
53 #define GMII_SEL (CTRL_BASE + 0x650)
56 #define UART_SYSCFG_OFFSET 0x54
57 #define UART_SYSSTS_OFFSET 0x58
59 #define UART_RESET (0x1 << 1)
60 #define UART_CLK_RUNNING_MASK 0x1
61 #define UART_SMART_IDLE_EN (0x1 << 0x3)
64 #define TSICR_REG 0x54
65 #define TIOCP_CFG_REG 0x10
68 /* RGMII mode define */
69 #define RGMII_MODE_ENABLE 0xA
70 #define RMII_MODE_ENABLE 0x5
71 #define MII_MODE_ENABLE 0x0
73 #define NO_OF_MAC_ADDR 1
76 #define MUX_CFG(value, offset) { \
77 __raw_writel(value, (CTRL_BASE + (offset))); \
80 /* PAD Control Fields */
81 #define SLEWCTRL (0x1 << 6)
82 #define RXACTIVE (0x1 << 5)
83 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
84 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
85 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
86 #define MODE(val) (val)
90 * Field names corresponds to the pad signal name
182 int ecap0_in_pwm0_out;
201 int xdma_event_intr0;
202 int xdma_event_intr1;
306 #define PAD_CTRL_BASE 0x800
307 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
311 * Configure the pin mux for the module
313 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
318 for (i = 0; i < num_pins; i++)
319 MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset);
322 #define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
323 #define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
324 #define PRM_RSTST_WDT1_RST (1 << 4)
325 #define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
326 #define PRM_RSTST_ICEPICK_RST (1 << 9)
328 static u32 prm_rstst __attribute__((section(".data")));
331 * Basic board specific setup
333 static const struct pin_mux stk5_pads[] = {
335 { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
337 { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
338 /* LCD POWER_ENABLE */
339 { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
340 /* LCD Backlight (PWM) */
341 { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
344 static const struct pin_mux stk5_lcd_pads[] = {
346 { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
347 { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
348 { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
349 { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
350 { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
351 { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
352 { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
353 { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
354 { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
355 { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
356 { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
357 { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
358 { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
359 { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
360 { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
361 { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
362 /* LCD control signals */
363 { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
364 { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
365 { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
366 { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
369 static const struct gpio stk5_gpios[] = {
370 { AM33XX_GPIO_NR(1, 26), GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
373 static const struct gpio stk5_lcd_gpios[] = {
374 { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
375 { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
376 { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
379 static const struct pin_mux stk5v5_pads[] = {
380 /* CAN transceiver control */
381 { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
384 static const struct gpio stk5v5_gpios[] = {
385 { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", },
389 static u16 tx48_cmap[256];
390 vidinfo_t panel_info = {
391 /* set to max. size supported by SoC */
395 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
399 #define FB_SYNC_OE_LOW_ACT (1 << 31)
400 #define FB_SYNC_CLK_LAT_FALL (1 << 30)
402 static struct fb_videomode tx48_fb_modes[] = {
404 /* Standard VGA timing */
409 .pixclock = KHZ2PICOS(25175),
416 .sync = FB_SYNC_CLK_LAT_FALL,
419 /* Emerging ETV570 640 x 480 display. Syncs low active,
420 * DE high active, 115.2 mm x 86.4 mm display area
421 * VGA compatible timing
427 .pixclock = KHZ2PICOS(25175),
434 .sync = FB_SYNC_CLK_LAT_FALL,
437 /* Emerging ET0350G0DH6 320 x 240 display.
438 * 70.08 mm x 52.56 mm display area.
444 .pixclock = KHZ2PICOS(6500),
445 .left_margin = 68 - 34,
448 .upper_margin = 18 - 3,
451 .sync = FB_SYNC_CLK_LAT_FALL,
454 /* Emerging ET0430G0DH6 480 x 272 display.
455 * 95.04 mm x 53.856 mm display area.
461 .pixclock = KHZ2PICOS(9000),
470 /* Emerging ET0500G0DH6 800 x 480 display.
471 * 109.6 mm x 66.4 mm display area.
477 .pixclock = KHZ2PICOS(33260),
478 .left_margin = 216 - 128,
480 .right_margin = 1056 - 800 - 216,
481 .upper_margin = 35 - 2,
483 .lower_margin = 525 - 480 - 35,
484 .sync = FB_SYNC_CLK_LAT_FALL,
487 /* Emerging ETQ570G0DH6 320 x 240 display.
488 * 115.2 mm x 86.4 mm display area.
494 .pixclock = KHZ2PICOS(6400),
498 .upper_margin = 16, /* 15 according to datasheet */
499 .vsync_len = 3, /* TVP -> 1>x>5 */
500 .lower_margin = 4, /* 4.5 according to datasheet */
501 .sync = FB_SYNC_CLK_LAT_FALL,
504 /* Emerging ET0700G0DH6 800 x 480 display.
505 * 152.4 mm x 91.44 mm display area.
511 .pixclock = KHZ2PICOS(33260),
512 .left_margin = 216 - 128,
514 .right_margin = 1056 - 800 - 216,
515 .upper_margin = 35 - 2,
517 .lower_margin = 525 - 480 - 35,
518 .sync = FB_SYNC_CLK_LAT_FALL,
521 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
529 .sync = FB_SYNC_CLK_LAT_FALL,
533 void *lcd_base; /* Start of framebuffer memory */
534 void *lcd_console_address; /* Start of console buffer */
542 static int lcd_enabled = 1;
544 void lcd_initcolregs(void)
548 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
552 void lcd_enable(void)
555 * global variable from common/lcd.c
556 * Set to 0 here to prevent messages from going to LCD
557 * rather than serial console
562 karo_load_splashimage(1);
564 debug("Switching LCD on\n");
565 gpio_set_value(TX48_LCD_PWR_GPIO, 1);
567 gpio_set_value(TX48_LCD_RST_GPIO, 1);
569 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 0);
573 void lcd_disable(void)
576 printf("Disabling LCD\n");
582 static void tx48_lcd_panel_setup(struct da8xx_panel *p,
583 struct fb_videomode *fb)
585 p->pxl_clk = PICOS2KHZ(fb->pixclock) * 1000;
588 p->hbp = fb->left_margin;
589 p->hsw = fb->hsync_len;
590 p->hfp = fb->right_margin;
592 p->height = fb->yres;
593 p->vbp = fb->upper_margin;
594 p->vsw = fb->vsync_len;
595 p->vfp = fb->lower_margin;
597 p->invert_pxl_clk = !!(fb->sync & FB_SYNC_CLK_LAT_FALL);
600 void lcd_panel_disable(void)
603 debug("Switching LCD off\n");
604 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 1);
605 gpio_set_value(TX48_LCD_PWR_GPIO, 0);
606 gpio_set_value(TX48_LCD_RST_GPIO, 0);
610 void lcd_ctrl_init(void *lcdbase)
612 int color_depth = 24;
616 struct fb_videomode *p = &tx48_fb_modes[0];
617 struct fb_videomode fb_mode;
618 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
621 debug("LCD disabled\n");
625 if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
626 debug("Disabling LCD\n");
628 setenv("splashimage", NULL);
634 vm = getenv("video_mode");
636 debug("Disabling LCD\n");
641 if ((v = strstr(vm, ":")))
644 if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
646 debug("Using video mode from FDT\n");
648 if (fb_mode.xres > panel_info.vl_col ||
649 fb_mode.yres > panel_info.vl_row) {
650 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
651 fb_mode.xres, fb_mode.yres,
652 panel_info.vl_col, panel_info.vl_row);
658 debug("Trying compiled-in video modes\n");
659 while (p->name != NULL) {
660 if (strcmp(p->name, vm) == 0) {
661 debug("Using video mode: '%s'\n", p->name);
668 debug("Trying to decode video_mode: '%s'\n", vm);
669 while (*vm != '\0') {
670 if (*vm >= '0' && *vm <= '9') {
673 val = simple_strtoul(vm, &end, 0);
676 if (val > panel_info.vl_col)
677 val = panel_info.vl_col;
679 panel_info.vl_col = val;
681 } else if (!yres_set) {
682 if (val > panel_info.vl_row)
683 val = panel_info.vl_row;
685 panel_info.vl_row = val;
687 } else if (!bpp_set) {
696 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
697 end - vm, vm, color_depth);
700 } else if (!refresh_set) {
727 if (p->xres == 0 || p->yres == 0) {
728 printf("Invalid video mode: %s\n", getenv("video_mode"));
730 printf("Supported video modes are:");
731 for (p = &tx48_fb_modes[0]; p->name != NULL; p++) {
732 printf(" %s", p->name);
737 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
738 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
739 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
743 panel_info.vl_col = p->xres;
744 panel_info.vl_row = p->yres;
746 switch (color_depth) {
748 panel_info.vl_bpix = LCD_COLOR8;
751 panel_info.vl_bpix = LCD_COLOR16;
754 panel_info.vl_bpix = LCD_COLOR24;
757 p->pixclock = KHZ2PICOS(refresh *
758 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
759 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
761 debug("Pixel clock set to %lu.%03lu MHz\n",
762 PICOS2KHZ(p->pixclock) / 1000,
763 PICOS2KHZ(p->pixclock) % 1000);
767 char *modename = getenv("video_mode");
769 printf("Creating new display-timing node from '%s'\n",
771 ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
773 printf("Failed to create new display-timing node from '%s': %d\n",
777 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
778 tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
780 if (karo_load_splashimage(0) == 0) {
781 struct da8xx_panel da8xx_panel = { };
783 debug("Initializing FB driver\n");
784 tx48_lcd_panel_setup(&da8xx_panel, p);
785 da8xx_video_init(&da8xx_panel, color_depth);
787 debug("Initializing LCD controller\n");
790 debug("Skipping initialization of LCD controller\n");
794 #define lcd_enabled 0
795 #endif /* CONFIG_LCD */
797 static void stk5_board_init(void)
799 tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
802 static void stk5v3_board_init(void)
807 static void stk5v5_board_init(void)
810 tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
811 gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
814 /* called with default environment! */
817 /* mach type passed to kernel */
818 #ifdef CONFIG_OF_LIBFDT
819 gd->bd->bi_arch_number = -1;
821 /* address of boot parameters */
822 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
827 static void show_reset_cause(u32 prm_rstst)
829 const char *dlm = "";
831 printf("RESET cause: ");
832 if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
833 printf("%sPOR", dlm);
836 if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
840 if (prm_rstst & PRM_RSTST_WDT1_RST) {
841 printf("%sWATCHDOG", dlm);
844 if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
845 printf("%sWARM", dlm);
848 if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
849 printf("%sJTAG", dlm);
858 /* called with default environment! */
861 prm_rstst = readl(PRM_RSTST);
862 show_reset_cause(prm_rstst);
864 #ifdef CONFIG_OF_LIBFDT
865 printf("Board: Ka-Ro TX48-7020 with FDT support\n");
867 printf("Board: Ka-Ro TX48-7020\n");
873 static void tx48_set_cpu_clock(void)
875 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
877 if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST))
880 if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000)
883 mpu_pll_config_val(cpu_clk);
885 printf("CPU clock set to %lu.%03lu MHz\n",
886 mpu_clk_rate() / 1000000,
887 mpu_clk_rate() / 1000 % 1000);
890 static void tx48_init_mac(void)
892 uint8_t mac_addr[ETH_ALEN];
893 uint32_t mac_hi, mac_lo;
895 /* try reading mac address from efuse */
896 mac_lo = __raw_readl(MAC_ID0_LO);
897 mac_hi = __raw_readl(MAC_ID0_HI);
899 mac_addr[0] = mac_hi & 0xFF;
900 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
901 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
902 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
903 mac_addr[4] = mac_lo & 0xFF;
904 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
906 if (!is_valid_ether_addr(mac_addr)) {
907 printf("No valid MAC address programmed\n");
910 printf("MAC addr from fuse: %pM\n", mac_addr);
911 eth_setenv_enetaddr("ethaddr", mac_addr);
914 /* called with environment from NAND or MMC */
915 int board_late_init(void)
918 const char *baseboard;
920 tx48_set_cpu_clock();
923 baseboard = getenv("baseboard");
927 if (strncmp(baseboard, "stk5", 4) == 0) {
928 printf("Baseboard: %s\n", baseboard);
929 if ((strlen(baseboard) == 4) ||
930 strcmp(baseboard, "stk5-v3") == 0) {
932 } else if (strcmp(baseboard, "stk5-v5") == 0) {
935 printf("WARNING: Unsupported STK5 board rev.: %s\n",
939 printf("WARNING: Unsupported baseboard: '%s'\n",
948 #ifdef CONFIG_DRIVER_TI_CPSW
949 static void tx48_phy_init(char *name, int addr)
951 debug("%s: Resetting ethernet PHY\n", __func__);
953 gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
958 gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
960 /* Wait for PHY internal POR signal to deassert */
964 static void cpsw_control(int enabled)
966 /* nothing for now */
967 /* TODO : VTP was here before */
970 static struct cpsw_slave_data cpsw_slaves[] = {
972 .slave_reg_ofs = 0x208,
973 .sliver_reg_ofs = 0xd80,
975 .phy_if = PHY_INTERFACE_MODE_RMII,
981 /* Nothing to be done here */
984 static struct cpsw_platform_data cpsw_data = {
985 .mdio_base = CPSW_MDIO_BASE,
986 .cpsw_base = CPSW_BASE,
989 .cpdma_reg_ofs = 0x800,
990 .slaves = ARRAY_SIZE(cpsw_slaves),
991 .slave_data = cpsw_slaves,
992 .ale_reg_ofs = 0xd00,
994 .host_port_reg_ofs = 0x108,
995 .hw_stats_reg_ofs = 0x900,
996 .mac_control = (1 << 5) /* MIIEN */,
997 .control = cpsw_control,
998 .phy_init = tx48_phy_init,
1001 .version = CPSW_CTRL_VERSION_2,
1004 int board_eth_init(bd_t *bis)
1006 __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
1007 __raw_writel(0x5D, GMII_SEL);
1008 return cpsw_register(&cpsw_data);
1010 #endif /* CONFIG_DRIVER_TI_CPSW */
1012 void tx48_disable_watchdog(void)
1014 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
1016 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1018 writel(0xaaaa, &wdtimer->wdtwspr);
1019 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1021 writel(0x5555, &wdtimer->wdtwspr);
1025 LED_STATE_INIT = -1,
1030 void show_activity(int arg)
1032 static int led_state = LED_STATE_INIT;
1035 if (led_state == LED_STATE_INIT) {
1036 last = get_timer(0);
1037 gpio_set_value(TX48_LED_GPIO, 1);
1038 led_state = LED_STATE_ON;
1040 if (get_timer(last) > CONFIG_SYS_HZ) {
1041 last = get_timer(0);
1042 if (led_state == LED_STATE_ON) {
1043 gpio_set_value(TX48_LED_GPIO, 0);
1045 gpio_set_value(TX48_LED_GPIO, 1);
1047 led_state = 1 - led_state;
1052 #ifdef CONFIG_OF_BOARD_SETUP
1053 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1054 #include <jffs2/jffs2.h>
1055 #include <mtd_node.h>
1056 struct node_info nodes[] = {
1057 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
1061 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1062 #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
1064 void ft_board_setup(void *blob, bd_t *bd)
1066 const char *baseboard = getenv("baseboard");
1067 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1069 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1070 fdt_fixup_ethernet(blob);
1072 karo_fdt_fixup_touchpanel(blob);
1073 karo_fdt_fixup_flexcan(blob, stk5_v5);
1075 tx48_disable_watchdog();
1077 #endif /* CONFIG_OF_BOARD_SETUP */