2 * Copyright (C) 2012-2013 Lothar Waßmann <LW@KARO-electronics.de>
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
24 #include <fdt_support.h>
27 #include <linux/mtd/nand.h>
30 #include <asm/cache.h>
31 #include <asm/omap_common.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/hardware.h>
35 #include <asm/arch/mmc_host_def.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/nand.h>
38 #include <asm/arch/clock.h>
40 #include <asm/arch/da8xx-fb.h>
42 #include "../common/karo.h"
44 DECLARE_GLOBAL_DATA_PTR;
46 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
47 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
48 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
49 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
50 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
52 #define GMII_SEL (CTRL_BASE + 0x650)
55 #define UART_SYSCFG_OFFSET 0x54
56 #define UART_SYSSTS_OFFSET 0x58
58 #define UART_RESET (0x1 << 1)
59 #define UART_CLK_RUNNING_MASK 0x1
60 #define UART_SMART_IDLE_EN (0x1 << 0x3)
63 #define TSICR_REG 0x54
64 #define TIOCP_CFG_REG 0x10
67 /* RGMII mode define */
68 #define RGMII_MODE_ENABLE 0xA
69 #define RMII_MODE_ENABLE 0x5
70 #define MII_MODE_ENABLE 0x0
72 #define NO_OF_MAC_ADDR 1
75 #define MUX_CFG(value, offset) { \
76 __raw_writel(value, (CTRL_BASE + (offset))); \
79 /* PAD Control Fields */
80 #define SLEWCTRL (0x1 << 6)
81 #define RXACTIVE (0x1 << 5)
82 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
83 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
84 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
85 #define MODE(val) (val)
89 * Field names corresponds to the pad signal name
181 int ecap0_in_pwm0_out;
200 int xdma_event_intr0;
201 int xdma_event_intr1;
305 #define PAD_CTRL_BASE 0x800
306 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
310 * Configure the pin mux for the module
312 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
317 for (i = 0; i < num_pins; i++)
318 MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset);
321 #define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
322 #define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
323 #define PRM_RSTST_WDT1_RST (1 << 4)
324 #define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
325 #define PRM_RSTST_ICEPICK_RST (1 << 9)
327 static u32 prm_rstst __attribute__((section(".data")));
330 * Basic board specific setup
332 static const struct pin_mux stk5_pads[] = {
334 { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
336 { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
337 /* LCD POWER_ENABLE */
338 { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
339 /* LCD Backlight (PWM) */
340 { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
343 static const struct pin_mux stk5_lcd_pads[] = {
345 { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
346 { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
347 { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
348 { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
349 { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
350 { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
351 { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
352 { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
353 { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
354 { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
355 { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
356 { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
357 { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
358 { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
359 { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
360 { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
361 /* LCD control signals */
362 { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
363 { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
364 { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
365 { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
368 static const struct gpio stk5_gpios[] = {
369 { AM33XX_GPIO_NR(1, 26), GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
372 static const struct gpio stk5_lcd_gpios[] = {
373 { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
374 { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
375 { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
378 static const struct pin_mux stk5v5_pads[] = {
379 /* CAN transceiver control */
380 { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
383 static const struct gpio stk5v5_gpios[] = {
384 { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", },
388 static u16 tx48_cmap[256];
389 vidinfo_t panel_info = {
390 /* set to max. size supported by SoC */
394 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
398 #define FB_SYNC_OE_LOW_ACT (1 << 31)
399 #define FB_SYNC_CLK_LAT_FALL (1 << 30)
401 static struct fb_videomode tx48_fb_modes[] = {
403 /* Standard VGA timing */
408 .pixclock = KHZ2PICOS(25175),
415 .sync = FB_SYNC_CLK_LAT_FALL,
418 /* Emerging ETV570 640 x 480 display. Syncs low active,
419 * DE high active, 115.2 mm x 86.4 mm display area
420 * VGA compatible timing
426 .pixclock = KHZ2PICOS(25175),
433 .sync = FB_SYNC_CLK_LAT_FALL,
436 /* Emerging ET0350G0DH6 320 x 240 display.
437 * 70.08 mm x 52.56 mm display area.
443 .pixclock = KHZ2PICOS(6500),
444 .left_margin = 68 - 34,
447 .upper_margin = 18 - 3,
450 .sync = FB_SYNC_CLK_LAT_FALL,
453 /* Emerging ET0430G0DH6 480 x 272 display.
454 * 95.04 mm x 53.856 mm display area.
460 .pixclock = KHZ2PICOS(9000),
469 /* Emerging ET0500G0DH6 800 x 480 display.
470 * 109.6 mm x 66.4 mm display area.
476 .pixclock = KHZ2PICOS(33260),
477 .left_margin = 216 - 128,
479 .right_margin = 1056 - 800 - 216,
480 .upper_margin = 35 - 2,
482 .lower_margin = 525 - 480 - 35,
483 .sync = FB_SYNC_CLK_LAT_FALL,
486 /* Emerging ETQ570G0DH6 320 x 240 display.
487 * 115.2 mm x 86.4 mm display area.
493 .pixclock = KHZ2PICOS(6400),
497 .upper_margin = 16, /* 15 according to datasheet */
498 .vsync_len = 3, /* TVP -> 1>x>5 */
499 .lower_margin = 4, /* 4.5 according to datasheet */
500 .sync = FB_SYNC_CLK_LAT_FALL,
503 /* Emerging ET0700G0DH6 800 x 480 display.
504 * 152.4 mm x 91.44 mm display area.
510 .pixclock = KHZ2PICOS(33260),
511 .left_margin = 216 - 128,
513 .right_margin = 1056 - 800 - 216,
514 .upper_margin = 35 - 2,
516 .lower_margin = 525 - 480 - 35,
517 .sync = FB_SYNC_CLK_LAT_FALL,
520 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
528 .sync = FB_SYNC_CLK_LAT_FALL,
532 void *lcd_base; /* Start of framebuffer memory */
533 void *lcd_console_address; /* Start of console buffer */
541 static int lcd_enabled = 1;
543 void lcd_initcolregs(void)
547 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
551 void lcd_enable(void)
554 * global variable from common/lcd.c
555 * Set to 0 here to prevent messages from going to LCD
556 * rather than serial console
561 karo_load_splashimage(1);
563 debug("Switching LCD on\n");
564 gpio_set_value(TX48_LCD_PWR_GPIO, 1);
566 gpio_set_value(TX48_LCD_RST_GPIO, 1);
568 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 0);
572 void lcd_disable(void)
575 printf("Disabling LCD\n");
581 static void tx48_lcd_panel_setup(struct da8xx_panel *p,
582 struct fb_videomode *fb)
584 p->pxl_clk = PICOS2KHZ(fb->pixclock) * 1000;
587 p->hbp = fb->left_margin;
588 p->hsw = fb->hsync_len;
589 p->hfp = fb->right_margin;
591 p->height = fb->yres;
592 p->vbp = fb->upper_margin;
593 p->vsw = fb->vsync_len;
594 p->vfp = fb->lower_margin;
596 p->invert_pxl_clk = !!(fb->sync & FB_SYNC_CLK_LAT_FALL);
599 void lcd_panel_disable(void)
602 debug("Switching LCD off\n");
603 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 1);
604 gpio_set_value(TX48_LCD_PWR_GPIO, 0);
605 gpio_set_value(TX48_LCD_RST_GPIO, 0);
609 void lcd_ctrl_init(void *lcdbase)
611 int color_depth = 24;
615 struct fb_videomode *p = &tx48_fb_modes[0];
616 struct fb_videomode fb_mode;
617 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
620 debug("LCD disabled\n");
624 if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
625 debug("Disabling LCD\n");
627 setenv("splashimage", NULL);
633 vm = getenv("video_mode");
635 debug("Disabling LCD\n");
640 if ((v = strstr(vm, ":")))
643 if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
645 debug("Using video mode from FDT\n");
647 if (fb_mode.xres > panel_info.vl_col ||
648 fb_mode.yres > panel_info.vl_row) {
649 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
650 fb_mode.xres, fb_mode.yres,
651 panel_info.vl_col, panel_info.vl_row);
657 debug("Trying compiled-in video modes\n");
658 while (p->name != NULL) {
659 if (strcmp(p->name, vm) == 0) {
660 debug("Using video mode: '%s'\n", p->name);
667 debug("Trying to decode video_mode: '%s'\n", vm);
668 while (*vm != '\0') {
669 if (*vm >= '0' && *vm <= '9') {
672 val = simple_strtoul(vm, &end, 0);
675 if (val > panel_info.vl_col)
676 val = panel_info.vl_col;
678 panel_info.vl_col = val;
680 } else if (!yres_set) {
681 if (val > panel_info.vl_row)
682 val = panel_info.vl_row;
684 panel_info.vl_row = val;
686 } else if (!bpp_set) {
695 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
696 end - vm, vm, color_depth);
699 } else if (!refresh_set) {
726 if (p->xres == 0 || p->yres == 0) {
727 printf("Invalid video mode: %s\n", getenv("video_mode"));
729 printf("Supported video modes are:");
730 for (p = &tx48_fb_modes[0]; p->name != NULL; p++) {
731 printf(" %s", p->name);
736 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
737 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
738 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
742 panel_info.vl_col = p->xres;
743 panel_info.vl_row = p->yres;
745 switch (color_depth) {
747 panel_info.vl_bpix = LCD_COLOR8;
750 panel_info.vl_bpix = LCD_COLOR16;
753 panel_info.vl_bpix = LCD_COLOR24;
756 p->pixclock = KHZ2PICOS(refresh *
757 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
758 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
760 debug("Pixel clock set to %lu.%03lu MHz\n",
761 PICOS2KHZ(p->pixclock) / 1000,
762 PICOS2KHZ(p->pixclock) % 1000);
766 char *modename = getenv("video_mode");
768 printf("Creating new display-timing node from '%s'\n",
770 ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
772 printf("Failed to create new display-timing node from '%s': %d\n",
776 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
777 tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
779 if (karo_load_splashimage(0) == 0) {
780 struct da8xx_panel da8xx_panel = { };
782 debug("Initializing FB driver\n");
783 tx48_lcd_panel_setup(&da8xx_panel, p);
784 da8xx_video_init(&da8xx_panel, color_depth);
786 debug("Initializing LCD controller\n");
789 debug("Skipping initialization of LCD controller\n");
793 #define lcd_enabled 0
794 #endif /* CONFIG_LCD */
796 static void stk5_board_init(void)
798 tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
801 static void stk5v3_board_init(void)
806 static void stk5v5_board_init(void)
809 tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
810 gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
813 /* called with default environment! */
816 /* mach type passed to kernel */
817 #ifdef CONFIG_OF_LIBFDT
818 gd->bd->bi_arch_number = -1;
820 /* address of boot parameters */
821 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
826 static void show_reset_cause(u32 prm_rstst)
828 const char *dlm = "";
830 printf("RESET cause: ");
831 if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
832 printf("%sPOR", dlm);
835 if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
839 if (prm_rstst & PRM_RSTST_WDT1_RST) {
840 printf("%sWATCHDOG", dlm);
843 if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
844 printf("%sWARM", dlm);
847 if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
848 printf("%sJTAG", dlm);
857 /* called with default environment! */
860 prm_rstst = readl(PRM_RSTST);
861 show_reset_cause(prm_rstst);
863 #ifdef CONFIG_OF_LIBFDT
864 printf("Board: Ka-Ro TX48-7020 with FDT support\n");
866 printf("Board: Ka-Ro TX48-7020\n");
872 static void tx48_set_cpu_clock(void)
874 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
876 if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST))
879 if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000)
882 mpu_pll_config_val(cpu_clk);
884 printf("CPU clock set to %lu.%03lu MHz\n",
885 mpu_clk_rate() / 1000000,
886 mpu_clk_rate() / 1000 % 1000);
889 static void tx48_init_mac(void)
891 uint8_t mac_addr[ETH_ALEN];
892 uint32_t mac_hi, mac_lo;
894 /* try reading mac address from efuse */
895 mac_lo = __raw_readl(MAC_ID0_LO);
896 mac_hi = __raw_readl(MAC_ID0_HI);
898 mac_addr[0] = mac_hi & 0xFF;
899 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
900 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
901 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
902 mac_addr[4] = mac_lo & 0xFF;
903 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
905 if (!is_valid_ether_addr(mac_addr)) {
906 printf("No valid MAC address programmed\n");
909 printf("MAC addr from fuse: %pM\n", mac_addr);
910 eth_setenv_enetaddr("ethaddr", mac_addr);
913 /* called with environment from NAND or MMC */
914 int board_late_init(void)
917 const char *baseboard;
919 tx48_set_cpu_clock();
922 baseboard = getenv("baseboard");
926 if (strncmp(baseboard, "stk5", 4) == 0) {
927 printf("Baseboard: %s\n", baseboard);
928 if ((strlen(baseboard) == 4) ||
929 strcmp(baseboard, "stk5-v3") == 0) {
931 } else if (strcmp(baseboard, "stk5-v5") == 0) {
934 printf("WARNING: Unsupported STK5 board rev.: %s\n",
938 printf("WARNING: Unsupported baseboard: '%s'\n",
947 #ifdef CONFIG_DRIVER_TI_CPSW
948 static void tx48_phy_init(char *name, int addr)
950 debug("%s: Resetting ethernet PHY\n", __func__);
952 gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
957 gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
959 /* Wait for PHY internal POR signal to deassert */
963 static void cpsw_control(int enabled)
965 /* nothing for now */
966 /* TODO : VTP was here before */
969 static struct cpsw_slave_data cpsw_slaves[] = {
971 .slave_reg_ofs = 0x208,
972 .sliver_reg_ofs = 0xd80,
974 .phy_if = PHY_INTERFACE_MODE_RMII,
980 /* Nothing to be done here */
983 static struct cpsw_platform_data cpsw_data = {
984 .mdio_base = CPSW_MDIO_BASE,
985 .cpsw_base = CPSW_BASE,
988 .cpdma_reg_ofs = 0x800,
989 .slaves = ARRAY_SIZE(cpsw_slaves),
990 .slave_data = cpsw_slaves,
991 .ale_reg_ofs = 0xd00,
993 .host_port_reg_ofs = 0x108,
994 .hw_stats_reg_ofs = 0x900,
995 .mac_control = (1 << 5) /* MIIEN */,
996 .control = cpsw_control,
997 .phy_init = tx48_phy_init,
1000 .version = CPSW_CTRL_VERSION_2,
1003 int board_eth_init(bd_t *bis)
1005 __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
1006 __raw_writel(0x5D, GMII_SEL);
1007 return cpsw_register(&cpsw_data);
1009 #endif /* CONFIG_DRIVER_TI_CPSW */
1011 void tx48_disable_watchdog(void)
1013 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
1015 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1017 writel(0xaaaa, &wdtimer->wdtwspr);
1018 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1020 writel(0x5555, &wdtimer->wdtwspr);
1024 LED_STATE_INIT = -1,
1029 void show_activity(int arg)
1031 static int led_state = LED_STATE_INIT;
1034 if (led_state == LED_STATE_INIT) {
1035 last = get_timer(0);
1036 gpio_set_value(TX48_LED_GPIO, 1);
1037 led_state = LED_STATE_ON;
1039 if (get_timer(last) > CONFIG_SYS_HZ) {
1040 last = get_timer(0);
1041 if (led_state == LED_STATE_ON) {
1042 gpio_set_value(TX48_LED_GPIO, 0);
1044 gpio_set_value(TX48_LED_GPIO, 1);
1046 led_state = 1 - led_state;
1051 #ifdef CONFIG_OF_BOARD_SETUP
1052 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1053 #include <jffs2/jffs2.h>
1054 #include <mtd_node.h>
1055 struct node_info nodes[] = {
1056 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
1060 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1061 #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
1063 void ft_board_setup(void *blob, bd_t *bd)
1065 const char *baseboard = getenv("baseboard");
1066 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1068 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1069 fdt_fixup_ethernet(blob);
1071 karo_fdt_fixup_touchpanel(blob);
1072 karo_fdt_fixup_flexcan(blob, stk5_v5);
1074 tx48_disable_watchdog();
1076 #endif /* CONFIG_OF_BOARD_SETUP */