karo: fdt: prevent duplicate call of fdt_fixup_ethernet()
[karo-tx-uboot.git] / board / karo / tx51 / tx51.c
1 /*
2  * Copyright (C) 2011-2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18
19 #include <common.h>
20 #include <errno.h>
21 #include <libfdt.h>
22 #include <fdt_support.h>
23 #include <lcd.h>
24 #include <netdev.h>
25 #include <mmc.h>
26 #include <fsl_esdhc.h>
27 #include <video_fb.h>
28 #include <ipu.h>
29 #include <mxcfb.h>
30 #include <linux/fb.h>
31 #include <asm/io.h>
32 #include <asm/gpio.h>
33 #include <asm/arch/iomux-mx51.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
38
39 #include "../common/karo.h"
40
41 #define TX51_FEC_RST_GPIO       IMX_GPIO_NR(2, 14)
42 #define TX51_FEC_PWR_GPIO       IMX_GPIO_NR(1, 3)
43 #define TX51_FEC_INT_GPIO       IMX_GPIO_NR(3, 18)
44 #define TX51_LED_GPIO           IMX_GPIO_NR(4, 10)
45
46 #define TX51_LCD_PWR_GPIO       IMX_GPIO_NR(4, 14)
47 #define TX51_LCD_RST_GPIO       IMX_GPIO_NR(4, 13)
48 #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
49
50 #define TX51_RESET_OUT_GPIO     IMX_GPIO_NR(2, 15)
51
52 DECLARE_GLOBAL_DATA_PTR;
53
54 #define IOMUX_SION              IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
55
56 #define FEC_PAD_CTRL            MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
57                                         PAD_CTL_SRE_FAST)
58 #define FEC_PAD_CTRL2           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
59 #define GPIO_PAD_CTRL           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
60
61 static iomux_v3_cfg_t tx51_pads[] = {
62         /* NAND flash pads are set up in lowlevel_init.S */
63
64         /* RESET_OUT */
65         MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
66
67         /* UART pads */
68 #if CONFIG_MXC_UART_BASE == UART1_BASE
69         MX51_PAD_UART1_RXD__UART1_RXD,
70         MX51_PAD_UART1_TXD__UART1_TXD,
71         MX51_PAD_UART1_RTS__UART1_RTS,
72         MX51_PAD_UART1_CTS__UART1_CTS,
73 #endif
74 #if CONFIG_MXC_UART_BASE == UART2_BASE
75         MX51_PAD_UART2_RXD__UART2_RXD,
76         MX51_PAD_UART2_TXD__UART2_TXD,
77         MX51_PAD_EIM_D26__UART2_RTS,
78         MX51_PAD_EIM_D25__UART2_CTS,
79 #endif
80 #if CONFIG_MXC_UART_BASE == UART3_BASE
81         MX51_PAD_UART3_RXD__UART3_RXD,
82         MX51_PAD_UART3_TXD__UART3_TXD,
83         MX51_PAD_EIM_D18__UART3_RTS,
84         MX51_PAD_EIM_D17__UART3_CTS,
85 #endif
86         /* internal I2C */
87         MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
88         MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
89
90         /* FEC PHY GPIO functions */
91         MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL,    /* PHY POWER */
92         MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL,   /* PHY RESET */
93         MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
94
95         /* FEC functions */
96         MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
97         MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
98         MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
99         MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
100         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
101         MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
102         MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
103         MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
104         MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
105         MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
106
107         /* strap pins for PHY configuration */
108         MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
109         MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL,  /* RXD0/Mode0 */
110         MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL,   /* RXD1/Mode1 */
111         MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL,   /* RXD2/Mode2 */
112         MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL,   /* RXD3/nINTSEL */
113         MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
114         MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL,   /* CRS/PHYAD4 */
115
116         /* unusable pins on TX51 */
117         MX51_PAD_GPIO1_0__GPIO1_0,
118         MX51_PAD_GPIO1_1__GPIO1_1,
119 };
120
121 static const struct gpio tx51_gpios[] = {
122         /* RESET_OUT */
123         { TX51_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "RESET_OUT", },
124
125         /* FEC PHY control GPIOs */
126         { TX51_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
127         { TX51_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
128         { TX51_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },      /* PHY INT (TX_ER) */
129
130         /* FEC PHY strap pins */
131         { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY REGOFF", },  /* RX_CLK/REGOFF */
132         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE0", },   /* RXD0/Mode0 */
133         { IMX_GPIO_NR(2, 23), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE1", },   /* RXD1/Mode1 */
134         { IMX_GPIO_NR(2, 27), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE2", },   /* RXD2/Mode2 */
135         { IMX_GPIO_NR(2, 28), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
136         { IMX_GPIO_NR(3, 10), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RMII", },         /* COL/RMII/CRSDV */
137         { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", },  /* CRS/PHYAD4 */
138
139         /* module internal I2C bus */
140         { IMX_GPIO_NR(4, 17), GPIOFLAG_INPUT, "I2C1 SDA", },
141         { IMX_GPIO_NR(4, 16), GPIOFLAG_INPUT, "I2C1 SCL", },
142
143         /* Unconnected pins */
144         { IMX_GPIO_NR(1, 0), GPIOFLAG_OUTPUT_INIT_LOW, "N/C", },
145         { IMX_GPIO_NR(1, 1), GPIOFLAG_OUTPUT_INIT_LOW, "N/C", },
146 };
147
148 /*
149  * Functions
150  */
151 /* placed in section '.data' to prevent overwriting relocation info
152  * overlayed with bss
153  */
154 static u32 wrsr __attribute__((section(".data")));
155
156 #define WRSR_POR        (1 << 4)
157 #define WRSR_TOUT       (1 << 1)
158 #define WRSR_SFTW       (1 << 0)
159
160 static void print_reset_cause(void)
161 {
162         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
163         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
164         u32 srsr;
165         char *dlm = "";
166
167         printf("Reset cause: ");
168
169         srsr = readl(&src_regs->srsr);
170         wrsr = readw(wdt_base + 4);
171
172         if (wrsr & WRSR_POR) {
173                 printf("%sPOR", dlm);
174                 dlm = " | ";
175         }
176         if (srsr & 0x00004) {
177                 printf("%sCSU", dlm);
178                 dlm = " | ";
179         }
180         if (srsr & 0x00008) {
181                 printf("%sIPP USER", dlm);
182                 dlm = " | ";
183         }
184         if (srsr & 0x00010) {
185                 if (wrsr & WRSR_SFTW) {
186                         printf("%sSOFT", dlm);
187                         dlm = " | ";
188                 }
189                 if (wrsr & WRSR_TOUT) {
190                         printf("%sWDOG", dlm);
191                         dlm = " | ";
192                 }
193         }
194         if (srsr & 0x00020) {
195                 printf("%sJTAG HIGH-Z", dlm);
196                 dlm = " | ";
197         }
198         if (srsr & 0x00040) {
199                 printf("%sJTAG SW", dlm);
200                 dlm = " | ";
201         }
202         if (srsr & 0x10000) {
203                 printf("%sWARM BOOT", dlm);
204                 dlm = " | ";
205         }
206         if (dlm[0] == '\0')
207                 printf("unknown");
208
209         printf("\n");
210 }
211
212 static void tx51_print_cpuinfo(void)
213 {
214         u32 cpurev;
215
216         cpurev = get_cpu_rev();
217
218         printf("CPU:   Freescale i.MX51 rev%d.%d at %d MHz\n",
219                 (cpurev & 0x000F0) >> 4,
220                 (cpurev & 0x0000F) >> 0,
221                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
222
223         print_reset_cause();
224 }
225
226 int board_early_init_f(void)
227 {
228         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
229
230         gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
231         imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
232
233         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
234         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
235
236         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
237         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
238         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
239         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
240         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
241
242         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
243         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
244
245         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
246         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
247         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
248         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
249         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
250
251         writel(0xffcfffff, &ccm_regs->CCGR0);
252         writel(0x003fffff, &ccm_regs->CCGR1);
253         writel(0x030c003c, &ccm_regs->CCGR2);
254         writel(0x000000ff, &ccm_regs->CCGR3);
255         writel(0x00000000, &ccm_regs->CCGR4);
256         writel(0x003fc003, &ccm_regs->CCGR5);
257         writel(0x00000000, &ccm_regs->CCGR6);
258         writel(0x00000000, &ccm_regs->cmeor);
259 #ifdef CONFIG_CMD_BOOTCE
260         /* WinCE fails to enable these clocks */
261         writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
262         writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
263         writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
264 #endif
265         return 0;
266 }
267
268 int board_init(void)
269 {
270         /* Address of boot parameters */
271         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
272
273         if (ctrlc() || (wrsr & WRSR_TOUT)) {
274                 if (wrsr & WRSR_TOUT)
275                         printf("WDOG RESET detected\n");
276                 else
277                         printf("<CTRL-C> detected; safeboot enabled\n");
278                 return 1;
279         }
280         return 0;
281 }
282
283 int dram_init(void)
284 {
285         int ret;
286
287         /* dram_init must store complete ramsize in gd->ram_size */
288         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
289                                 PHYS_SDRAM_1_SIZE);
290
291         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
292                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
293         if (ret)
294                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
295                         CONFIG_SYS_SDRAM_CLK, ret);
296         else
297                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
298                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
299                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
300                         CONFIG_SYS_SDRAM_CLK);
301         return ret;
302 }
303
304 void dram_init_banksize(void)
305 {
306         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
307         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
308                         PHYS_SDRAM_1_SIZE);
309 #if CONFIG_NR_DRAM_BANKS > 1
310         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
311         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
312                         PHYS_SDRAM_2_SIZE);
313 #endif
314 }
315
316 #ifdef  CONFIG_CMD_MMC
317 static const iomux_v3_cfg_t mmc0_pads[] = {
318         MX51_PAD_SD1_CMD__SD1_CMD,
319         MX51_PAD_SD1_CLK__SD1_CLK,
320         MX51_PAD_SD1_DATA0__SD1_DATA0,
321         MX51_PAD_SD1_DATA1__SD1_DATA1,
322         MX51_PAD_SD1_DATA2__SD1_DATA2,
323         MX51_PAD_SD1_DATA3__SD1_DATA3,
324         /* SD1 CD */
325         MX51_PAD_DISPB2_SER_RS__GPIO3_8 | GPIO_PAD_CTRL,
326 };
327
328 static const iomux_v3_cfg_t mmc1_pads[] = {
329         MX51_PAD_SD2_CMD__SD2_CMD,
330         MX51_PAD_SD2_CLK__SD2_CLK,
331         MX51_PAD_SD2_DATA0__SD2_DATA0,
332         MX51_PAD_SD2_DATA1__SD2_DATA1,
333         MX51_PAD_SD2_DATA2__SD2_DATA2,
334         MX51_PAD_SD2_DATA3__SD2_DATA3,
335         /* SD2 CD */
336         MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | GPIO_PAD_CTRL,
337 };
338
339 static struct tx51_esdhc_cfg {
340         const iomux_v3_cfg_t *pads;
341         int num_pads;
342         struct fsl_esdhc_cfg cfg;
343         int cd_gpio;
344 } tx51_esdhc_cfg[] = {
345         {
346                 .pads = mmc0_pads,
347                 .num_pads = ARRAY_SIZE(mmc0_pads),
348                 .cfg = {
349                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
350                         .max_bus_width = 4,
351                 },
352                 .cd_gpio = IMX_GPIO_NR(3, 8),
353         },
354         {
355                 .pads = mmc1_pads,
356                 .num_pads = ARRAY_SIZE(mmc1_pads),
357                 .cfg = {
358                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
359                         .max_bus_width = 4,
360                 },
361                 .cd_gpio = IMX_GPIO_NR(3, 6),
362         },
363 };
364
365 static inline struct tx51_esdhc_cfg *to_tx51_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
366 {
367         return container_of(cfg, struct tx51_esdhc_cfg, cfg);
368 }
369
370 int board_mmc_getcd(struct mmc *mmc)
371 {
372         struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv);
373
374         if (cfg->cd_gpio < 0)
375                 return cfg->cd_gpio;
376
377         debug("SD card %d is %spresent\n",
378                 cfg - tx51_esdhc_cfg,
379                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
380         return !gpio_get_value(cfg->cd_gpio);
381 }
382
383 int board_mmc_init(bd_t *bis)
384 {
385         int i;
386
387         for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) {
388                 struct mmc *mmc;
389                 struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
390                 int ret;
391
392                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
393                                                 cfg->num_pads);
394                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
395
396                 ret = gpio_request_one(cfg->cd_gpio,
397                                 GPIOFLAG_INPUT, "MMC CD");
398                 if (ret) {
399                         printf("Error %d requesting GPIO%d_%d\n",
400                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
401                         continue;
402                 }
403
404                 debug("%s: Initializing MMC slot %d\n", __func__, i);
405                 fsl_esdhc_initialize(bis, &cfg->cfg);
406
407                 mmc = find_mmc_device(i);
408                 if (mmc == NULL)
409                         continue;
410                 if (board_mmc_getcd(mmc) > 0)
411                         mmc_init(mmc);
412         }
413         return 0;
414 }
415 #endif /* CONFIG_CMD_MMC */
416
417 #ifdef CONFIG_FEC_MXC
418
419 #ifndef ETH_ALEN
420 #define ETH_ALEN 6
421 #endif
422
423 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
424 {
425         int i;
426         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
427         struct fuse_bank *bank = &iim->bank[1];
428         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
429
430         if (dev_id > 0)
431                 return;
432
433         for (i = 0; i < ETH_ALEN; i++)
434                 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
435 }
436
437 static iomux_v3_cfg_t tx51_fec_pads[] = {
438         /* reconfigure strap pins for FEC function */
439         MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
440         MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
441         MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
442         MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
443         MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
444         MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
445         MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
446 };
447
448 /* take bit 4 of PHY address from configured PHY address or
449  * set it to 0 if PHYADDR is -1 (probe for PHY)
450  */
451 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
452
453 static struct gpio tx51_fec_gpios[] = {
454         { TX51_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
455         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode0", },    /* RXD0/Mode0 */
456         { IMX_GPIO_NR(2, 23), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode1", },    /* RXD1/Mode1 */
457         { IMX_GPIO_NR(2, 27), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode2", },    /* RXD2/Mode2 */
458         { IMX_GPIO_NR(2, 28), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", },  /* RXD3/nINTSEL */
459 #if PHYAD4
460         { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
461 #else
462         { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
463 #endif
464 };
465
466 int board_eth_init(bd_t *bis)
467 {
468         int ret;
469
470         /* Power up the external phy and assert strap options */
471         gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
472
473         /* delay at least 21ms for the PHY internal POR signal to deassert */
474         udelay(22000);
475
476         /* Deassert RESET to the external phy */
477         gpio_set_value(TX51_FEC_RST_GPIO, 1);
478
479         /*
480          * Due to an RC-filter in the PHY RESET line, a minimum
481          * delay of 535us is required to let the RESET line rise
482          * above the logic high threshold of the PHY input pin.
483          */
484         udelay(550);
485         imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
486                                         ARRAY_SIZE(tx51_fec_pads));
487
488         ret = cpu_eth_init(bis);
489         if (ret)
490                 printf("cpu_eth_init() failed: %d\n", ret);
491
492         return ret;
493 }
494 #endif /* CONFIG_FEC_MXC */
495
496 enum {
497         LED_STATE_INIT = -1,
498         LED_STATE_OFF,
499         LED_STATE_ON,
500 };
501
502 void show_activity(int arg)
503 {
504         static int led_state = LED_STATE_INIT;
505         static ulong last;
506
507         if (led_state == LED_STATE_INIT) {
508                 last = get_timer(0);
509                 gpio_set_value(TX51_LED_GPIO, 1);
510                 led_state = LED_STATE_ON;
511         } else {
512                 if (get_timer(last) > CONFIG_SYS_HZ) {
513                         last = get_timer(0);
514                         if (led_state == LED_STATE_ON) {
515                                 gpio_set_value(TX51_LED_GPIO, 0);
516                         } else {
517                                 gpio_set_value(TX51_LED_GPIO, 1);
518                         }
519                         led_state = 1 - led_state;
520                 }
521         }
522 }
523
524 static const iomux_v3_cfg_t stk5_pads[] = {
525         /* SW controlled LED on STK5 baseboard */
526         MX51_PAD_CSI2_D13__GPIO4_10 | GPIO_PAD_CTRL,
527
528         /* USB PHY reset */
529         MX51_PAD_GPIO1_4__GPIO1_4 | GPIO_PAD_CTRL,
530         /* USBOTG OC */
531         MX51_PAD_GPIO1_6__GPIO1_6 | GPIO_PAD_CTRL,
532         /* USB PHY clock enable */
533         MX51_PAD_GPIO1_7__GPIO1_7 | GPIO_PAD_CTRL,
534         /* USBH1 VBUS enable */
535         MX51_PAD_GPIO1_8__GPIO1_8 | GPIO_PAD_CTRL,
536         /* USBH1 OC */
537         MX51_PAD_GPIO1_9__GPIO1_9 | GPIO_PAD_CTRL,
538 };
539
540 static const struct gpio stk5_gpios[] = {
541         { TX51_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
542
543         { IMX_GPIO_NR(1, 4), GPIOFLAG_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
544         { IMX_GPIO_NR(1, 6), GPIOFLAG_INPUT, "USBOTG OC", },
545         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "ULPI PHY reset", },
546         { IMX_GPIO_NR(1, 8), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
547         { IMX_GPIO_NR(1, 9), GPIOFLAG_INPUT, "USBH1 OC", },
548 };
549
550 #ifdef CONFIG_LCD
551 static u16 tx51_cmap[256];
552 vidinfo_t panel_info = {
553         /* set to max. size supported by SoC */
554         .vl_col = 1600,
555         .vl_row = 1200,
556
557         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
558         .cmap = tx51_cmap,
559 };
560
561 static struct fb_videomode tx51_fb_modes[] = {
562         {
563                 /* Standard VGA timing */
564                 .name           = "VGA",
565                 .refresh        = 60,
566                 .xres           = 640,
567                 .yres           = 480,
568                 .pixclock       = KHZ2PICOS(25175),
569                 .left_margin    = 48,
570                 .hsync_len      = 96,
571                 .right_margin   = 16,
572                 .upper_margin   = 31,
573                 .vsync_len      = 2,
574                 .lower_margin   = 12,
575                 .sync           = FB_SYNC_CLK_LAT_FALL,
576         },
577         {
578                 /* Emerging ETV570 640 x 480 display. Syncs low active,
579                  * DE high active, 115.2 mm x 86.4 mm display area
580                  * VGA compatible timing
581                  */
582                 .name           = "ETV570",
583                 .refresh        = 60,
584                 .xres           = 640,
585                 .yres           = 480,
586                 .pixclock       = KHZ2PICOS(25175),
587                 .left_margin    = 114,
588                 .hsync_len      = 30,
589                 .right_margin   = 16,
590                 .upper_margin   = 32,
591                 .vsync_len      = 3,
592                 .lower_margin   = 10,
593                 .sync           = FB_SYNC_CLK_LAT_FALL,
594         },
595         {
596                 /* Emerging ET0350G0DH6 320 x 240 display.
597                  * 70.08 mm x 52.56 mm display area.
598                  */
599                 .name           = "ET0350",
600                 .refresh        = 60,
601                 .xres           = 320,
602                 .yres           = 240,
603                 .pixclock       = KHZ2PICOS(6500),
604                 .left_margin    = 68 - 34,
605                 .hsync_len      = 34,
606                 .right_margin   = 20,
607                 .upper_margin   = 18 - 3,
608                 .vsync_len      = 3,
609                 .lower_margin   = 4,
610                 .sync           = FB_SYNC_CLK_LAT_FALL,
611         },
612         {
613                 /* Emerging ET0430G0DH6 480 x 272 display.
614                  * 95.04 mm x 53.856 mm display area.
615                  */
616                 .name           = "ET0430",
617                 .refresh        = 60,
618                 .xres           = 480,
619                 .yres           = 272,
620                 .pixclock       = KHZ2PICOS(9000),
621                 .left_margin    = 2,
622                 .hsync_len      = 41,
623                 .right_margin   = 2,
624                 .upper_margin   = 2,
625                 .vsync_len      = 10,
626                 .lower_margin   = 2,
627                 .sync           = FB_SYNC_CLK_LAT_FALL,
628         },
629         {
630                 /* Emerging ET0500G0DH6 800 x 480 display.
631                  * 109.6 mm x 66.4 mm display area.
632                  */
633                 .name           = "ET0500",
634                 .refresh        = 60,
635                 .xres           = 800,
636                 .yres           = 480,
637                 .pixclock       = KHZ2PICOS(33260),
638                 .left_margin    = 216 - 128,
639                 .hsync_len      = 128,
640                 .right_margin   = 1056 - 800 - 216,
641                 .upper_margin   = 35 - 2,
642                 .vsync_len      = 2,
643                 .lower_margin   = 525 - 480 - 35,
644                 .sync           = FB_SYNC_CLK_LAT_FALL,
645         },
646         {
647                 /* Emerging ETQ570G0DH6 320 x 240 display.
648                  * 115.2 mm x 86.4 mm display area.
649                  */
650                 .name           = "ETQ570",
651                 .refresh        = 60,
652                 .xres           = 320,
653                 .yres           = 240,
654                 .pixclock       = KHZ2PICOS(6400),
655                 .left_margin    = 38,
656                 .hsync_len      = 30,
657                 .right_margin   = 30,
658                 .upper_margin   = 16, /* 15 according to datasheet */
659                 .vsync_len      = 3, /* TVP -> 1>x>5 */
660                 .lower_margin   = 4, /* 4.5 according to datasheet */
661                 .sync           = FB_SYNC_CLK_LAT_FALL,
662         },
663         {
664                 /* Emerging ET0700G0DH6 800 x 480 display.
665                  * 152.4 mm x 91.44 mm display area.
666                  */
667                 .name           = "ET0700",
668                 .refresh        = 60,
669                 .xres           = 800,
670                 .yres           = 480,
671                 .pixclock       = KHZ2PICOS(33260),
672                 .left_margin    = 216 - 128,
673                 .hsync_len      = 128,
674                 .right_margin   = 1056 - 800 - 216,
675                 .upper_margin   = 35 - 2,
676                 .vsync_len      = 2,
677                 .lower_margin   = 525 - 480 - 35,
678                 .sync           = FB_SYNC_CLK_LAT_FALL,
679         },
680         {
681                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
682                 .refresh        = 60,
683                 .left_margin    = 48,
684                 .hsync_len      = 96,
685                 .right_margin   = 16,
686                 .upper_margin   = 31,
687                 .vsync_len      = 2,
688                 .lower_margin   = 12,
689                 .sync           = FB_SYNC_CLK_LAT_FALL,
690         },
691 };
692
693 static int lcd_enabled = 1;
694 static int lcd_bl_polarity;
695
696 static int lcd_backlight_polarity(void)
697 {
698         return lcd_bl_polarity;
699 }
700
701 void lcd_enable(void)
702 {
703         /* HACK ALERT:
704          * global variable from common/lcd.c
705          * Set to 0 here to prevent messages from going to LCD
706          * rather than serial console
707          */
708         lcd_is_enabled = 0;
709
710         if (lcd_enabled) {
711                 karo_load_splashimage(1);
712
713                 debug("Switching LCD on\n");
714                 gpio_set_value(TX51_LCD_PWR_GPIO, 1);
715                 udelay(100);
716                 gpio_set_value(TX51_LCD_RST_GPIO, 1);
717                 udelay(300000);
718                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
719                         lcd_backlight_polarity());
720         }
721 }
722
723 void lcd_disable(void)
724 {
725         if (lcd_enabled) {
726                 printf("Disabling LCD\n");
727                 ipuv3_fb_shutdown();
728         }
729 }
730
731 void lcd_panel_disable(void)
732 {
733         if (lcd_enabled) {
734                 debug("Switching LCD off\n");
735                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
736                         !lcd_backlight_polarity());
737                 gpio_set_value(TX51_LCD_RST_GPIO, 0);
738                 gpio_set_value(TX51_LCD_PWR_GPIO, 0);
739         }
740 }
741
742 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
743         /* LCD RESET */
744         MX51_PAD_CSI2_VSYNC__GPIO4_13,
745         /* LCD POWER_ENABLE */
746         MX51_PAD_CSI2_HSYNC__GPIO4_14,
747         /* LCD Backlight (PWM) */
748         MX51_PAD_GPIO1_2__GPIO1_2,
749
750         /* Display */
751         MX51_PAD_DISP1_DAT0__DISP1_DAT0,
752         MX51_PAD_DISP1_DAT1__DISP1_DAT1,
753         MX51_PAD_DISP1_DAT2__DISP1_DAT2,
754         MX51_PAD_DISP1_DAT3__DISP1_DAT3,
755         MX51_PAD_DISP1_DAT4__DISP1_DAT4,
756         MX51_PAD_DISP1_DAT5__DISP1_DAT5,
757         MX51_PAD_DISP1_DAT6__DISP1_DAT6,
758         MX51_PAD_DISP1_DAT7__DISP1_DAT7,
759         MX51_PAD_DISP1_DAT8__DISP1_DAT8,
760         MX51_PAD_DISP1_DAT9__DISP1_DAT9,
761         MX51_PAD_DISP1_DAT10__DISP1_DAT10,
762         MX51_PAD_DISP1_DAT11__DISP1_DAT11,
763         MX51_PAD_DISP1_DAT12__DISP1_DAT12,
764         MX51_PAD_DISP1_DAT13__DISP1_DAT13,
765         MX51_PAD_DISP1_DAT14__DISP1_DAT14,
766         MX51_PAD_DISP1_DAT15__DISP1_DAT15,
767         MX51_PAD_DISP1_DAT16__DISP1_DAT16,
768         MX51_PAD_DISP1_DAT17__DISP1_DAT17,
769         MX51_PAD_DISP1_DAT18__DISP1_DAT18,
770         MX51_PAD_DISP1_DAT19__DISP1_DAT19,
771         MX51_PAD_DISP1_DAT20__DISP1_DAT20,
772         MX51_PAD_DISP1_DAT21__DISP1_DAT21,
773         MX51_PAD_DISP1_DAT22__DISP1_DAT22,
774         MX51_PAD_DISP1_DAT23__DISP1_DAT23,
775         MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
776         MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
777 };
778
779 static const struct gpio stk5_lcd_gpios[] = {
780         { TX51_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
781         { TX51_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
782         { TX51_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
783 };
784
785 void lcd_ctrl_init(void *lcdbase)
786 {
787         int color_depth = 24;
788         const char *video_mode = karo_get_vmode(getenv("video_mode"));
789         const char *vm;
790         unsigned long val;
791         int refresh = 60;
792         struct fb_videomode *p = &tx51_fb_modes[0];
793         struct fb_videomode fb_mode;
794         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
795         int pix_fmt;
796         int lcd_bus_width;
797         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
798         unsigned long di_clk_rate = 65000000;
799
800         if (!lcd_enabled) {
801                 debug("LCD disabled\n");
802                 return;
803         }
804
805         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
806                 debug("Disabling LCD\n");
807                 lcd_enabled = 0;
808                 setenv("splashimage", NULL);
809                 return;
810         }
811
812         karo_fdt_move_fdt();
813         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
814
815         if (video_mode == NULL) {
816                 debug("Disabling LCD\n");
817                 lcd_enabled = 0;
818                 return;
819         }
820         vm = video_mode;
821         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
822                 p = &fb_mode;
823                 debug("Using video mode from FDT\n");
824                 vm += strlen(vm);
825                 if (fb_mode.xres > panel_info.vl_col ||
826                         fb_mode.yres > panel_info.vl_row) {
827                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
828                                 fb_mode.xres, fb_mode.yres,
829                                 panel_info.vl_col, panel_info.vl_row);
830                         lcd_enabled = 0;
831                         return;
832                 }
833         }
834         if (p->name != NULL)
835                 debug("Trying compiled-in video modes\n");
836         while (p->name != NULL) {
837                 if (strcmp(p->name, vm) == 0) {
838                         debug("Using video mode: '%s'\n", p->name);
839                         vm += strlen(vm);
840                         break;
841                 }
842                 p++;
843         }
844         if (*vm != '\0')
845                 debug("Trying to decode video_mode: '%s'\n", vm);
846         while (*vm != '\0') {
847                 if (*vm >= '0' && *vm <= '9') {
848                         char *end;
849
850                         val = simple_strtoul(vm, &end, 0);
851                         if (end > vm) {
852                                 if (!xres_set) {
853                                         if (val > panel_info.vl_col)
854                                                 val = panel_info.vl_col;
855                                         p->xres = val;
856                                         panel_info.vl_col = val;
857                                         xres_set = 1;
858                                 } else if (!yres_set) {
859                                         if (val > panel_info.vl_row)
860                                                 val = panel_info.vl_row;
861                                         p->yres = val;
862                                         panel_info.vl_row = val;
863                                         yres_set = 1;
864                                 } else if (!bpp_set) {
865                                         switch (val) {
866                                         case 8:
867                                         case 16:
868                                         case 24:
869                                         case 32:
870                                                 color_depth = val;
871                                                 break;
872
873                                         default:
874                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
875                                                         end - vm, vm, color_depth);
876                                         }
877                                         bpp_set = 1;
878                                 } else if (!refresh_set) {
879                                         refresh = val;
880                                         refresh_set = 1;
881                                 }
882                         }
883                         vm = end;
884                 }
885                 switch (*vm) {
886                 case '@':
887                         bpp_set = 1;
888                         /* fallthru */
889                 case '-':
890                         yres_set = 1;
891                         /* fallthru */
892                 case 'x':
893                         xres_set = 1;
894                         /* fallthru */
895                 case 'M':
896                 case 'R':
897                         vm++;
898                         break;
899
900                 default:
901                         if (*vm != '\0')
902                                 vm++;
903                 }
904         }
905         if (p->xres == 0 || p->yres == 0) {
906                 printf("Invalid video mode: %s\n", getenv("video_mode"));
907                 lcd_enabled = 0;
908                 printf("Supported video modes are:");
909                 for (p = &tx51_fb_modes[0]; p->name != NULL; p++) {
910                         printf(" %s", p->name);
911                 }
912                 printf("\n");
913                 return;
914         }
915         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
916                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
917                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
918                 lcd_enabled = 0;
919                 return;
920         }
921         panel_info.vl_col = p->xres;
922         panel_info.vl_row = p->yres;
923
924         switch (color_depth) {
925         case 8:
926                 panel_info.vl_bpix = LCD_COLOR8;
927                 break;
928         case 16:
929                 panel_info.vl_bpix = LCD_COLOR16;
930                 break;
931         default:
932                 panel_info.vl_bpix = LCD_COLOR32;
933         }
934
935         p->pixclock = KHZ2PICOS(refresh *
936                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
937                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
938                                 1000);
939         debug("Pixel clock set to %lu.%03lu MHz\n",
940                 PICOS2KHZ(p->pixclock) / 1000,
941                 PICOS2KHZ(p->pixclock) % 1000);
942
943         if (p != &fb_mode) {
944                 int ret;
945
946                 debug("Creating new display-timing node from '%s'\n",
947                         video_mode);
948                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
949                 if (ret)
950                         printf("Failed to create new display-timing node from '%s': %d\n",
951                                 video_mode, ret);
952         }
953
954         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
955         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
956                                         ARRAY_SIZE(stk5_lcd_pads));
957
958         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
959         switch (lcd_bus_width) {
960         case 24:
961                 pix_fmt = IPU_PIX_FMT_RGB24;
962                 break;
963
964         case 18:
965                 pix_fmt = IPU_PIX_FMT_RGB666;
966                 break;
967
968         case 16:
969                 pix_fmt = IPU_PIX_FMT_RGB565;
970                 break;
971
972         default:
973                 lcd_enabled = 0;
974                 printf("Invalid LCD bus width: %d\n", lcd_bus_width);
975                 return;
976         }
977         if (karo_load_splashimage(0) == 0) {
978                 int ret;
979                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
980                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
981
982                 /* MIPI HSC clock is required for initialization */
983                 writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
984
985                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3DEX;
986
987                 debug("Initializing LCD controller\n");
988                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
989                 writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
990                 if (ret) {
991                         printf("Failed to initialize FB driver: %d\n", ret);
992                         lcd_enabled = 0;
993                 }
994         } else {
995                 debug("Skipping initialization of LCD controller\n");
996         }
997 }
998 #else
999 #define lcd_enabled 0
1000 #endif /* CONFIG_LCD */
1001
1002 static void stk5_board_init(void)
1003 {
1004         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1005         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1006 }
1007
1008 static void stk5v3_board_init(void)
1009 {
1010         stk5_board_init();
1011 }
1012
1013 static void tx51_set_cpu_clock(void)
1014 {
1015         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1016
1017         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1018                 return;
1019
1020         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1021                 return;
1022
1023         if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1024                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1025                 printf("CPU clock set to %lu.%03lu MHz\n",
1026                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1027         } else {
1028                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1029         }
1030 }
1031
1032 static void tx51_init_mac(void)
1033 {
1034         u8 mac[ETH_ALEN];
1035
1036         imx_get_mac_from_fuse(0, mac);
1037         if (!is_valid_ethaddr(mac)) {
1038                 printf("No valid MAC address programmed\n");
1039                 return;
1040         }
1041
1042         printf("MAC addr from fuse: %pM\n", mac);
1043         eth_setenv_enetaddr("ethaddr", mac);
1044 }
1045
1046 int board_late_init(void)
1047 {
1048         int ret = 0;
1049         const char *baseboard;
1050
1051         env_cleanup();
1052
1053         tx51_set_cpu_clock();
1054
1055         if (had_ctrlc())
1056                 setenv_ulong("safeboot", 1);
1057         else if (wrsr & WRSR_TOUT)
1058                 setenv_ulong("wdreset", 1);
1059         else
1060                 karo_fdt_move_fdt();
1061
1062         baseboard = getenv("baseboard");
1063         if (!baseboard)
1064                 goto exit;
1065
1066         printf("Baseboard: %s\n", baseboard);
1067
1068         if (strncmp(baseboard, "stk5", 4) == 0) {
1069                 if ((strlen(baseboard) == 4) ||
1070                         strcmp(baseboard, "stk5-v3") == 0) {
1071                         stk5v3_board_init();
1072                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1073                         printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
1074                                 baseboard);
1075                         stk5v3_board_init();
1076                 } else {
1077                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1078                                 baseboard + 4);
1079                 }
1080         } else {
1081                 printf("WARNING: Unsupported baseboard: '%s'\n",
1082                         baseboard);
1083                 ret = -EINVAL;
1084         }
1085
1086 exit:
1087         tx51_init_mac();
1088
1089         gpio_set_value(TX51_RESET_OUT_GPIO, 1);
1090         clear_ctrlc();
1091         return ret;
1092 }
1093
1094 int checkboard(void)
1095 {
1096         tx51_print_cpuinfo();
1097 #if CONFIG_NR_DRAM_BANKS > 1
1098         printf("Board: Ka-Ro TX51-8xx1 | TX51-8xx2\n");
1099 #else
1100         printf("Board: Ka-Ro TX51-8xx0\n");
1101 #endif
1102         return 0;
1103 }
1104
1105 #if defined(CONFIG_OF_BOARD_SETUP)
1106 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1107 #include <jffs2/jffs2.h>
1108 #include <mtd_node.h>
1109 static struct node_info nodes[] = {
1110         { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
1111 };
1112 #else
1113 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1114 #endif
1115
1116 static const char *tx51_touchpanels[] = {
1117         "ti,tsc2007",
1118         "edt,edt-ft5x06",
1119 };
1120
1121 int ft_board_setup(void *blob, bd_t *bd)
1122 {
1123         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1124         int ret;
1125
1126         ret = fdt_increase_size(blob, 4096);
1127         if (ret) {
1128                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1129                 return ret;
1130         }
1131         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1132
1133         karo_fdt_fixup_touchpanel(blob, tx51_touchpanels,
1134                                 ARRAY_SIZE(tx51_touchpanels));
1135         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1136         karo_fdt_update_fb_mode(blob, video_mode);
1137
1138         return 0;
1139 }
1140 #endif /* CONFIG_OF_BOARD_SETUP */