2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <fsl_esdhc.h>
29 #include <fdt_support.h>
30 #include <asm/string.h>
33 #include <asm/arch/iomux-mx51.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/sys_proto.h>
38 #if !defined(CONFIG_TX51_80x0) && !defined(CONFIG_TX51_80x1) && !defined(CONFIG_TX51_80x2)
39 #error TX51 model not selected
44 #define IMX_GPIO_NR(p, o) ((((p) - 1) << 5) | (o))
46 #define TX51_FEC_RESET_GPIO IMX_GPIO_NR(2, 14)
47 #define TX51_FEC_POWER_GPIO IMX_GPIO_NR(1, 3)
48 #define TX51_LED_GPIO IMX_GPIO_NR(4, 10)
50 DECLARE_GLOBAL_DATA_PTR;
55 static void print_reset_cause(void)
58 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
59 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
62 printf("Reset cause: ");
64 srsr = readl(&src_regs->srsr);
74 printf("%sIPP USER", dlm);
78 u32 wrsr = readw(wdt_base + 4);
79 if (wrsr & (1 << 0)) {
80 printf("%sSOFT", dlm);
83 if (wrsr & (1 << 1)) {
84 printf("%sWDOG", dlm);
89 printf("%sJTAG HIGH-Z", dlm);
93 printf("%sJTAG SW", dlm);
97 printf("%sWARM BOOT", dlm);
106 static void print_cpuinfo(void)
110 cpurev = get_cpu_rev();
112 printf("CPU: Freescale i.MX51 rev%d.%d at %d MHz\n",
113 (cpurev & 0x000F0) >> 4,
114 (cpurev & 0x0000F) >> 0,
115 mxc_get_clock(MXC_ARM_CLK) / 1000000);
120 int board_early_init_f(void)
122 #ifdef CONFIG_USB_EHCI_MX5
125 writel(0xffffffff, 0x73fd4068);
126 writel(0xffffffff, 0x73fd406c);
127 writel(0xffffffff, 0x73fd4070);
128 writel(0xffffffff, 0x73fd4074);
129 writel(0xffffffff, 0x73fd4078);
130 writel(0xffffffff, 0x73fd407c);
131 writel(0xffffffff, 0x73fd4080);
132 writel(0xffffffff, 0x73fd4084);
136 void coloured_LED_init(void)
139 gpio_set_value(TX51_LED_GPIO, 0);
144 /* Address of boot parameters */
145 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
153 /* dram_init must store complete ramsize in gd->ram_size */
154 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
157 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
158 CONFIG_SYS_SDRAM_CLOCK, MXC_DDR_CLK);
160 printf("%s: Failed to set DDR clock to %uMHz: %d\n", __func__,
161 CONFIG_SYS_SDRAM_CLOCK, ret);
163 debug("%s: DDR clock set to %u.%03uMHz (desig.: %u.000MHz)\n",
164 __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
165 mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
166 CONFIG_SYS_SDRAM_CLOCK);
170 void dram_init_banksize(void)
172 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
173 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
175 #if CONFIG_NR_DRAM_BANKS > 1
176 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
177 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
182 #ifdef CONFIG_CMD_MMC
183 int board_mmc_getcd(struct mmc *mmc)
185 struct fsl_esdhc_cfg *cfg = mmc->priv;
187 if (cfg->cd_gpio < 0)
190 return !gpio_get_value(cfg->cd_gpio);
193 static struct fsl_esdhc_cfg esdhc_cfg[] = {
195 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
197 .cd_gpio = IMX_GPIO_NR(3, 8),
201 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
203 .cd_gpio = IMX_GPIO_NR(3, 6),
208 static const iomux_v3_cfg_t mmc0_pads[] = {
209 MX51_PAD_SD1_CMD__SD1_CMD,
210 MX51_PAD_SD1_CLK__SD1_CLK,
211 MX51_PAD_SD1_DATA0__SD1_DATA0,
212 MX51_PAD_SD1_DATA1__SD1_DATA1,
213 MX51_PAD_SD1_DATA2__SD1_DATA2,
214 MX51_PAD_SD1_DATA3__SD1_DATA3,
216 MX51_PAD_DISPB2_SER_RS__GPIO3_8 |
217 MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE),
220 static const iomux_v3_cfg_t mmc1_pads[] = {
221 MX51_PAD_SD2_CMD__SD2_CMD,
222 MX51_PAD_SD2_CLK__SD2_CLK,
223 MX51_PAD_SD2_DATA0__SD2_DATA0,
224 MX51_PAD_SD2_DATA1__SD2_DATA1,
225 MX51_PAD_SD2_DATA2__SD2_DATA2,
226 MX51_PAD_SD2_DATA3__SD2_DATA3,
228 MX51_PAD_DISPB2_SER_DIO__GPIO3_6 |
229 MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE),
233 const iomux_v3_cfg_t *pads;
235 } mmc_pad_config[] = {
236 { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
237 { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
240 int board_mmc_init(bd_t *bis)
244 for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
247 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
249 mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
250 mmc_pad_config[i].count);
251 fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
252 mmc = find_mmc_device(i);
255 if (board_mmc_getcd(mmc) > 0)
260 #endif /* CONFIG_CMD_MMC */
262 #ifdef CONFIG_FEC_MXC
268 #define IOMUX_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
270 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
273 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
274 struct fuse_bank *bank = &iim->bank[1];
275 struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
280 for (i = 0; i < ETH_ALEN; i++)
281 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
284 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
286 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE | \
287 PAD_CTL_PUS_100K_UP | PAD_CTL_SRE_FAST)
288 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
290 static iomux_v3_cfg_t tx51_fec_gpio_pads[] = {
291 NEW_PAD_CTRL(MX51_PAD_NANDF_CS3__GPIO3_19, GPIO_PAD_CTL) | IOMUX_SION,
292 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__GPIO2_22, GPIO_PAD_CTL) | IOMUX_SION,
293 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, GPIO_PAD_CTL) | IOMUX_SION,
294 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__GPIO3_29, GPIO_PAD_CTL) | IOMUX_SION,
295 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, GPIO_PAD_CTL) | IOMUX_SION, /* RXD0/Mode0 */
296 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, GPIO_PAD_CTL) | IOMUX_SION, /* RXD1/Mode1 */
297 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, GPIO_PAD_CTL) | IOMUX_SION, /* RXD2/Mode2 */
298 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, GPIO_PAD_CTL) | IOMUX_SION, /* RXD3/nINTSEL */
299 NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, GPIO_PAD_CTL) | IOMUX_SION,
300 NEW_PAD_CTRL(MX51_PAD_NANDF_RDY_INT__GPIO3_24, GPIO_PAD_CTL) | IOMUX_SION,
301 NEW_PAD_CTRL(MX51_PAD_NANDF_CS7__GPIO3_23, GPIO_PAD_CTL) | IOMUX_SION,
302 NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, GPIO_PAD_CTL) | IOMUX_SION,
303 NEW_PAD_CTRL(MX51_PAD_NANDF_CS4__GPIO3_20, GPIO_PAD_CTL) | IOMUX_SION,
304 NEW_PAD_CTRL(MX51_PAD_NANDF_CS5__GPIO3_21, GPIO_PAD_CTL) | IOMUX_SION,
305 NEW_PAD_CTRL(MX51_PAD_NANDF_CS6__GPIO3_22, GPIO_PAD_CTL) | IOMUX_SION,
306 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, GPIO_PAD_CTL) | IOMUX_SION,
307 NEW_PAD_CTRL(MX51_PAD_EIM_CS5__GPIO2_30, GPIO_PAD_CTL) | IOMUX_SION,
308 NEW_PAD_CTRL(MX51_PAD_NANDF_CS2__GPIO3_18, GPIO_PAD_CTL) | IOMUX_SION, /* PHY INT */
309 NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, GPIO_PAD_CTL) | IOMUX_SION, /* PHY RESET */
310 NEW_PAD_CTRL(MX51_PAD_GPIO1_3__GPIO1_3, GPIO_PAD_CTL) | IOMUX_SION, /* PHY POWER */
313 static iomux_v3_cfg_t tx51_fec_pads[] = {
314 NEW_PAD_CTRL(MX51_PAD_NANDF_CS3__FEC_MDC, FEC_PAD_CTL),
315 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, FEC_PAD_CTL),
316 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, FEC_PAD_CTL2),
317 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, FEC_PAD_CTL2),
318 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__FEC_RDATA0, FEC_PAD_CTL2),
319 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, FEC_PAD_CTL2),
320 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, FEC_PAD_CTL2),
321 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, FEC_PAD_CTL2),
322 NEW_PAD_CTRL(MX51_PAD_EIM_CS4__FEC_RX_ER, FEC_PAD_CTL2),
323 NEW_PAD_CTRL(MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, FEC_PAD_CTL2),
324 NEW_PAD_CTRL(MX51_PAD_NANDF_CS7__FEC_TX_EN, FEC_PAD_CTL),
325 NEW_PAD_CTRL(MX51_PAD_NANDF_D8__FEC_TDATA0, FEC_PAD_CTL),
326 NEW_PAD_CTRL(MX51_PAD_NANDF_CS4__FEC_TDATA1, FEC_PAD_CTL),
327 NEW_PAD_CTRL(MX51_PAD_NANDF_CS5__FEC_TDATA2, FEC_PAD_CTL),
328 NEW_PAD_CTRL(MX51_PAD_NANDF_CS6__FEC_TDATA3, FEC_PAD_CTL),
329 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, FEC_PAD_CTL2),
330 NEW_PAD_CTRL(MX51_PAD_EIM_CS5__FEC_CRS, FEC_PAD_CTL),
331 NEW_PAD_CTRL(MX51_PAD_NANDF_CS2__GPIO3_18, GPIO_PAD_CTL),
332 NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, GPIO_PAD_CTL),
333 NEW_PAD_CTRL(MX51_PAD_GPIO1_3__GPIO1_3, GPIO_PAD_CTL),
340 } tx51_fec_gpios[] = {
341 { IMX_GPIO_NR(1, 3), 1, 0, }, /* PHY power */
342 { IMX_GPIO_NR(2, 14), 1, 0, }, /* PHY reset */
343 { IMX_GPIO_NR(3, 19), 1, 0, }, /* MDC */
344 { IMX_GPIO_NR(2, 22), 1, 0, }, /* MDIO */
345 { IMX_GPIO_NR(3, 11), 0, 1, }, /* RX_CLK */
346 { IMX_GPIO_NR(3, 29), 0, 0, }, /* RX_DV */
347 { IMX_GPIO_NR(3, 31), 1, 1, }, /* RXD0/Mode0 */
348 { IMX_GPIO_NR(2, 23), 1, 1, }, /* RXD1/Mode1 */
349 { IMX_GPIO_NR(2, 27), 1, 1, }, /* RXD2/Mode2 */
350 { IMX_GPIO_NR(2, 28), 1, 1, }, /* RXD3/nINTSEL */
351 { IMX_GPIO_NR(2, 29), 0, 0, }, /* RX_ER */
352 { IMX_GPIO_NR(3, 24), 0, 0, }, /* TX_CLK */
353 { IMX_GPIO_NR(3, 23), 1, 0, }, /* TX_EN */
354 { IMX_GPIO_NR(4, 0), 1, 0, }, /* TXD0 */
355 { IMX_GPIO_NR(3, 20), 1, 0, }, /* TXD1 */
356 { IMX_GPIO_NR(3, 21), 1, 0, }, /* TXD2 */
357 { IMX_GPIO_NR(3, 22), 1, 0, }, /* TXD3 */
358 { IMX_GPIO_NR(3, 10), 1, 0, }, /* COL */
359 { IMX_GPIO_NR(2, 30), 1, (CONFIG_FEC_MXC_PHYADDR >> 4) & 1, }, /* PHYAD4 */
360 { IMX_GPIO_NR(3, 18), 0, 1, }, /* PHY INT (TX_ER) */
363 int board_eth_init(bd_t *bis)
366 unsigned char mac[ETH_ALEN];
367 char mac_str[ETH_ALEN * 3] = "";
370 for (i = 0; i < ARRAY_SIZE(tx51_fec_gpios); i++) {
371 int gpio = tx51_fec_gpios[i].gpio;
373 debug("Setting GPIO%d_%d as output LOW\n",
374 gpio / 32 + 1, gpio % 32);
375 gpio_direction_output(gpio, 0);
377 mxc_iomux_v3_setup_multiple_pads(tx51_fec_gpio_pads,
378 ARRAY_SIZE(tx51_fec_gpio_pads));
380 /* Power on the external phy */
381 gpio_direction_output(TX51_FEC_POWER_GPIO, 1);
385 for (i = 0; i < ARRAY_SIZE(tx51_fec_gpios); i++) {
386 int gpio = tx51_fec_gpios[i].gpio;
387 int dir = tx51_fec_gpios[i].dir;
388 int val = tx51_fec_gpios[i].val;
391 gpio_direction_output(gpio, val);
393 gpio_direction_input(gpio);
399 /* Deassert RESET to the external phy */
400 gpio_set_value(TX51_FEC_RESET_GPIO, 1);
404 mxc_iomux_v3_setup_multiple_pads(tx51_fec_pads,
405 ARRAY_SIZE(tx51_fec_pads));
407 ret = cpu_eth_init(bis);
409 printf("cpu_eth_init() failed: %d\n", ret);
412 imx_get_mac_from_fuse(0, mac);
413 snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
414 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
415 setenv("ethaddr", mac_str);
419 #endif /* CONFIG_FEC_MXC */
427 void show_activity(int arg)
429 static int led_state = LED_STATE_INIT;
432 if (led_state == LED_STATE_INIT) {
434 gpio_set_value(TX51_LED_GPIO, 1);
435 led_state = LED_STATE_ON;
437 if (get_timer(last) > CONFIG_SYS_HZ) {
439 if (led_state == LED_STATE_ON) {
440 gpio_set_value(TX51_LED_GPIO, 0);
442 gpio_set_value(TX51_LED_GPIO, 1);
444 led_state = 1 - led_state;
449 static const iomux_v3_cfg_t stk5_pads[] = {
451 MX51_PAD_CSI2_D13__GPIO4_10,
453 MX51_PAD_CSI2_VSYNC__GPIO4_13,
454 /* LCD POWER_ENABLE */
455 MX51_PAD_CSI2_HSYNC__GPIO4_14,
456 /* LCD Backlight (PWM) */
457 MX51_PAD_GPIO1_2__GPIO1_2,
462 GPIOF_OUTPUT_INIT_LOW,
463 GPIOF_OUTPUT_INIT_HIGH,
468 enum gpio_flags flags;
472 static const struct gpio stk5_gpios[] = {
473 { IMX_GPIO_NR(4, 10), GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
474 { IMX_GPIO_NR(4, 13), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
475 { IMX_GPIO_NR(4, 14), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
476 { IMX_GPIO_NR(1, 2), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
479 static int gpio_request_array(const struct gpio *gp, int count)
484 for (i = 0; i < count; i++) {
485 ret = gpio_request(gp[i].gpio, gp[i].label);
489 if (gp[i].flags == GPIOF_INPUT)
490 gpio_direction_input(gp[i].gpio);
491 else if (gp[i].flags == GPIOF_OUTPUT_INIT_LOW)
492 gpio_direction_output(gp[i].gpio, 0);
493 else if (gp[i].flags == GPIOF_OUTPUT_INIT_HIGH)
494 gpio_direction_output(gp[i].gpio, 1);
500 gpio_free(gp[i].gpio);
505 static void stk5_board_init(void)
507 mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
508 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
511 static void stk5v3_board_init(void)
516 static void stk5v5_board_init(void)
521 static void tx51_move_fdt(void)
523 unsigned long fdt_addr = getenv_ulong("fdtcontroladdr", 16, 0);
526 #ifdef CONFIG_OF_EMBED
527 fdt = _binary_dt_dtb_start;
528 #elif defined CONFIG_OF_SEPARATE
529 fdt = (void *)(_end_ofs + _TEXT_BASE);
531 if (fdt && fdt_addr != 0) {
532 if (fdt_check_header(fdt) == 0) {
533 size_t fdt_len = fdt_totalsize(fdt);
535 memmove((void *)fdt_addr, fdt, fdt_len);
537 printf("ERROR: No valid FDT found at %p\n", fdt);
542 int board_late_init(void)
544 const char *baseboard;
546 baseboard = getenv("baseboard");
550 if (strncmp(baseboard, "stk5", 4) == 0) {
551 printf("Baseboard: %s\n", baseboard);
552 if ((strlen(baseboard) == 4) ||
553 strcmp(baseboard, "stk5-v3") == 0) {
555 } else if (strcmp(baseboard, "stk5-v5") == 0) {
558 printf("WARNING: Unsupported STK5 board rev.: %s\n",
562 printf("WARNING: Unsupported baseboard: '%s'\n",
573 printf("Board: Ka-Ro TX51\n");
579 unsigned long start = get_timer(0);
580 unsigned long last = gd->tbl;
581 unsigned long loop = 0;
582 unsigned long cnt = 0;
584 unsigned long elapsed = get_timer(start);
585 unsigned long diff = gd->tbl - last;
590 printf("loop %4lu: t=%08lx diff=%08lx steps=%5lu elapsed time: %lu",
591 loop, gd->tbl, diff, cnt, elapsed / CONFIG_SYS_HZ);
593 while (get_timer(start) < loop * CONFIG_SYS_HZ) {
604 #if defined(CONFIG_OF_BOARD_SETUP)
605 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
606 #include <jffs2/jffs2.h>
607 #include <mtd_node.h>
608 struct node_info nodes[] = {
609 { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
613 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
616 static const char *tx51_touchpanels[] = {
621 static void tx51_fixup_touchpanel(void *blob)
624 const char *model = getenv("touchpanel");
626 for (i = 0; i < ARRAY_SIZE(tx51_touchpanels); i++) {
628 const char *tp = tx51_touchpanels[i];
630 if (model != NULL && strcmp(model, tp) == 0)
633 tp = strchr(tp, ',');
634 if (tp != NULL && *tp != '\0' && strcmp(model, tp + 1) == 0)
637 offs = fdt_node_offset_by_compatible(blob, -1,
638 tx51_touchpanels[i]);
640 printf("node '%s' not found: %d\n",
641 tx51_touchpanels[i], offs);
644 printf("Removing node '%s' at offset %d\n",
645 tx51_touchpanels[i], offs);
646 fdt_del_node(blob, offs);
650 void ft_board_setup(void *blob, bd_t *bd)
652 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
653 fdt_fixup_ethernet(blob);
655 tx51_fixup_touchpanel(blob);