board/karo/tx51/tx51.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <lcd.h>
  24 #include <netdev.h>
  25 #include <mmc.h>
  26 #include <fsl_esdhc.h>
  27 #include <video_fb.h>
  28 #include <ipu.h>
  29 #include <mxcfb.h>
  30 #include <linux/fb.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/iomux-mx51.h>
  34 #include <asm/arch/clock.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40
  41 #define TX51_FEC_RST_GPIO       IMX_GPIO_NR(2, 14)
  42 #define TX51_FEC_PWR_GPIO       IMX_GPIO_NR(1, 3)
  43 #define TX51_FEC_INT_GPIO       IMX_GPIO_NR(3, 18)
  44 #define TX51_LED_GPIO           IMX_GPIO_NR(4, 10)
  45
  46 #define TX51_LCD_PWR_GPIO       IMX_GPIO_NR(4, 14)
  47 #define TX51_LCD_RST_GPIO       IMX_GPIO_NR(4, 13)
  48 #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
  49
  50 #define TX51_RESET_OUT_GPIO     IMX_GPIO_NR(2, 15)
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 #define IOMUX_SION              IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  55
  56 #define FEC_PAD_CTRL            MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
  57                                         PAD_CTL_SRE_FAST)
  58 #define FEC_PAD_CTRL2           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
  59 #define GPIO_PAD_CTRL           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
  60
  61 static iomux_v3_cfg_t tx51_pads[] = {
  62         /* NAND flash pads are set up in lowlevel_init.S */
  63
  64         /* RESET_OUT */
  65         MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
  66
  67         /* UART pads */
  68 #if CONFIG_MXC_UART_BASE == UART1_BASE
  69         MX51_PAD_UART1_RXD__UART1_RXD,
  70         MX51_PAD_UART1_TXD__UART1_TXD,
  71         MX51_PAD_UART1_RTS__UART1_RTS,
  72         MX51_PAD_UART1_CTS__UART1_CTS,
  73 #endif
  74 #if CONFIG_MXC_UART_BASE == UART2_BASE
  75         MX51_PAD_UART2_RXD__UART2_RXD,
  76         MX51_PAD_UART2_TXD__UART2_TXD,
  77         MX51_PAD_EIM_D26__UART2_RTS,
  78         MX51_PAD_EIM_D25__UART2_CTS,
  79 #endif
  80 #if CONFIG_MXC_UART_BASE == UART3_BASE
  81         MX51_PAD_UART3_RXD__UART3_RXD,
  82         MX51_PAD_UART3_TXD__UART3_TXD,
  83         MX51_PAD_EIM_D18__UART3_RTS,
  84         MX51_PAD_EIM_D17__UART3_CTS,
  85 #endif
  86         /* internal I2C */
  87         MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
  88         MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
  89
  90         /* FEC PHY GPIO functions */
  91         MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL,    /* PHY POWER */
  92         MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL,   /* PHY RESET */
  93         MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
  94
  95         /* FEC functions */
  96         MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
  97         MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
  98         MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
  99         MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
 100         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
 101         MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
 102         MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
 103         MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
 104         MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
 105         MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
 106
 107         /* strap pins for PHY configuration */
 108         MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
 109         MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL,  /* RXD0/Mode0 */
 110         MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL,   /* RXD1/Mode1 */
 111         MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL,   /* RXD2/Mode2 */
 112         MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL,   /* RXD3/nINTSEL */
 113         MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
 114         MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL,   /* CRS/PHYAD4 */
 115
 116         /* unusable pins on TX51 */
 117         MX51_PAD_GPIO1_0__GPIO1_0,
 118         MX51_PAD_GPIO1_1__GPIO1_1,
 119 };
 120
 121 static const struct gpio tx51_gpios[] = {
 122         /* RESET_OUT */
 123         { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
 124
 125         /* FEC PHY control GPIOs */
 126         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
 127         { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
 128         { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },         /* PHY INT (TX_ER) */
 129
 130         /* FEC PHY strap pins */
 131         { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", },  /* RX_CLK/REGOFF */
 132         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", },   /* RXD0/Mode0 */
 133         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", },   /* RXD1/Mode1 */
 134         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", },   /* RXD2/Mode2 */
 135         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
 136         { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", },    /* COL/RMII/CRSDV */
 137         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", },  /* CRS/PHYAD4 */
 138
 139         /* module internal I2C bus */
 140         { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
 141         { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
 142
 143         /* Unconnected pins */
 144         { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 145         { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 146 };
 147
 148 /*
 149  * Functions
 150  */
 151 /* placed in section '.data' to prevent overwriting relocation info
 152  * overlayed with bss
 153  */
 154 static u32 wrsr __attribute__((section(".data")));
 155
 156 #define WRSR_POR        (1 << 4)
 157 #define WRSR_TOUT       (1 << 1)
 158 #define WRSR_SFTW       (1 << 0)
 159
 160 static void print_reset_cause(void)
 161 {
 162         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 163         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 164         u32 srsr;
 165         char *dlm = "";
 166
 167         printf("Reset cause: ");
 168
 169         srsr = readl(&src_regs->srsr);
 170         wrsr = readw(wdt_base + 4);
 171
 172         if (wrsr & WRSR_POR) {
 173                 printf("%sPOR", dlm);
 174                 dlm = " | ";
 175         }
 176         if (srsr & 0x00004) {
 177                 printf("%sCSU", dlm);
 178                 dlm = " | ";
 179         }
 180         if (srsr & 0x00008) {
 181                 printf("%sIPP USER", dlm);
 182                 dlm = " | ";
 183         }
 184         if (srsr & 0x00010) {
 185                 if (wrsr & WRSR_SFTW) {
 186                         printf("%sSOFT", dlm);
 187                         dlm = " | ";
 188                 }
 189                 if (wrsr & WRSR_TOUT) {
 190                         printf("%sWDOG", dlm);
 191                         dlm = " | ";
 192                 }
 193         }
 194         if (srsr & 0x00020) {
 195                 printf("%sJTAG HIGH-Z", dlm);
 196                 dlm = " | ";
 197         }
 198         if (srsr & 0x00040) {
 199                 printf("%sJTAG SW", dlm);
 200                 dlm = " | ";
 201         }
 202         if (srsr & 0x10000) {
 203                 printf("%sWARM BOOT", dlm);
 204                 dlm = " | ";
 205         }
 206         if (dlm[0] == '\0')
 207                 printf("unknown");
 208
 209         printf("\n");
 210 }
 211
 212 static void tx51_print_cpuinfo(void)
 213 {
 214         u32 cpurev;
 215
 216         cpurev = get_cpu_rev();
 217
 218         printf("CPU:   Freescale i.MX51 rev%d.%d at %d MHz\n",
 219                 (cpurev & 0x000F0) >> 4,
 220                 (cpurev & 0x0000F) >> 0,
 221                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 222
 223         print_reset_cause();
 224 }
 225
 226 int board_early_init_f(void)
 227 {
 228         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 229
 230         gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
 231         imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
 232
 233         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 234         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 235
 236         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 237         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 238         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 239         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 240         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 241
 242         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 243         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 244
 245         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 246         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 247         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 248         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 249         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 250
 251         writel(0xffcffffc, &ccm_regs->CCGR0);
 252         writel(0x003fffff, &ccm_regs->CCGR1);
 253         writel(0x030c003c, &ccm_regs->CCGR2);
 254         writel(0x000000ff, &ccm_regs->CCGR3);
 255         writel(0x00000000, &ccm_regs->CCGR4);
 256         writel(0x003fc003, &ccm_regs->CCGR5);
 257         writel(0x00000000, &ccm_regs->CCGR6);
 258         writel(0x00000000, &ccm_regs->cmeor);
 259 #ifdef CONFIG_CMD_BOOTCE
 260         /* WinCE fails to enable these clocks */
 261         writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
 262         writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
 263         writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
 264 #endif
 265         return 0;
 266 }
 267
 268 int board_init(void)
 269 {
 270         /* Address of boot parameters */
 271         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 272         return 0;
 273 }
 274
 275 int dram_init(void)
 276 {
 277         int ret;
 278
 279         /* dram_init must store complete ramsize in gd->ram_size */
 280         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 281                                 PHYS_SDRAM_1_SIZE);
 282
 283         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 284                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 285         if (ret)
 286                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 287                         CONFIG_SYS_SDRAM_CLK, ret);
 288         else
 289                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 290                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 291                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 292                         CONFIG_SYS_SDRAM_CLK);
 293         return ret;
 294 }
 295
 296 void dram_init_banksize(void)
 297 {
 298         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 299         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 300                         PHYS_SDRAM_1_SIZE);
 301 #if CONFIG_NR_DRAM_BANKS > 1
 302         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 303         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 304                         PHYS_SDRAM_2_SIZE);
 305 #endif
 306 }
 307
 308 #ifdef  CONFIG_CMD_MMC
 309 static const iomux_v3_cfg_t mmc0_pads[] = {
 310         MX51_PAD_SD1_CMD__SD1_CMD,
 311         MX51_PAD_SD1_CLK__SD1_CLK,
 312         MX51_PAD_SD1_DATA0__SD1_DATA0,
 313         MX51_PAD_SD1_DATA1__SD1_DATA1,
 314         MX51_PAD_SD1_DATA2__SD1_DATA2,
 315         MX51_PAD_SD1_DATA3__SD1_DATA3,
 316         /* SD1 CD */
 317         MX51_PAD_DISPB2_SER_RS__GPIO3_8 | GPIO_PAD_CTRL,
 318 };
 319
 320 static const iomux_v3_cfg_t mmc1_pads[] = {
 321         MX51_PAD_SD2_CMD__SD2_CMD,
 322         MX51_PAD_SD2_CLK__SD2_CLK,
 323         MX51_PAD_SD2_DATA0__SD2_DATA0,
 324         MX51_PAD_SD2_DATA1__SD2_DATA1,
 325         MX51_PAD_SD2_DATA2__SD2_DATA2,
 326         MX51_PAD_SD2_DATA3__SD2_DATA3,
 327         /* SD2 CD */
 328         MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | GPIO_PAD_CTRL,
 329 };
 330
 331 static struct tx51_esdhc_cfg {
 332         const iomux_v3_cfg_t *pads;
 333         int num_pads;
 334         struct fsl_esdhc_cfg cfg;
 335         int cd_gpio;
 336 } tx51_esdhc_cfg[] = {
 337         {
 338                 .pads = mmc0_pads,
 339                 .num_pads = ARRAY_SIZE(mmc0_pads),
 340                 .cfg = {
 341                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 342                         .max_bus_width = 4,
 343                 },
 344                 .cd_gpio = IMX_GPIO_NR(3, 8),
 345         },
 346         {
 347                 .pads = mmc1_pads,
 348                 .num_pads = ARRAY_SIZE(mmc1_pads),
 349                 .cfg = {
 350                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 351                         .max_bus_width = 4,
 352                 },
 353                 .cd_gpio = IMX_GPIO_NR(3, 6),
 354         },
 355 };
 356
 357 #define to_tx51_esdhc_cfg(p) container_of(p, struct tx51_esdhc_cfg, cfg)
 358
 359 int board_mmc_getcd(struct mmc *mmc)
 360 {
 361         struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv);
 362
 363         if (cfg->cd_gpio < 0)
 364                 return cfg->cd_gpio;
 365
 366         debug("SD card %d is %spresent\n",
 367                 cfg - tx51_esdhc_cfg,
 368                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 369         return !gpio_get_value(cfg->cd_gpio);
 370 }
 371
 372 int board_mmc_init(bd_t *bis)
 373 {
 374         int i;
 375
 376         for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) {
 377                 struct mmc *mmc;
 378                 struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
 379                 int ret;
 380
 381                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 382                         break;
 383
 384                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 385                                                 cfg->num_pads);
 386                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 387
 388                 fsl_esdhc_initialize(bis, &cfg->cfg);
 389
 390                 ret = gpio_request_one(cfg->cd_gpio,
 391                                 GPIOF_INPUT, "MMC CD");
 392                 if (ret) {
 393                         printf("Error %d requesting GPIO%d_%d\n",
 394                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 395                         continue;
 396                 }
 397
 398                 mmc = find_mmc_device(i);
 399                 if (mmc == NULL)
 400                         continue;
 401                 if (board_mmc_getcd(mmc) > 0)
 402                         mmc_init(mmc);
 403         }
 404         return 0;
 405 }
 406 #endif /* CONFIG_CMD_MMC */
 407
 408 #ifdef CONFIG_FEC_MXC
 409
 410 #ifndef ETH_ALEN
 411 #define ETH_ALEN 6
 412 #endif
 413
 414 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 415 {
 416         int i;
 417         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 418         struct fuse_bank *bank = &iim->bank[1];
 419         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 420
 421         if (dev_id > 0)
 422                 return;
 423
 424         for (i = 0; i < ETH_ALEN; i++)
 425                 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
 426 }
 427
 428 static iomux_v3_cfg_t tx51_fec_pads[] = {
 429         /* reconfigure strap pins for FEC function */
 430         MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
 431         MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
 432         MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
 433         MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
 434         MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
 435         MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
 436         MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
 437 };
 438
 439 /* take bit 4 of PHY address from configured PHY address or
 440  * set it to 0 if PHYADDR is -1 (probe for PHY)
 441  */
 442 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
 443
 444 static struct gpio tx51_fec_gpios[] = {
 445         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
 446         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", },       /* RXD0/Mode0 */
 447         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", },       /* RXD1/Mode1 */
 448         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", },       /* RXD2/Mode2 */
 449         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", },     /* RXD3/nINTSEL */
 450 #if PHYAD4
 451         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 452 #else
 453         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 454 #endif
 455 };
 456
 457 int board_eth_init(bd_t *bis)
 458 {
 459         int ret;
 460
 461         /* Power up the external phy and assert strap options */
 462         gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
 463
 464         /* delay at least 21ms for the PHY internal POR signal to deassert */
 465         udelay(22000);
 466
 467         /* Deassert RESET to the external phy */
 468         gpio_set_value(TX51_FEC_RST_GPIO, 1);
 469
 470         /* Without this delay the PHY won't work, though nothing in
 471          * the datasheets suggests that it should be necessary!
 472          */
 473         udelay(400);
 474         imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
 475                                         ARRAY_SIZE(tx51_fec_pads));
 476
 477         ret = cpu_eth_init(bis);
 478         if (ret)
 479                 printf("cpu_eth_init() failed: %d\n", ret);
 480         return ret;
 481 }
 482 #endif /* CONFIG_FEC_MXC */
 483
 484 enum {
 485         LED_STATE_INIT = -1,
 486         LED_STATE_OFF,
 487         LED_STATE_ON,
 488 };
 489
 490 void show_activity(int arg)
 491 {
 492         static int led_state = LED_STATE_INIT;
 493         static ulong last;
 494
 495         if (led_state == LED_STATE_INIT) {
 496                 last = get_timer(0);
 497                 gpio_set_value(TX51_LED_GPIO, 1);
 498                 led_state = LED_STATE_ON;
 499         } else {
 500                 if (get_timer(last) > CONFIG_SYS_HZ) {
 501                         last = get_timer(0);
 502                         if (led_state == LED_STATE_ON) {
 503                                 gpio_set_value(TX51_LED_GPIO, 0);
 504                         } else {
 505                                 gpio_set_value(TX51_LED_GPIO, 1);
 506                         }
 507                         led_state = 1 - led_state;
 508                 }
 509         }
 510 }
 511
 512 static const iomux_v3_cfg_t stk5_pads[] = {
 513         /* SW controlled LED on STK5 baseboard */
 514         MX51_PAD_CSI2_D13__GPIO4_10 | GPIO_PAD_CTRL,
 515
 516         /* USB PHY reset */
 517         MX51_PAD_GPIO1_4__GPIO1_4 | GPIO_PAD_CTRL,
 518         /* USBOTG OC */
 519         MX51_PAD_GPIO1_6__GPIO1_6 | GPIO_PAD_CTRL,
 520         /* USB PHY clock enable */
 521         MX51_PAD_GPIO1_7__GPIO1_7 | GPIO_PAD_CTRL,
 522         /* USBH1 VBUS enable */
 523         MX51_PAD_GPIO1_8__GPIO1_8 | GPIO_PAD_CTRL,
 524         /* USBH1 OC */
 525         MX51_PAD_GPIO1_9__GPIO1_9 | GPIO_PAD_CTRL,
 526 };
 527
 528 static const struct gpio stk5_gpios[] = {
 529         { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 530
 531         { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
 532         { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
 533         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
 534         { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 535         { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
 536 };
 537
 538 #ifdef CONFIG_LCD
 539 vidinfo_t panel_info = {
 540         /* set to max. size supported by SoC */
 541         .vl_col = 1600,
 542         .vl_row = 1200,
 543
 544         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 545 };
 546
 547 static struct fb_videomode tx51_fb_modes[] = {
 548         {
 549                 /* Standard VGA timing */
 550                 .name           = "VGA",
 551                 .refresh        = 60,
 552                 .xres           = 640,
 553                 .yres           = 480,
 554                 .pixclock       = KHZ2PICOS(25175),
 555                 .left_margin    = 48,
 556                 .hsync_len      = 96,
 557                 .right_margin   = 16,
 558                 .upper_margin   = 31,
 559                 .vsync_len      = 2,
 560                 .lower_margin   = 12,
 561                 .sync           = FB_SYNC_CLK_LAT_FALL,
 562         },
 563         {
 564                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 565                  * DE high active, 115.2 mm x 86.4 mm display area
 566                  * VGA compatible timing
 567                  */
 568                 .name           = "ETV570",
 569                 .refresh        = 60,
 570                 .xres           = 640,
 571                 .yres           = 480,
 572                 .pixclock       = KHZ2PICOS(25175),
 573                 .left_margin    = 114,
 574                 .hsync_len      = 30,
 575                 .right_margin   = 16,
 576                 .upper_margin   = 32,
 577                 .vsync_len      = 3,
 578                 .lower_margin   = 10,
 579                 .sync           = FB_SYNC_CLK_LAT_FALL,
 580         },
 581         {
 582                 /* Emerging ET0350G0DH6 320 x 240 display.
 583                  * 70.08 mm x 52.56 mm display area.
 584                  */
 585                 .name           = "ET0350",
 586                 .refresh        = 60,
 587                 .xres           = 320,
 588                 .yres           = 240,
 589                 .pixclock       = KHZ2PICOS(6500),
 590                 .left_margin    = 68 - 34,
 591                 .hsync_len      = 34,
 592                 .right_margin   = 20,
 593                 .upper_margin   = 18 - 3,
 594                 .vsync_len      = 3,
 595                 .lower_margin   = 4,
 596                 .sync           = FB_SYNC_CLK_LAT_FALL,
 597         },
 598         {
 599                 /* Emerging ET0430G0DH6 480 x 272 display.
 600                  * 95.04 mm x 53.856 mm display area.
 601                  */
 602                 .name           = "ET0430",
 603                 .refresh        = 60,
 604                 .xres           = 480,
 605                 .yres           = 272,
 606                 .pixclock       = KHZ2PICOS(9000),
 607                 .left_margin    = 2,
 608                 .hsync_len      = 41,
 609                 .right_margin   = 2,
 610                 .upper_margin   = 2,
 611                 .vsync_len      = 10,
 612                 .lower_margin   = 2,
 613                 .sync           = FB_SYNC_CLK_LAT_FALL,
 614         },
 615         {
 616                 /* Emerging ET0500G0DH6 800 x 480 display.
 617                  * 109.6 mm x 66.4 mm display area.
 618                  */
 619                 .name           = "ET0500",
 620                 .refresh        = 60,
 621                 .xres           = 800,
 622                 .yres           = 480,
 623                 .pixclock       = KHZ2PICOS(33260),
 624                 .left_margin    = 216 - 128,
 625                 .hsync_len      = 128,
 626                 .right_margin   = 1056 - 800 - 216,
 627                 .upper_margin   = 35 - 2,
 628                 .vsync_len      = 2,
 629                 .lower_margin   = 525 - 480 - 35,
 630                 .sync           = FB_SYNC_CLK_LAT_FALL,
 631         },
 632         {
 633                 /* Emerging ETQ570G0DH6 320 x 240 display.
 634                  * 115.2 mm x 86.4 mm display area.
 635                  */
 636                 .name           = "ETQ570",
 637                 .refresh        = 60,
 638                 .xres           = 320,
 639                 .yres           = 240,
 640                 .pixclock       = KHZ2PICOS(6400),
 641                 .left_margin    = 38,
 642                 .hsync_len      = 30,
 643                 .right_margin   = 30,
 644                 .upper_margin   = 16, /* 15 according to datasheet */
 645                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 646                 .lower_margin   = 4, /* 4.5 according to datasheet */
 647                 .sync           = FB_SYNC_CLK_LAT_FALL,
 648         },
 649         {
 650                 /* Emerging ET0700G0DH6 800 x 480 display.
 651                  * 152.4 mm x 91.44 mm display area.
 652                  */
 653                 .name           = "ET0700",
 654                 .refresh        = 60,
 655                 .xres           = 800,
 656                 .yres           = 480,
 657                 .pixclock       = KHZ2PICOS(33260),
 658                 .left_margin    = 216 - 128,
 659                 .hsync_len      = 128,
 660                 .right_margin   = 1056 - 800 - 216,
 661                 .upper_margin   = 35 - 2,
 662                 .vsync_len      = 2,
 663                 .lower_margin   = 525 - 480 - 35,
 664                 .sync           = FB_SYNC_CLK_LAT_FALL,
 665         },
 666         {
 667                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 668                 .refresh        = 60,
 669                 .left_margin    = 48,
 670                 .hsync_len      = 96,
 671                 .right_margin   = 16,
 672                 .upper_margin   = 31,
 673                 .vsync_len      = 2,
 674                 .lower_margin   = 12,
 675                 .sync           = FB_SYNC_CLK_LAT_FALL,
 676         },
 677 };
 678
 679 static int lcd_enabled = 1;
 680 static int lcd_bl_polarity;
 681
 682 static int lcd_backlight_polarity(void)
 683 {
 684         return lcd_bl_polarity;
 685 }
 686
 687 void lcd_enable(void)
 688 {
 689         /* HACK ALERT:
 690          * global variable from common/lcd.c
 691          * Set to 0 here to prevent messages from going to LCD
 692          * rather than serial console
 693          */
 694         lcd_is_enabled = 0;
 695
 696         if (lcd_enabled) {
 697                 karo_load_splashimage(1);
 698
 699                 debug("Switching LCD on\n");
 700                 gpio_set_value(TX51_LCD_PWR_GPIO, 1);
 701                 udelay(100);
 702                 gpio_set_value(TX51_LCD_RST_GPIO, 1);
 703                 udelay(300000);
 704                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
 705                         lcd_backlight_polarity());
 706         }
 707 }
 708
 709 void lcd_disable(void)
 710 {
 711         if (lcd_enabled) {
 712                 printf("Disabling LCD\n");
 713                 ipuv3_fb_shutdown();
 714         }
 715 }
 716
 717 void lcd_panel_disable(void)
 718 {
 719         if (lcd_enabled) {
 720                 debug("Switching LCD off\n");
 721                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
 722                         !lcd_backlight_polarity());
 723                 gpio_set_value(TX51_LCD_RST_GPIO, 0);
 724                 gpio_set_value(TX51_LCD_PWR_GPIO, 0);
 725         }
 726 }
 727
 728 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 729         /* LCD RESET */
 730         MX51_PAD_CSI2_VSYNC__GPIO4_13,
 731         /* LCD POWER_ENABLE */
 732         MX51_PAD_CSI2_HSYNC__GPIO4_14,
 733         /* LCD Backlight (PWM) */
 734         MX51_PAD_GPIO1_2__GPIO1_2,
 735
 736         /* Display */
 737         MX51_PAD_DISP1_DAT0__DISP1_DAT0,
 738         MX51_PAD_DISP1_DAT1__DISP1_DAT1,
 739         MX51_PAD_DISP1_DAT2__DISP1_DAT2,
 740         MX51_PAD_DISP1_DAT3__DISP1_DAT3,
 741         MX51_PAD_DISP1_DAT4__DISP1_DAT4,
 742         MX51_PAD_DISP1_DAT5__DISP1_DAT5,
 743         MX51_PAD_DISP1_DAT6__DISP1_DAT6,
 744         MX51_PAD_DISP1_DAT7__DISP1_DAT7,
 745         MX51_PAD_DISP1_DAT8__DISP1_DAT8,
 746         MX51_PAD_DISP1_DAT9__DISP1_DAT9,
 747         MX51_PAD_DISP1_DAT10__DISP1_DAT10,
 748         MX51_PAD_DISP1_DAT11__DISP1_DAT11,
 749         MX51_PAD_DISP1_DAT12__DISP1_DAT12,
 750         MX51_PAD_DISP1_DAT13__DISP1_DAT13,
 751         MX51_PAD_DISP1_DAT14__DISP1_DAT14,
 752         MX51_PAD_DISP1_DAT15__DISP1_DAT15,
 753         MX51_PAD_DISP1_DAT16__DISP1_DAT16,
 754         MX51_PAD_DISP1_DAT17__DISP1_DAT17,
 755         MX51_PAD_DISP1_DAT18__DISP1_DAT18,
 756         MX51_PAD_DISP1_DAT19__DISP1_DAT19,
 757         MX51_PAD_DISP1_DAT20__DISP1_DAT20,
 758         MX51_PAD_DISP1_DAT21__DISP1_DAT21,
 759         MX51_PAD_DISP1_DAT22__DISP1_DAT22,
 760         MX51_PAD_DISP1_DAT23__DISP1_DAT23,
 761         MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
 762         MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
 763 };
 764
 765 static const struct gpio stk5_lcd_gpios[] = {
 766         { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 767         { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 768         { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 769 };
 770
 771 void lcd_ctrl_init(void *lcdbase)
 772 {
 773         int color_depth = 24;
 774         char *vm;
 775         unsigned long val;
 776         int refresh = 60;
 777         struct fb_videomode *p = &tx51_fb_modes[0];
 778         struct fb_videomode fb_mode;
 779         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 780         int pix_fmt = 0;
 781         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 782         unsigned long di_clk_rate = 65000000;
 783
 784         if (!lcd_enabled) {
 785                 debug("LCD disabled\n");
 786                 return;
 787         }
 788
 789         if (tstc() || (wrsr & WRSR_TOUT)) {
 790                 debug("Disabling LCD\n");
 791                 lcd_enabled = 0;
 792                 setenv("splashimage", NULL);
 793                 return;
 794         }
 795
 796         karo_fdt_move_fdt();
 797         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 798
 799         vm = getenv("video_mode");
 800         if (vm == NULL) {
 801                 debug("Disabling LCD\n");
 802                 lcd_enabled = 0;
 803                 return;
 804         }
 805         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 806                 p = &fb_mode;
 807                 debug("Using video mode from FDT\n");
 808                 vm += strlen(vm);
 809                 if (fb_mode.xres > panel_info.vl_col ||
 810                         fb_mode.yres > panel_info.vl_row) {
 811                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 812                                 fb_mode.xres, fb_mode.yres,
 813                                 panel_info.vl_col, panel_info.vl_row);
 814                         lcd_enabled = 0;
 815                         return;
 816                 }
 817         }
 818         if (p->name != NULL)
 819                 debug("Trying compiled-in video modes\n");
 820         while (p->name != NULL) {
 821                 if (strcmp(p->name, vm) == 0) {
 822                         debug("Using video mode: '%s'\n", p->name);
 823                         vm += strlen(vm);
 824                         break;
 825                 }
 826                 p++;
 827         }
 828         if (*vm != '\0')
 829                 debug("Trying to decode video_mode: '%s'\n", vm);
 830         while (*vm != '\0') {
 831                 if (*vm >= '0' && *vm <= '9') {
 832                         char *end;
 833
 834                         val = simple_strtoul(vm, &end, 0);
 835                         if (end > vm) {
 836                                 if (!xres_set) {
 837                                         if (val > panel_info.vl_col)
 838                                                 val = panel_info.vl_col;
 839                                         p->xres = val;
 840                                         panel_info.vl_col = val;
 841                                         xres_set = 1;
 842                                 } else if (!yres_set) {
 843                                         if (val > panel_info.vl_row)
 844                                                 val = panel_info.vl_row;
 845                                         p->yres = val;
 846                                         panel_info.vl_row = val;
 847                                         yres_set = 1;
 848                                 } else if (!bpp_set) {
 849                                         switch (val) {
 850                                         case 8:
 851                                         case 16:
 852                                         case 24:
 853                                         case 32:
 854                                                 color_depth = val;
 855                                                 break;
 856
 857                                         default:
 858                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 859                                                         end - vm, vm, color_depth);
 860                                         }
 861                                         bpp_set = 1;
 862                                 } else if (!refresh_set) {
 863                                         refresh = val;
 864                                         refresh_set = 1;
 865                                 }
 866                         }
 867                         vm = end;
 868                 }
 869                 switch (*vm) {
 870                 case '@':
 871                         bpp_set = 1;
 872                         /* fallthru */
 873                 case '-':
 874                         yres_set = 1;
 875                         /* fallthru */
 876                 case 'x':
 877                         xres_set = 1;
 878                         /* fallthru */
 879                 case 'M':
 880                 case 'R':
 881                         vm++;
 882                         break;
 883
 884                 default:
 885                         if (!pix_fmt) {
 886                                 char *tmp;
 887
 888                                 pix_fmt = IPU_PIX_FMT_RGB24;
 889                                 tmp = strchr(vm, ':');
 890                                 if (tmp)
 891                                         vm = tmp;
 892                         }
 893                         if (*vm != '\0')
 894                                 vm++;
 895                 }
 896         }
 897         if (p->xres == 0 || p->yres == 0) {
 898                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 899                 lcd_enabled = 0;
 900                 printf("Supported video modes are:");
 901                 for (p = &tx51_fb_modes[0]; p->name != NULL; p++) {
 902                         printf(" %s", p->name);
 903                 }
 904                 printf("\n");
 905                 return;
 906         }
 907         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 908                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 909                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 910                 lcd_enabled = 0;
 911                 return;
 912         }
 913         panel_info.vl_col = p->xres;
 914         panel_info.vl_row = p->yres;
 915
 916         switch (color_depth) {
 917         case 8:
 918                 panel_info.vl_bpix = LCD_COLOR8;
 919                 break;
 920         case 16:
 921                 panel_info.vl_bpix = LCD_COLOR16;
 922                 break;
 923         default:
 924                 panel_info.vl_bpix = LCD_COLOR24;
 925         }
 926
 927         p->pixclock = KHZ2PICOS(refresh *
 928                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 929                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 930                 / 1000);
 931         debug("Pixel clock set to %lu.%03lu MHz\n",
 932                 PICOS2KHZ(p->pixclock) / 1000,
 933                 PICOS2KHZ(p->pixclock) % 1000);
 934
 935         if (p != &fb_mode) {
 936                 int ret;
 937                 char *modename = getenv("video_mode");
 938
 939                 printf("Creating new display-timing node from '%s'\n",
 940                         modename);
 941                 ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
 942                 if (ret)
 943                         printf("Failed to create new display-timing node from '%s': %d\n",
 944                                 modename, ret);
 945         }
 946
 947         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 948         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 949                                         ARRAY_SIZE(stk5_lcd_pads));
 950
 951         debug("Initializing FB driver\n");
 952         if (!pix_fmt)
 953                 pix_fmt = IPU_PIX_FMT_RGB24;
 954
 955         if (karo_load_splashimage(0) == 0) {
 956                 int ret;
 957                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 958                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
 959
 960                 /* MIPI HSC clock is required for initialization */
 961                 writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
 962
 963                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3DEX;
 964
 965                 debug("Initializing LCD controller\n");
 966                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 967                 writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
 968                 if (ret) {
 969                         printf("Failed to initialize FB driver: %d\n", ret);
 970                         lcd_enabled = 0;
 971                 }
 972         } else {
 973                 debug("Skipping initialization of LCD controller\n");
 974         }
 975 }
 976 #else
 977 #define lcd_enabled 0
 978 #endif /* CONFIG_LCD */
 979
 980 static void stk5_board_init(void)
 981 {
 982         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 983         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 984 }
 985
 986 static void stk5v3_board_init(void)
 987 {
 988         stk5_board_init();
 989 }
 990
 991 static void tx51_set_cpu_clock(void)
 992 {
 993         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 994         int ret;
 995
 996         if (tstc() || (wrsr & WRSR_TOUT))
 997                 return;
 998
 999         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1000                 return;
1001
1002         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
1003         if (ret != 0) {
1004                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1005                 return;
1006         }
1007         printf("CPU clock set to %u.%03u MHz\n",
1008                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
1009                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
1010 }
1011
1012 static void tx51_init_mac(void)
1013 {
1014         u8 mac[ETH_ALEN];
1015
1016         imx_get_mac_from_fuse(0, mac);
1017         if (!is_valid_ether_addr(mac)) {
1018                 printf("No valid MAC address programmed\n");
1019                 return;
1020         }
1021
1022         eth_setenv_enetaddr("ethaddr", mac);
1023         printf("MAC addr from fuse: %pM\n", mac);
1024 }
1025
1026 int board_late_init(void)
1027 {
1028         int ret = 0;
1029         const char *baseboard;
1030
1031         tx51_set_cpu_clock();
1032         karo_fdt_move_fdt();
1033
1034         baseboard = getenv("baseboard");
1035         if (!baseboard)
1036                 goto exit;
1037
1038         if (strncmp(baseboard, "stk5", 4) == 0) {
1039                 printf("Baseboard: %s\n", baseboard);
1040                 if ((strlen(baseboard) == 4) ||
1041                         strcmp(baseboard, "stk5-v3") == 0) {
1042                         stk5v3_board_init();
1043                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1044                         printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
1045                                 baseboard);
1046                         stk5v3_board_init();
1047                 } else {
1048                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1049                                 baseboard + 4);
1050                 }
1051         } else {
1052                 printf("WARNING: Unsupported baseboard: '%s'\n",
1053                         baseboard);
1054                 ret = -EINVAL;
1055         }
1056
1057 exit:
1058         tx51_init_mac();
1059         gpio_set_value(TX51_RESET_OUT_GPIO, 1);
1060         return ret;
1061 }
1062
1063 int checkboard(void)
1064 {
1065         tx51_print_cpuinfo();
1066 #if CONFIG_NR_DRAM_BANKS > 1
1067         printf("Board: Ka-Ro TX51-8xx1 | TX51-8xx2\n");
1068 #else
1069         printf("Board: Ka-Ro TX51-8xx0\n");
1070 #endif
1071         return 0;
1072 }
1073
1074 #if defined(CONFIG_OF_BOARD_SETUP)
1075 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1076 #include <jffs2/jffs2.h>
1077 #include <mtd_node.h>
1078 struct node_info nodes[] = {
1079         { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
1080 };
1081
1082 #else
1083 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1084 #endif
1085
1086 static const char *tx51_touchpanels[] = {
1087         "ti,tsc2007",
1088         "edt,edt-ft5x06",
1089 };
1090
1091 void ft_board_setup(void *blob, bd_t *bd)
1092 {
1093         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1094         fdt_fixup_ethernet(blob);
1095
1096         karo_fdt_fixup_touchpanel(blob, tx51_touchpanels,
1097                                 ARRAY_SIZE(tx51_touchpanels));
1098         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1099         karo_fdt_update_fb_mode(blob, getenv("video_mode"));
1100 }
1101 #endif