karo: tx53: clear persistent bits in lpgr upon boot
[karo-tx-uboot.git] / board / karo / tx53 / tx53.c
1 /*
2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18
19 #include <common.h>
20 #include <errno.h>
21 #include <libfdt.h>
22 #include <fdt_support.h>
23 #include <i2c.h>
24 #include <lcd.h>
25 #include <netdev.h>
26 #include <mmc.h>
27 #include <fsl_esdhc.h>
28 #include <video_fb.h>
29 #include <ipu.h>
30 #include <mxcfb.h>
31 #include <linux/fb.h>
32 #include <asm/io.h>
33 #include <asm/gpio.h>
34 #include <asm/arch/iomux-mx53.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/crm_regs.h>
38 #include <asm/arch/sys_proto.h>
39
40 #include "../common/karo.h"
41
42 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
43 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
44 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
45 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
46
47 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
48 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
50
51 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
52
53 DECLARE_GLOBAL_DATA_PTR;
54
55 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
56                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
57
58 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
59                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
60
61 static iomux_v3_cfg_t tx53_pads[] = {
62         /* NAND flash pads are set up in lowlevel_init.S */
63
64         /* UART pads */
65 #if CONFIG_MXC_UART_BASE == UART1_BASE
66         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
67         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
68         MX53_PAD_PATA_IORDY__UART1_RTS,
69         MX53_PAD_PATA_RESET_B__UART1_CTS,
70 #endif
71 #if CONFIG_MXC_UART_BASE == UART2_BASE
72         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
73         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
74         MX53_PAD_PATA_DIOR__UART2_RTS,
75         MX53_PAD_PATA_INTRQ__UART2_CTS,
76 #endif
77 #if CONFIG_MXC_UART_BASE == UART3_BASE
78         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
79         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
80         MX53_PAD_PATA_DA_2__UART3_RTS,
81         MX53_PAD_PATA_DA_1__UART3_CTS,
82 #endif
83         /* internal I2C */
84         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
85         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
86
87         /* FEC PHY GPIO functions */
88         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
89         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
90         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
91
92         /* FEC functions */
93         MX53_PAD_FEC_MDC__FEC_MDC,
94         MX53_PAD_FEC_MDIO__FEC_MDIO,
95         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
96         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
97         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
98         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
99         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
100         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
101         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
102         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
103 };
104
105 static const struct gpio tx53_gpios[] = {
106         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
107         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
108         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
109         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
110 };
111
112 /*
113  * Functions
114  */
115 /* placed in section '.data' to prevent overwriting relocation info
116  * overlayed with bss
117  */
118 static u32 wrsr __attribute__((section(".data")));
119
120 #define WRSR_POR        (1 << 4)
121 #define WRSR_TOUT       (1 << 1)
122 #define WRSR_SFTW       (1 << 0)
123
124 static void print_reset_cause(void)
125 {
126         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
127         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
128         u32 srsr;
129         char *dlm = "";
130
131         printf("Reset cause: ");
132
133         srsr = readl(&src_regs->srsr);
134         wrsr = readw(wdt_base + 4);
135
136         if (wrsr & WRSR_POR) {
137                 printf("%sPOR", dlm);
138                 dlm = " | ";
139         }
140         if (srsr & 0x00004) {
141                 printf("%sCSU", dlm);
142                 dlm = " | ";
143         }
144         if (srsr & 0x00008) {
145                 printf("%sIPP USER", dlm);
146                 dlm = " | ";
147         }
148         if (srsr & 0x00010) {
149                 if (wrsr & WRSR_SFTW) {
150                         printf("%sSOFT", dlm);
151                         dlm = " | ";
152                 }
153                 if (wrsr & WRSR_TOUT) {
154                         printf("%sWDOG", dlm);
155                         dlm = " | ";
156                 }
157         }
158         if (srsr & 0x00020) {
159                 printf("%sJTAG HIGH-Z", dlm);
160                 dlm = " | ";
161         }
162         if (srsr & 0x00040) {
163                 printf("%sJTAG SW", dlm);
164                 dlm = " | ";
165         }
166         if (srsr & 0x10000) {
167                 printf("%sWARM BOOT", dlm);
168                 dlm = " | ";
169         }
170         if (dlm[0] == '\0')
171                 printf("unknown");
172
173         printf("\n");
174 }
175
176 #define pr_lpgr_val(v, n, b, c) do {                                    \
177         u32 __v = ((v) >> (b)) & ((1 << (c)) - 1);                      \
178         if (__v)                                                        \
179                 printf(" %s=%0*x", #n, DIV_ROUND_UP(c, 4), __v);        \
180 } while (0)
181
182 static inline void print_lpgr(u32 lpgr)
183 {
184         if (!lpgr)
185                 return;
186
187         printf("LPGR=%08x:", lpgr);
188         pr_lpgr_val(lpgr, SW_ISO, 31, 1);
189         pr_lpgr_val(lpgr, SECONDARY_BOOT, 30, 1);
190         pr_lpgr_val(lpgr, BLOCK_REWRITE, 29, 1);
191         pr_lpgr_val(lpgr, WDOG_BOOT, 28, 1);
192         pr_lpgr_val(lpgr, SBMR_SHADOW, 0, 26);
193         printf("\n");
194 }
195
196 static void tx53_print_cpuinfo(void)
197 {
198         u32 cpurev;
199         struct srtc_regs *srtc_regs = (void *)SRTC_BASE_ADDR;
200         u32 lpgr = readl(&srtc_regs->lpgr);
201
202         cpurev = get_cpu_rev();
203
204         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
205                 (cpurev & 0x000F0) >> 4,
206                 (cpurev & 0x0000F) >> 0,
207                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
208
209         print_reset_cause();
210
211         print_lpgr(lpgr);
212
213         if (lpgr & (1 << 30))
214                 printf("WARNING: U-Boot started from secondary bootstrap image\n");
215
216         if (lpgr) {
217                 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
218                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
219
220                 writel(ccgr4 | MXC_CCM_CCGR4_SRTC(3), &ccm_regs->CCGR4);
221                 writel(0, &srtc_regs->lpgr);
222                 writel(ccgr4, &ccm_regs->CCGR4);
223         }
224 }
225
226 enum LTC3589_REGS {
227         LTC3589_SCR1 = 0x07,
228         LTC3589_SCR2 = 0x12,
229         LTC3589_VCCR = 0x20,
230         LTC3589_CLIRQ = 0x21,
231         LTC3589_B1DTV1 = 0x23,
232         LTC3589_B1DTV2 = 0x24,
233         LTC3589_VRRCR = 0x25,
234         LTC3589_B2DTV1 = 0x26,
235         LTC3589_B2DTV2 = 0x27,
236         LTC3589_B3DTV1 = 0x29,
237         LTC3589_B3DTV2 = 0x2a,
238         LTC3589_L2DTV1 = 0x32,
239         LTC3589_L2DTV2 = 0x33,
240 };
241
242 #define LTC3589_BnDTV1_PGOOD_MASK       (1 << 5)
243 #define LTC3589_BnDTV1_SLEW(n)          (((n) & 3) << 6)
244
245 #define LTC3589_CLK_RATE_LOW            (1 << 5)
246
247 #define LTC3589_SCR2_PGOOD_SHUTDWN      (1 << 7)
248
249 #define VDD_LDO2_VAL            mV_to_regval(vout_to_vref(1325 * 10, 2))
250 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1100 * 10, 3))
251 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1325 * 10, 4))
252 #define VDD_BUCK3_VAL           mV_to_regval(vout_to_vref(2500 * 10, 5))
253
254 #ifndef CONFIG_SYS_TX53_HWREV_2
255 /* LDO2 vref divider */
256 #define R1_2    180
257 #define R2_2    191
258 /* BUCK1 vref divider */
259 #define R1_3    150
260 #define R2_3    180
261 /* BUCK2 vref divider */
262 #define R1_4    180
263 #define R2_4    191
264 /* BUCK3 vref divider */
265 #define R1_5    270
266 #define R2_5    100
267 #else
268 /* no dividers on vref */
269 #define R1_2    0
270 #define R2_2    1
271 #define R1_3    0
272 #define R2_3    1
273 #define R1_4    0
274 #define R2_4    1
275 #define R1_5    0
276 #define R2_5    1
277 #endif
278
279 /* calculate voltages in 10mV */
280 #define R1(idx)                 R1_##idx
281 #define R2(idx)                 R2_##idx
282
283 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
284 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
285
286 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
287 #define regval_to_mV(v)         (((v) * 125 + 3625))
288
289 static struct pmic_regs {
290         enum LTC3589_REGS addr;
291         u8 val;
292 } ltc3589_regs[] = {
293         { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
294         { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
295
296         { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
297         { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
298
299         { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
300         { LTC3589_B1DTV2, VDD_CORE_VAL, },
301
302         { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
303         { LTC3589_B2DTV2, VDD_SOC_VAL, },
304
305         { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
306         { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
307
308         /* Select ref 0 for all regulators and enable slew */
309         { LTC3589_VCCR, 0x55, },
310
311         { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
312 };
313
314 static int setup_pmic_voltages(void)
315 {
316         int ret;
317         unsigned char value;
318         int i;
319
320         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
321         if (ret != 0) {
322                 printf("Failed to initialize I2C\n");
323                 return ret;
324         }
325
326         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
327         if (ret) {
328                 printf("%s: i2c_read error: %d\n", __func__, ret);
329                 return ret;
330         }
331
332         for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
333                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
334                                 &value, 1);
335                 debug("Writing %02x to reg %02x (%02x)\n",
336                         ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
337                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
338                                 &ltc3589_regs[i].val, 1);
339                 if (ret) {
340                         printf("%s: failed to write PMIC register %02x: %d\n",
341                                 __func__, ltc3589_regs[i].addr, ret);
342                         return ret;
343                 }
344         }
345         printf("VDDCORE set to %umV\n",
346                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
347
348         printf("VDDSOC  set to %umV\n",
349                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
350         return 0;
351 }
352
353 static struct {
354         u32 max_freq;
355         u32 mV;
356 } tx53_core_voltages[] = {
357         { 800000000, 1100, },
358         { 1000000000, 1240, },
359         { 1200000000, 1350, },
360 };
361
362 int adjust_core_voltage(u32 freq)
363 {
364         int ret;
365         int i;
366
367         printf("%s@%d\n", __func__, __LINE__);
368
369         for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
370                 if (freq <= tx53_core_voltages[i].max_freq) {
371                         int retries = 0;
372                         const int max_tries = 10;
373                         const int delay_us = 1;
374                         u32 mV = tx53_core_voltages[i].mV;
375                         u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
376                         u8 v;
377
378                         printf("regval[%umV]=%02x\n", mV, val);
379
380                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
381                                 &v, 1);
382                         if (ret) {
383                                 printf("%s: failed to read PMIC register %02x: %d\n",
384                                         __func__, LTC3589_B1DTV1, ret);
385                                 return ret;
386                         }
387                         printf("Changing reg %02x from %02x to %02x\n",
388                                 LTC3589_B1DTV1, v, (v & ~0x1f) |
389                                 mV_to_regval(vout_to_vref(mV * 10, 3)));
390                         v &= ~0x1f;
391                         v |= mV_to_regval(vout_to_vref(mV * 10, 3));
392                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
393                                         &v, 1);
394                         if (ret) {
395                                 printf("%s: failed to write PMIC register %02x: %d\n",
396                                         __func__, LTC3589_B1DTV1, ret);
397                                 return ret;
398                         }
399                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
400                                         &v, 1);
401                         if (ret) {
402                                 printf("%s: failed to read PMIC register %02x: %d\n",
403                                         __func__, LTC3589_VCCR, ret);
404                                 return ret;
405                         }
406                         v |= 0x1;
407                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
408                                         &v, 1);
409                         if (ret) {
410                                 printf("%s: failed to write PMIC register %02x: %d\n",
411                                         __func__, LTC3589_VCCR, ret);
412                                 return ret;
413                         }
414                         for (retries = 0; retries < max_tries; retries++) {
415                                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
416                                         LTC3589_VCCR, 1, &v, 1);
417                                 if (ret) {
418                                         printf("%s: failed to read PMIC register %02x: %d\n",
419                                                 __func__, LTC3589_VCCR, ret);
420                                         return ret;
421                                 }
422                                 if (!(v & 1))
423                                         break;
424                                 udelay(delay_us);
425                         }
426                         if (v & 1) {
427                                 printf("change of VDDCORE did not complete after %uµs\n",
428                                         retries * delay_us);
429                                 return -ETIMEDOUT;
430                         }
431
432                         printf("VDDCORE set to %umV after %u loops\n",
433                                 DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
434                                         10), retries);
435                         return 0;
436                 }
437         }
438         return -EINVAL;
439 }
440
441 int board_early_init_f(void)
442 {
443         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
444
445         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
446         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
447
448         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
449         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
450
451         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
452         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
453         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
454         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
455         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
456
457         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
458         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
459
460         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
461         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
462         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
463         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
464         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
465
466         writel(0xffcf0fff, &ccm_regs->CCGR0);
467         writel(0x000fffcf, &ccm_regs->CCGR1);
468         writel(0x033c0000, &ccm_regs->CCGR2);
469         writel(0x000000ff, &ccm_regs->CCGR3);
470         writel(0x00000000, &ccm_regs->CCGR4);
471         writel(0x00fff033, &ccm_regs->CCGR5);
472         writel(0x0f00030f, &ccm_regs->CCGR6);
473         writel(0xfff00000, &ccm_regs->CCGR7);
474         writel(0x00000000, &ccm_regs->cmeor);
475
476         return 0;
477 }
478
479 int board_init(void)
480 {
481         int ret;
482
483         /* Address of boot parameters */
484         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
485
486         if (ctrlc() || (wrsr & WRSR_TOUT)) {
487                 printf("CTRL-C detected; Skipping PMIC setup\n");
488                 return 1;
489         }
490
491         ret = setup_pmic_voltages();
492         if (ret) {
493                 printf("Failed to setup PMIC voltages\n");
494                 hang();
495         }
496         return 0;
497 }
498
499 int dram_init(void)
500 {
501         int ret;
502
503         /* dram_init must store complete ramsize in gd->ram_size */
504         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
505                                 PHYS_SDRAM_1_SIZE);
506
507         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
508                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
509         if (ret)
510                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
511                         CONFIG_SYS_SDRAM_CLK, ret);
512         else
513                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
514                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
515                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
516                         CONFIG_SYS_SDRAM_CLK);
517         return ret;
518 }
519
520 void dram_init_banksize(void)
521 {
522         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
523         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
524                         PHYS_SDRAM_1_SIZE);
525 #if CONFIG_NR_DRAM_BANKS > 1
526         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
527         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
528                         PHYS_SDRAM_2_SIZE);
529 #endif
530 }
531
532 #ifdef  CONFIG_CMD_MMC
533 static const iomux_v3_cfg_t mmc0_pads[] = {
534         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
535         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
536         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
537         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
538         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
539         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
540         /* SD1 CD */
541         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
542 };
543
544 static const iomux_v3_cfg_t mmc1_pads[] = {
545         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
546         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
547         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
548         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
549         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
550         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
551         /* SD2 CD */
552         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
553 };
554
555 static struct tx53_esdhc_cfg {
556         const iomux_v3_cfg_t *pads;
557         int num_pads;
558         struct fsl_esdhc_cfg cfg;
559         int cd_gpio;
560 } tx53_esdhc_cfg[] = {
561         {
562                 .pads = mmc0_pads,
563                 .num_pads = ARRAY_SIZE(mmc0_pads),
564                 .cfg = {
565                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
566                         .max_bus_width = 4,
567                 },
568                 .cd_gpio = IMX_GPIO_NR(3, 24),
569         },
570         {
571                 .pads = mmc1_pads,
572                 .num_pads = ARRAY_SIZE(mmc1_pads),
573                 .cfg = {
574                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
575                         .max_bus_width = 4,
576                 },
577                 .cd_gpio = IMX_GPIO_NR(3, 25),
578         },
579 };
580
581 static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
582 {
583         return container_of(cfg, struct tx53_esdhc_cfg, cfg);
584 }
585
586 int board_mmc_getcd(struct mmc *mmc)
587 {
588         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
589
590         if (cfg->cd_gpio < 0)
591                 return cfg->cd_gpio;
592
593         debug("SD card %d is %spresent\n",
594                 cfg - tx53_esdhc_cfg,
595                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
596         return !gpio_get_value(cfg->cd_gpio);
597 }
598
599 int board_mmc_init(bd_t *bis)
600 {
601         int i;
602
603         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
604                 struct mmc *mmc;
605                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
606                 int ret;
607
608                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
609                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
610
611                 ret = gpio_request_one(cfg->cd_gpio,
612                                 GPIOF_INPUT, "MMC CD");
613                 if (ret) {
614                         printf("Error %d requesting GPIO%d_%d\n",
615                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
616                         continue;
617                 }
618
619                 debug("%s: Initializing MMC slot %d\n", __func__, i);
620                 fsl_esdhc_initialize(bis, &cfg->cfg);
621
622                 mmc = find_mmc_device(i);
623                 if (mmc == NULL)
624                         continue;
625                 if (board_mmc_getcd(mmc) > 0)
626                         mmc_init(mmc);
627         }
628         return 0;
629 }
630 #endif /* CONFIG_CMD_MMC */
631
632 #ifdef CONFIG_FEC_MXC
633
634 #ifndef ETH_ALEN
635 #define ETH_ALEN 6
636 #endif
637
638 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
639 {
640         int i;
641         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
642         struct fuse_bank *bank = &iim->bank[1];
643         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
644
645         if (dev_id > 0)
646                 return;
647
648         for (i = 0; i < ETH_ALEN; i++)
649                 mac[i] = readl(&fuse->mac_addr[i]);
650 }
651
652 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
653                         PAD_CTL_SRE_FAST)
654 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
655 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
656
657 int board_eth_init(bd_t *bis)
658 {
659         int ret;
660
661         /* delay at least 21ms for the PHY internal POR signal to deassert */
662         udelay(22000);
663
664         /* Deassert RESET to the external phy */
665         gpio_set_value(TX53_FEC_RST_GPIO, 1);
666
667         ret = cpu_eth_init(bis);
668         if (ret)
669                 printf("cpu_eth_init() failed: %d\n", ret);
670
671         return ret;
672 }
673 #endif /* CONFIG_FEC_MXC */
674
675 enum {
676         LED_STATE_INIT = -1,
677         LED_STATE_OFF,
678         LED_STATE_ON,
679 };
680
681 void show_activity(int arg)
682 {
683         static int led_state = LED_STATE_INIT;
684         static ulong last;
685
686         if (led_state == LED_STATE_INIT) {
687                 last = get_timer(0);
688                 gpio_set_value(TX53_LED_GPIO, 1);
689                 led_state = LED_STATE_ON;
690         } else {
691                 if (get_timer(last) > CONFIG_SYS_HZ) {
692                         last = get_timer(0);
693                         if (led_state == LED_STATE_ON) {
694                                 gpio_set_value(TX53_LED_GPIO, 0);
695                         } else {
696                                 gpio_set_value(TX53_LED_GPIO, 1);
697                         }
698                         led_state = 1 - led_state;
699                 }
700         }
701 }
702
703 static const iomux_v3_cfg_t stk5_pads[] = {
704         /* SW controlled LED on STK5 baseboard */
705         MX53_PAD_EIM_A18__GPIO2_20,
706
707         /* I2C bus on DIMM pins 40/41 */
708         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
709         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
710
711         /* TSC200x PEN IRQ */
712         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
713
714         /* EDT-FT5x06 Polytouch panel */
715         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
716         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
717         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
718
719         /* USBH1 */
720         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
721         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
722         /* USBOTG */
723         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
724         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
725
726         /* DS1339 Interrupt */
727         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
728 };
729
730 static const struct gpio stk5_gpios[] = {
731         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
732
733         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
734         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
735         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
736         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
737 };
738
739 #ifdef CONFIG_LCD
740 static u16 tx53_cmap[256];
741 vidinfo_t panel_info = {
742         /* set to max. size supported by SoC */
743         .vl_col = 1600,
744         .vl_row = 1200,
745
746         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
747         .cmap = tx53_cmap,
748 };
749
750 static struct fb_videomode tx53_fb_modes[] = {
751 #ifndef CONFIG_SYS_LVDS_IF
752         {
753                 /* Standard VGA timing */
754                 .name           = "VGA",
755                 .refresh        = 60,
756                 .xres           = 640,
757                 .yres           = 480,
758                 .pixclock       = KHZ2PICOS(25175),
759                 .left_margin    = 48,
760                 .hsync_len      = 96,
761                 .right_margin   = 16,
762                 .upper_margin   = 31,
763                 .vsync_len      = 2,
764                 .lower_margin   = 12,
765                 .sync           = FB_SYNC_CLK_LAT_FALL,
766         },
767         {
768                 /* Emerging ETV570 640 x 480 display. Syncs low active,
769                  * DE high active, 115.2 mm x 86.4 mm display area
770                  * VGA compatible timing
771                  */
772                 .name           = "ETV570",
773                 .refresh        = 60,
774                 .xres           = 640,
775                 .yres           = 480,
776                 .pixclock       = KHZ2PICOS(25175),
777                 .left_margin    = 114,
778                 .hsync_len      = 30,
779                 .right_margin   = 16,
780                 .upper_margin   = 32,
781                 .vsync_len      = 3,
782                 .lower_margin   = 10,
783                 .sync           = FB_SYNC_CLK_LAT_FALL,
784         },
785         {
786                 /* Emerging ET0350G0DH6 320 x 240 display.
787                  * 70.08 mm x 52.56 mm display area.
788                  */
789                 .name           = "ET0350",
790                 .refresh        = 60,
791                 .xres           = 320,
792                 .yres           = 240,
793                 .pixclock       = KHZ2PICOS(6500),
794                 .left_margin    = 68 - 34,
795                 .hsync_len      = 34,
796                 .right_margin   = 20,
797                 .upper_margin   = 18 - 3,
798                 .vsync_len      = 3,
799                 .lower_margin   = 4,
800                 .sync           = FB_SYNC_CLK_LAT_FALL,
801         },
802         {
803                 /* Emerging ET0430G0DH6 480 x 272 display.
804                  * 95.04 mm x 53.856 mm display area.
805                  */
806                 .name           = "ET0430",
807                 .refresh        = 60,
808                 .xres           = 480,
809                 .yres           = 272,
810                 .pixclock       = KHZ2PICOS(9000),
811                 .left_margin    = 2,
812                 .hsync_len      = 41,
813                 .right_margin   = 2,
814                 .upper_margin   = 2,
815                 .vsync_len      = 10,
816                 .lower_margin   = 2,
817                 .sync           = FB_SYNC_CLK_LAT_FALL,
818         },
819         {
820                 /* Emerging ET0500G0DH6 800 x 480 display.
821                  * 109.6 mm x 66.4 mm display area.
822                  */
823                 .name           = "ET0500",
824                 .refresh        = 60,
825                 .xres           = 800,
826                 .yres           = 480,
827                 .pixclock       = KHZ2PICOS(33260),
828                 .left_margin    = 216 - 128,
829                 .hsync_len      = 128,
830                 .right_margin   = 1056 - 800 - 216,
831                 .upper_margin   = 35 - 2,
832                 .vsync_len      = 2,
833                 .lower_margin   = 525 - 480 - 35,
834                 .sync           = FB_SYNC_CLK_LAT_FALL,
835         },
836         {
837                 /* Emerging ETQ570G0DH6 320 x 240 display.
838                  * 115.2 mm x 86.4 mm display area.
839                  */
840                 .name           = "ETQ570",
841                 .refresh        = 60,
842                 .xres           = 320,
843                 .yres           = 240,
844                 .pixclock       = KHZ2PICOS(6400),
845                 .left_margin    = 38,
846                 .hsync_len      = 30,
847                 .right_margin   = 30,
848                 .upper_margin   = 16, /* 15 according to datasheet */
849                 .vsync_len      = 3, /* TVP -> 1>x>5 */
850                 .lower_margin   = 4, /* 4.5 according to datasheet */
851                 .sync           = FB_SYNC_CLK_LAT_FALL,
852         },
853         {
854                 /* Emerging ET0700G0DH6 800 x 480 display.
855                  * 152.4 mm x 91.44 mm display area.
856                  */
857                 .name           = "ET0700",
858                 .refresh        = 60,
859                 .xres           = 800,
860                 .yres           = 480,
861                 .pixclock       = KHZ2PICOS(33260),
862                 .left_margin    = 216 - 128,
863                 .hsync_len      = 128,
864                 .right_margin   = 1056 - 800 - 216,
865                 .upper_margin   = 35 - 2,
866                 .vsync_len      = 2,
867                 .lower_margin   = 525 - 480 - 35,
868                 .sync           = FB_SYNC_CLK_LAT_FALL,
869         },
870 #else
871         {
872                 /* HannStar HSD100PXN1
873                  * 202.7m mm x 152.06 mm display area.
874                  */
875                 .name           = "HSD100PXN1",
876                 .refresh        = 60,
877                 .xres           = 1024,
878                 .yres           = 768,
879                 .pixclock       = KHZ2PICOS(65000),
880                 .left_margin    = 0,
881                 .hsync_len      = 0,
882                 .right_margin   = 320,
883                 .upper_margin   = 0,
884                 .vsync_len      = 0,
885                 .lower_margin   = 38,
886                 .sync           = FB_SYNC_CLK_LAT_FALL,
887         },
888 #endif
889         {
890                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
891                 .refresh        = 60,
892                 .left_margin    = 48,
893                 .hsync_len      = 96,
894                 .right_margin   = 16,
895                 .upper_margin   = 31,
896                 .vsync_len      = 2,
897                 .lower_margin   = 12,
898                 .sync           = FB_SYNC_CLK_LAT_FALL,
899         },
900 };
901
902 static int lcd_enabled = 1;
903 static int lcd_bl_polarity;
904
905 static int lcd_backlight_polarity(void)
906 {
907         return lcd_bl_polarity;
908 }
909
910 void lcd_enable(void)
911 {
912         /* HACK ALERT:
913          * global variable from common/lcd.c
914          * Set to 0 here to prevent messages from going to LCD
915          * rather than serial console
916          */
917         lcd_is_enabled = 0;
918
919         if (lcd_enabled) {
920                 karo_load_splashimage(1);
921
922                 debug("Switching LCD on\n");
923                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
924                 udelay(100);
925                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
926                 udelay(300000);
927                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
928                         lcd_backlight_polarity());
929         }
930 }
931
932 void lcd_disable(void)
933 {
934         if (lcd_enabled) {
935                 printf("Disabling LCD\n");
936                 ipuv3_fb_shutdown();
937         }
938 }
939
940 void lcd_panel_disable(void)
941 {
942         if (lcd_enabled) {
943                 debug("Switching LCD off\n");
944                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
945                         !lcd_backlight_polarity());
946                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
947                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
948         }
949 }
950
951 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
952         /* LCD RESET */
953         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
954         /* LCD POWER_ENABLE */
955         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
956         /* LCD Backlight (PWM) */
957         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
958
959         /* Display */
960 #ifndef CONFIG_SYS_LVDS_IF
961         /* LCD option */
962         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
963         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
964         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
965         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
966         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
967         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
968         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
969         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
970         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
971         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
972         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
973         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
974         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
975         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
976         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
977         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
978         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
979         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
980         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
981         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
982         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
983         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
984         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
985         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
986         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
987         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
988         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
989         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
990 #else
991         /* LVDS option */
992         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
993         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
994         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
995         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
996         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
997         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
998         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
999         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
1000         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
1001         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
1002 #endif
1003 };
1004
1005 static const struct gpio stk5_lcd_gpios[] = {
1006         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
1007         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
1008         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1009 };
1010
1011 void lcd_ctrl_init(void *lcdbase)
1012 {
1013         int color_depth = 24;
1014         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1015         const char *vm;
1016         unsigned long val;
1017         int refresh = 60;
1018         struct fb_videomode *p = &tx53_fb_modes[0];
1019         struct fb_videomode fb_mode;
1020         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1021         int pix_fmt;
1022         int lcd_bus_width;
1023         ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
1024         unsigned long di_clk_rate = 65000000;
1025
1026         if (!lcd_enabled) {
1027                 debug("LCD disabled\n");
1028                 return;
1029         }
1030
1031         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1032                 debug("Disabling LCD\n");
1033                 lcd_enabled = 0;
1034                 setenv("splashimage", NULL);
1035                 return;
1036         }
1037
1038         karo_fdt_move_fdt();
1039         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1040
1041         if (video_mode == NULL) {
1042                 debug("Disabling LCD\n");
1043                 lcd_enabled = 0;
1044                 return;
1045         }
1046         vm = video_mode;
1047         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1048                 p = &fb_mode;
1049                 debug("Using video mode from FDT\n");
1050                 vm += strlen(vm);
1051                 if (fb_mode.xres > panel_info.vl_col ||
1052                         fb_mode.yres > panel_info.vl_row) {
1053                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1054                                 fb_mode.xres, fb_mode.yres,
1055                                 panel_info.vl_col, panel_info.vl_row);
1056                         lcd_enabled = 0;
1057                         return;
1058                 }
1059         }
1060         if (p->name != NULL)
1061                 debug("Trying compiled-in video modes\n");
1062         while (p->name != NULL) {
1063                 if (strcmp(p->name, vm) == 0) {
1064                         debug("Using video mode: '%s'\n", p->name);
1065                         vm += strlen(vm);
1066                         break;
1067                 }
1068                 p++;
1069         }
1070         if (*vm != '\0')
1071                 debug("Trying to decode video_mode: '%s'\n", vm);
1072         while (*vm != '\0') {
1073                 if (*vm >= '0' && *vm <= '9') {
1074                         char *end;
1075
1076                         val = simple_strtoul(vm, &end, 0);
1077                         if (end > vm) {
1078                                 if (!xres_set) {
1079                                         if (val > panel_info.vl_col)
1080                                                 val = panel_info.vl_col;
1081                                         p->xres = val;
1082                                         panel_info.vl_col = val;
1083                                         xres_set = 1;
1084                                 } else if (!yres_set) {
1085                                         if (val > panel_info.vl_row)
1086                                                 val = panel_info.vl_row;
1087                                         p->yres = val;
1088                                         panel_info.vl_row = val;
1089                                         yres_set = 1;
1090                                 } else if (!bpp_set) {
1091                                         switch (val) {
1092                                         case 32:
1093                                         case 24:
1094                                                 if (is_lvds())
1095                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1096                                                 /* fallthru */
1097                                         case 16:
1098                                         case 8:
1099                                                 color_depth = val;
1100                                                 break;
1101
1102                                         case 18:
1103                                                 if (is_lvds()) {
1104                                                         color_depth = val;
1105                                                         break;
1106                                                 }
1107                                                 /* fallthru */
1108                                         default:
1109                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1110                                                         end - vm, vm, color_depth);
1111                                         }
1112                                         bpp_set = 1;
1113                                 } else if (!refresh_set) {
1114                                         refresh = val;
1115                                         refresh_set = 1;
1116                                 }
1117                         }
1118                         vm = end;
1119                 }
1120                 switch (*vm) {
1121                 case '@':
1122                         bpp_set = 1;
1123                         /* fallthru */
1124                 case '-':
1125                         yres_set = 1;
1126                         /* fallthru */
1127                 case 'x':
1128                         xres_set = 1;
1129                         /* fallthru */
1130                 case 'M':
1131                 case 'R':
1132                         vm++;
1133                         break;
1134
1135                 default:
1136                         if (*vm != '\0')
1137                                 vm++;
1138                 }
1139         }
1140         if (p->xres == 0 || p->yres == 0) {
1141                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1142                 lcd_enabled = 0;
1143                 printf("Supported video modes are:");
1144                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
1145                         printf(" %s", p->name);
1146                 }
1147                 printf("\n");
1148                 return;
1149         }
1150         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1151                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1152                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1153                 lcd_enabled = 0;
1154                 return;
1155         }
1156         panel_info.vl_col = p->xres;
1157         panel_info.vl_row = p->yres;
1158
1159         switch (color_depth) {
1160         case 8:
1161                 panel_info.vl_bpix = LCD_COLOR8;
1162                 break;
1163         case 16:
1164                 panel_info.vl_bpix = LCD_COLOR16;
1165                 break;
1166         default:
1167                 panel_info.vl_bpix = LCD_COLOR24;
1168         }
1169
1170         p->pixclock = KHZ2PICOS(refresh *
1171                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1172                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1173                                 1000);
1174         debug("Pixel clock set to %lu.%03lu MHz\n",
1175                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1176
1177         if (p != &fb_mode) {
1178                 int ret;
1179
1180                 debug("Creating new display-timing node from '%s'\n",
1181                         video_mode);
1182                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1183                 if (ret)
1184                         printf("Failed to create new display-timing node from '%s': %d\n",
1185                                 video_mode, ret);
1186         }
1187
1188         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1189         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1190                                         ARRAY_SIZE(stk5_lcd_pads));
1191
1192         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1193         switch (lcd_bus_width) {
1194         case 24:
1195                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1196                 break;
1197
1198         case 18:
1199                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1200                 break;
1201
1202         case 16:
1203                 if (!is_lvds()) {
1204                         pix_fmt = IPU_PIX_FMT_RGB565;
1205                         break;
1206                 }
1207                 /* fallthru */
1208         default:
1209                 lcd_enabled = 0;
1210                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1211                         lcd_bus_width);
1212                 return;
1213         }
1214         if (is_lvds()) {
1215                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1216                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1217                 uint32_t gpr2;
1218
1219                 if (lvds_chan_mask == 0) {
1220                         printf("No LVDS channel active\n");
1221                         lcd_enabled = 0;
1222                         return;
1223                 }
1224
1225                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1226                 if (lcd_bus_width == 24)
1227                         gpr2 |= (1 << 5) | (1 << 7);
1228                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1229                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1230                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1231                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1232         }
1233         if (karo_load_splashimage(0) == 0) {
1234                 int ret;
1235
1236                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1237
1238                 debug("Initializing LCD controller\n");
1239                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1240                 if (ret) {
1241                         printf("Failed to initialize FB driver: %d\n", ret);
1242                         lcd_enabled = 0;
1243                 }
1244         } else {
1245                 debug("Skipping initialization of LCD controller\n");
1246         }
1247 }
1248 #else
1249 #define lcd_enabled 0
1250 #endif /* CONFIG_LCD */
1251
1252 static void stk5_board_init(void)
1253 {
1254         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1255         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1256 }
1257
1258 static void stk5v3_board_init(void)
1259 {
1260         stk5_board_init();
1261 }
1262
1263 static void stk5v5_board_init(void)
1264 {
1265         stk5_board_init();
1266
1267         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1268                         "Flexcan Transceiver");
1269         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1270 }
1271
1272 static void tx53_set_cpu_clock(void)
1273 {
1274         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1275
1276         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1277                 return;
1278
1279         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1280                 return;
1281
1282         if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1283                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1284                 printf("CPU clock set to %lu.%03lu MHz\n",
1285                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1286         } else {
1287                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1288         }
1289 }
1290
1291 static void tx53_init_mac(void)
1292 {
1293         u8 mac[ETH_ALEN];
1294
1295         imx_get_mac_from_fuse(0, mac);
1296         if (!is_valid_ether_addr(mac)) {
1297                 printf("No valid MAC address programmed\n");
1298                 return;
1299         }
1300
1301         printf("MAC addr from fuse: %pM\n", mac);
1302         eth_setenv_enetaddr("ethaddr", mac);
1303 }
1304
1305 int board_late_init(void)
1306 {
1307         int ret = 0;
1308         const char *baseboard;
1309
1310         tx53_set_cpu_clock();
1311         karo_fdt_move_fdt();
1312
1313         baseboard = getenv("baseboard");
1314         if (!baseboard)
1315                 goto exit;
1316
1317         printf("Baseboard: %s\n", baseboard);
1318
1319         if (strncmp(baseboard, "stk5", 4) == 0) {
1320                 if ((strlen(baseboard) == 4) ||
1321                         strcmp(baseboard, "stk5-v3") == 0) {
1322                         stk5v3_board_init();
1323                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1324                         const char *otg_mode = getenv("otg_mode");
1325
1326                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1327                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1328                                         otg_mode, baseboard);
1329                                 setenv("otg_mode", "none");
1330                         }
1331                         stk5v5_board_init();
1332                 } else {
1333                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1334                                 baseboard + 4);
1335                 }
1336         } else {
1337                 printf("WARNING: Unsupported baseboard: '%s'\n",
1338                         baseboard);
1339                 ret = -EINVAL;
1340         }
1341
1342 exit:
1343         tx53_init_mac();
1344
1345         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1346         clear_ctrlc();
1347         return ret;
1348 }
1349
1350 int checkboard(void)
1351 {
1352         tx53_print_cpuinfo();
1353
1354         printf("Board: Ka-Ro TX53-x%d3%s\n",
1355                 is_lvds(), TX53_MOD_SUFFIX);
1356
1357         return 0;
1358 }
1359
1360 #if defined(CONFIG_OF_BOARD_SETUP)
1361 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1362 #include <jffs2/jffs2.h>
1363 #include <mtd_node.h>
1364 static struct node_info nodes[] = {
1365         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1366 };
1367 #else
1368 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1369 #endif
1370
1371 #ifdef CONFIG_SYS_TX53_HWREV_2
1372 static void tx53_fixup_rtc(void *blob)
1373 {
1374         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1375         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1376 }
1377 #else
1378 static inline void tx53_fixup_rtc(void *blob)
1379 {
1380 }
1381 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1382
1383 static const char *tx53_touchpanels[] = {
1384         "ti,tsc2007",
1385         "edt,edt-ft5x06",
1386         "eeti,egalax_ts",
1387 };
1388
1389 void ft_board_setup(void *blob, bd_t *bd)
1390 {
1391         const char *baseboard = getenv("baseboard");
1392         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1393         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1394         int ret;
1395
1396         ret = fdt_increase_size(blob, 4096);
1397         if (ret)
1398                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1399
1400         if (stk5_v5)
1401                 karo_fdt_enable_node(blob, "stk5led", 0);
1402
1403         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1404         fdt_fixup_ethernet(blob);
1405
1406         karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1407                                 ARRAY_SIZE(tx53_touchpanels));
1408         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1409         karo_fdt_fixup_flexcan(blob, stk5_v5);
1410         tx53_fixup_rtc(blob);
1411         karo_fdt_update_fb_mode(blob, video_mode);
1412 }
1413 #endif /* CONFIG_OF_BOARD_SETUP */