Merge branch 'tx53-update-2016-02-03' into karo-tx6
[karo-tx-uboot.git] / board / karo / tx53 / tx53.c
1 /*
2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18
19 #include <common.h>
20 #include <errno.h>
21 #include <libfdt.h>
22 #include <fdt_support.h>
23 #include <i2c.h>
24 #include <lcd.h>
25 #include <netdev.h>
26 #include <mmc.h>
27 #include <fsl_esdhc.h>
28 #include <video_fb.h>
29 #include <ipu.h>
30 #include <mxcfb.h>
31 #include <linux/fb.h>
32 #include <asm/io.h>
33 #include <asm/gpio.h>
34 #include <asm/arch/iomux-mx53.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/hab.h>
37 #include <asm/arch/imx-regs.h>
38 #include <asm/arch/crm_regs.h>
39 #include <asm/arch/sys_proto.h>
40
41 #include "../common/karo.h"
42
43 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
44 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
45 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
46 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
47
48 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
49 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
50 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
51
52 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
53
54 DECLARE_GLOBAL_DATA_PTR;
55
56 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
57                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
58
59 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
60                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
61
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 char __csf_data[0] __attribute__((section(".__csf_data")));
64
65 static iomux_v3_cfg_t tx53_pads[] = {
66         /* NAND flash pads are set up in lowlevel_init.S */
67
68         /* UART pads */
69 #if CONFIG_MXC_UART_BASE == UART1_BASE
70         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
71         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
72         MX53_PAD_PATA_IORDY__UART1_RTS,
73         MX53_PAD_PATA_RESET_B__UART1_CTS,
74 #endif
75 #if CONFIG_MXC_UART_BASE == UART2_BASE
76         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
77         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
78         MX53_PAD_PATA_DIOR__UART2_RTS,
79         MX53_PAD_PATA_INTRQ__UART2_CTS,
80 #endif
81 #if CONFIG_MXC_UART_BASE == UART3_BASE
82         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
83         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
84         MX53_PAD_PATA_DA_2__UART3_RTS,
85         MX53_PAD_PATA_DA_1__UART3_CTS,
86 #endif
87         /* internal I2C */
88         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
89         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
90
91         /* FEC PHY GPIO functions */
92         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
93         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
94         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
95
96         /* FEC functions */
97         MX53_PAD_FEC_MDC__FEC_MDC,
98         MX53_PAD_FEC_MDIO__FEC_MDIO,
99         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
100         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
101         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
102         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
103         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
104         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
105         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
106         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
107 };
108
109 static const struct gpio tx53_gpios[] = {
110         { TX53_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
111         { TX53_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
112         { TX53_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
113         { TX53_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
114 };
115
116 /*
117  * Functions
118  */
119 /* placed in section '.data' to prevent overwriting relocation info
120  * overlayed with bss
121  */
122 static u32 wrsr __attribute__((section(".data")));
123
124 #define WRSR_POR        (1 << 4)
125 #define WRSR_TOUT       (1 << 1)
126 #define WRSR_SFTW       (1 << 0)
127
128 static void print_reset_cause(void)
129 {
130         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
131         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
132         u32 srsr;
133         char *dlm = "";
134
135         printf("Reset cause: ");
136
137         srsr = readl(&src_regs->srsr);
138         wrsr = readw(wdt_base + 4);
139
140         if (wrsr & WRSR_POR) {
141                 printf("%sPOR", dlm);
142                 dlm = " | ";
143         }
144         if (srsr & 0x00004) {
145                 printf("%sCSU", dlm);
146                 dlm = " | ";
147         }
148         if (srsr & 0x00008) {
149                 printf("%sIPP USER", dlm);
150                 dlm = " | ";
151         }
152         if (srsr & 0x00010) {
153                 if (wrsr & WRSR_SFTW) {
154                         printf("%sSOFT", dlm);
155                         dlm = " | ";
156                 }
157                 if (wrsr & WRSR_TOUT) {
158                         printf("%sWDOG", dlm);
159                         dlm = " | ";
160                 }
161         }
162         if (srsr & 0x00020) {
163                 printf("%sJTAG HIGH-Z", dlm);
164                 dlm = " | ";
165         }
166         if (srsr & 0x00040) {
167                 printf("%sJTAG SW", dlm);
168                 dlm = " | ";
169         }
170         if (srsr & 0x10000) {
171                 printf("%sWARM BOOT", dlm);
172                 dlm = " | ";
173         }
174         if (dlm[0] == '\0')
175                 printf("unknown");
176
177         printf("\n");
178 }
179
180 #define pr_lpgr_val(v, n, b, c) do {                                    \
181         u32 __v = ((v) >> (b)) & ((1 << (c)) - 1);                      \
182         if (__v)                                                        \
183                 printf(" %s=%0*x", #n, DIV_ROUND_UP(c, 4), __v);        \
184 } while (0)
185
186 static inline void print_lpgr(u32 lpgr)
187 {
188         if (!lpgr)
189                 return;
190
191         printf("LPGR=%08x:", lpgr);
192         pr_lpgr_val(lpgr, SW_ISO, 31, 1);
193         pr_lpgr_val(lpgr, SECONDARY_BOOT, 30, 1);
194         pr_lpgr_val(lpgr, BLOCK_REWRITE, 29, 1);
195         pr_lpgr_val(lpgr, WDOG_BOOT, 28, 1);
196         pr_lpgr_val(lpgr, SBMR_SHADOW, 0, 26);
197         printf("\n");
198 }
199
200 static void tx53_print_cpuinfo(void)
201 {
202         u32 cpurev;
203         struct srtc_regs *srtc_regs = (void *)SRTC_BASE_ADDR;
204         u32 lpgr = readl(&srtc_regs->lpgr);
205
206         cpurev = get_cpu_rev();
207
208         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
209                 (cpurev & 0x000F0) >> 4,
210                 (cpurev & 0x0000F) >> 0,
211                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
212
213         print_reset_cause();
214
215         print_lpgr(lpgr);
216
217         if (lpgr & (1 << 30))
218                 printf("WARNING: U-Boot started from secondary bootstrap image\n");
219
220         if (lpgr) {
221                 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
222                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
223
224                 writel(ccgr4 | MXC_CCM_CCGR4_SRTC(3), &ccm_regs->CCGR4);
225                 writel(0, &srtc_regs->lpgr);
226                 writel(ccgr4, &ccm_regs->CCGR4);
227         }
228 }
229
230 enum LTC3589_REGS {
231         LTC3589_SCR1 = 0x07,
232         LTC3589_SCR2 = 0x12,
233         LTC3589_VCCR = 0x20,
234         LTC3589_CLIRQ = 0x21,
235         LTC3589_B1DTV1 = 0x23,
236         LTC3589_B1DTV2 = 0x24,
237         LTC3589_VRRCR = 0x25,
238         LTC3589_B2DTV1 = 0x26,
239         LTC3589_B2DTV2 = 0x27,
240         LTC3589_B3DTV1 = 0x29,
241         LTC3589_B3DTV2 = 0x2a,
242         LTC3589_L2DTV1 = 0x32,
243         LTC3589_L2DTV2 = 0x33,
244 };
245
246 #define LTC3589_BnDTV1_PGOOD_MASK       (1 << 5)
247 #define LTC3589_BnDTV1_SLEW(n)          (((n) & 3) << 6)
248
249 #define LTC3589_CLK_RATE_LOW            (1 << 5)
250
251 #define LTC3589_SCR2_PGOOD_SHUTDWN      (1 << 7)
252
253 #define VDD_LDO2_VAL            mV_to_regval(vout_to_vref(1325 * 10, 2))
254 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1100 * 10, 3))
255 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1325 * 10, 4))
256 #define VDD_BUCK3_VAL           mV_to_regval(vout_to_vref(2500 * 10, 5))
257
258 #ifndef CONFIG_SYS_TX53_HWREV_2
259 /* LDO2 vref divider */
260 #define R1_2    180
261 #define R2_2    191
262 /* BUCK1 vref divider */
263 #define R1_3    150
264 #define R2_3    180
265 /* BUCK2 vref divider */
266 #define R1_4    180
267 #define R2_4    191
268 /* BUCK3 vref divider */
269 #define R1_5    270
270 #define R2_5    100
271 #else
272 /* no dividers on vref */
273 #define R1_2    0
274 #define R2_2    1
275 #define R1_3    0
276 #define R2_3    1
277 #define R1_4    0
278 #define R2_4    1
279 #define R1_5    0
280 #define R2_5    1
281 #endif
282
283 /* calculate voltages in 10mV */
284 #define R1(idx)                 R1_##idx
285 #define R2(idx)                 R2_##idx
286
287 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
288 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
289
290 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
291 #define regval_to_mV(v)         (((v) * 125 + 3625))
292
293 static struct pmic_regs {
294         enum LTC3589_REGS addr;
295         u8 val;
296 } ltc3589_regs[] = {
297         { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
298         { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
299
300         { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
301         { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
302
303         { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
304         { LTC3589_B1DTV2, VDD_CORE_VAL, },
305
306         { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
307         { LTC3589_B2DTV2, VDD_SOC_VAL, },
308
309         { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
310         { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
311
312         /* Select ref 0 for all regulators and enable slew */
313         { LTC3589_VCCR, 0x55, },
314
315         { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
316 };
317
318 static int setup_pmic_voltages(void)
319 {
320         int ret;
321         unsigned char value;
322         int i;
323
324         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
325         if (ret != 0) {
326                 printf("Failed to initialize I2C\n");
327                 return ret;
328         }
329
330         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
331         if (ret) {
332                 printf("%s: i2c_read error: %d\n", __func__, ret);
333                 return ret;
334         }
335
336         for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
337                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
338                                 &value, 1);
339                 debug("Writing %02x to reg %02x (%02x)\n",
340                         ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
341                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
342                                 &ltc3589_regs[i].val, 1);
343                 if (ret) {
344                         printf("%s: failed to write PMIC register %02x: %d\n",
345                                 __func__, ltc3589_regs[i].addr, ret);
346                         return ret;
347                 }
348         }
349         printf("VDDCORE set to %umV\n",
350                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
351
352         printf("VDDSOC  set to %umV\n",
353                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
354         return 0;
355 }
356
357 static struct {
358         u32 max_freq;
359         u32 mV;
360 } tx53_core_voltages[] = {
361         { 800000000, 1100, },
362         { 1000000000, 1240, },
363         { 1200000000, 1350, },
364 };
365
366 int adjust_core_voltage(u32 freq)
367 {
368         int ret;
369         int i;
370
371         printf("%s@%d\n", __func__, __LINE__);
372
373         for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
374                 if (freq <= tx53_core_voltages[i].max_freq) {
375                         int retries = 0;
376                         const int max_tries = 10;
377                         const int delay_us = 1;
378                         u32 mV = tx53_core_voltages[i].mV;
379                         u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
380                         u8 v;
381
382                         debug("regval[%umV]=%02x\n", mV, val);
383
384                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
385                                 &v, 1);
386                         if (ret) {
387                                 printf("%s: failed to read PMIC register %02x: %d\n",
388                                         __func__, LTC3589_B1DTV1, ret);
389                                 return ret;
390                         }
391                         debug("Changing reg %02x from %02x to %02x\n",
392                                 LTC3589_B1DTV1, v, (v & ~0x1f) |
393                                 mV_to_regval(vout_to_vref(mV * 10, 3)));
394                         v &= ~0x1f;
395                         v |= mV_to_regval(vout_to_vref(mV * 10, 3));
396                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
397                                         &v, 1);
398                         if (ret) {
399                                 printf("%s: failed to write PMIC register %02x: %d\n",
400                                         __func__, LTC3589_B1DTV1, ret);
401                                 return ret;
402                         }
403                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
404                                         &v, 1);
405                         if (ret) {
406                                 printf("%s: failed to read PMIC register %02x: %d\n",
407                                         __func__, LTC3589_VCCR, ret);
408                                 return ret;
409                         }
410                         v |= 0x1;
411                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
412                                         &v, 1);
413                         if (ret) {
414                                 printf("%s: failed to write PMIC register %02x: %d\n",
415                                         __func__, LTC3589_VCCR, ret);
416                                 return ret;
417                         }
418                         for (retries = 0; retries < max_tries; retries++) {
419                                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
420                                         LTC3589_VCCR, 1, &v, 1);
421                                 if (ret) {
422                                         printf("%s: failed to read PMIC register %02x: %d\n",
423                                                 __func__, LTC3589_VCCR, ret);
424                                         return ret;
425                                 }
426                                 if (!(v & 1))
427                                         break;
428                                 udelay(delay_us);
429                         }
430                         if (v & 1) {
431                                 printf("change of VDDCORE did not complete after %uµs\n",
432                                         retries * delay_us);
433                                 return -ETIMEDOUT;
434                         }
435
436                         printf("VDDCORE set to %umV after %u loops\n",
437                                 DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
438                                         10), retries);
439                         return 0;
440                 }
441         }
442         return -EINVAL;
443 }
444
445 int board_early_init_f(void)
446 {
447         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
448
449         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
450         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
451
452         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
453         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
454         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
455         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
456         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
457
458         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
459         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
460
461         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
462         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
463         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
464         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
465         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
466
467         writel(0xffcf0fff, &ccm_regs->CCGR0);
468         writel(0x000fffcf, &ccm_regs->CCGR1);
469         writel(0x033c0000, &ccm_regs->CCGR2);
470         writel(0x000000ff, &ccm_regs->CCGR3);
471         writel(0x00000000, &ccm_regs->CCGR4);
472         writel(0x00fff033, &ccm_regs->CCGR5);
473         writel(0x0f00030f, &ccm_regs->CCGR6);
474         writel(0xfff00000, &ccm_regs->CCGR7);
475         writel(0x00000000, &ccm_regs->cmeor);
476
477         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
478
479         return 0;
480 }
481
482 int board_init(void)
483 {
484         int ret;
485
486         ret = gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
487         if (ret < 0) {
488                 printf("Failed to request tx53_gpios: %d\n", ret);
489         }
490
491         /* Address of boot parameters */
492         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
493
494         if (ctrlc() || (wrsr & WRSR_TOUT)) {
495                 if (wrsr & WRSR_TOUT)
496                         printf("WDOG RESET detected; Skipping PMIC setup\n");
497                 else
498                         printf("<CTRL-C> detected; safeboot enabled\n");
499                 return 0;
500         }
501
502         ret = setup_pmic_voltages();
503         if (ret) {
504                 printf("Failed to setup PMIC voltages\n");
505                 hang();
506         }
507         return 0;
508 }
509
510 int dram_init(void)
511 {
512         int ret;
513
514         /*
515          * U-Boot doesn't support RAM banks with intervening holes,
516          * so let U-Boot only know about the first bank for its
517          * internal data structures. The size reported to Linux is
518          * determined from the individual bank sizes.
519          */
520         gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, SZ_1G);
521
522         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
523                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
524         if (ret)
525                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
526                         CONFIG_SYS_SDRAM_CLK, ret);
527         else
528                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
529                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
530                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
531                         CONFIG_SYS_SDRAM_CLK);
532         return ret;
533 }
534
535 void dram_init_banksize(void)
536 {
537         long total_size = gd->ram_size;
538
539         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
540         gd->bd->bi_dram[0].size = gd->ram_size;
541
542 #if CONFIG_NR_DRAM_BANKS > 1
543         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, SZ_1G);
544
545         if (gd->bd->bi_dram[1].size) {
546                 debug("Found %luMiB SDRAM in bank 2\n",
547                         gd->bd->bi_dram[1].size / SZ_1M);
548                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
549                 total_size += gd->bd->bi_dram[1].size;
550         }
551 #endif
552         if (total_size != CONFIG_SYS_SDRAM_SIZE)
553                 printf("WARNING: SDRAM size mismatch: %uMiB configured; %luMiB detected\n",
554                         CONFIG_SYS_SDRAM_SIZE / SZ_1M, total_size / SZ_1M);
555 }
556
557 #ifdef  CONFIG_CMD_MMC
558 static const iomux_v3_cfg_t mmc0_pads[] = {
559         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
560         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
561         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
562         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
563         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
564         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
565         /* SD1 CD */
566         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
567 };
568
569 static const iomux_v3_cfg_t mmc1_pads[] = {
570         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
571         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
572         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
573         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
574         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
575         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
576         /* SD2 CD */
577         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
578 };
579
580 static struct tx53_esdhc_cfg {
581         const iomux_v3_cfg_t *pads;
582         int num_pads;
583         struct fsl_esdhc_cfg cfg;
584         int cd_gpio;
585 } tx53_esdhc_cfg[] = {
586         {
587                 .pads = mmc0_pads,
588                 .num_pads = ARRAY_SIZE(mmc0_pads),
589                 .cfg = {
590                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
591                         .max_bus_width = 4,
592                 },
593                 .cd_gpio = IMX_GPIO_NR(3, 24),
594         },
595         {
596                 .pads = mmc1_pads,
597                 .num_pads = ARRAY_SIZE(mmc1_pads),
598                 .cfg = {
599                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
600                         .max_bus_width = 4,
601                 },
602                 .cd_gpio = IMX_GPIO_NR(3, 25),
603         },
604 };
605
606 static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
607 {
608         return container_of(cfg, struct tx53_esdhc_cfg, cfg);
609 }
610
611 int board_mmc_getcd(struct mmc *mmc)
612 {
613         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
614
615         if (cfg->cd_gpio < 0)
616                 return cfg->cd_gpio;
617
618         debug("SD card %d is %spresent\n",
619                 cfg - tx53_esdhc_cfg,
620                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
621         return !gpio_get_value(cfg->cd_gpio);
622 }
623
624 int board_mmc_init(bd_t *bis)
625 {
626         int i;
627
628         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
629                 struct mmc *mmc;
630                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
631                 int ret;
632
633                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
634                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
635
636                 ret = gpio_request_one(cfg->cd_gpio,
637                                 GPIOFLAG_INPUT, "MMC CD");
638                 if (ret) {
639                         printf("Error %d requesting GPIO%d_%d\n",
640                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
641                         continue;
642                 }
643
644                 debug("%s: Initializing MMC slot %d\n", __func__, i);
645                 fsl_esdhc_initialize(bis, &cfg->cfg);
646
647                 mmc = find_mmc_device(i);
648                 if (mmc == NULL)
649                         continue;
650                 if (board_mmc_getcd(mmc) > 0)
651                         mmc_init(mmc);
652         }
653         return 0;
654 }
655 #endif /* CONFIG_CMD_MMC */
656
657 #ifdef CONFIG_FEC_MXC
658
659 #ifndef ETH_ALEN
660 #define ETH_ALEN 6
661 #endif
662
663 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
664 {
665         int i;
666         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
667         struct fuse_bank *bank = &iim->bank[1];
668         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
669
670         if (dev_id > 0)
671                 return;
672
673         for (i = 0; i < ETH_ALEN; i++)
674                 mac[i] = readl(&fuse->mac_addr[i]);
675 }
676
677 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
678                         PAD_CTL_SRE_FAST)
679 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
680 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
681
682 int board_eth_init(bd_t *bis)
683 {
684         int ret;
685
686         /* delay at least 21ms for the PHY internal POR signal to deassert */
687         udelay(22000);
688
689         /* Deassert RESET to the external phy */
690         gpio_set_value(TX53_FEC_RST_GPIO, 1);
691
692         ret = cpu_eth_init(bis);
693         if (ret)
694                 printf("cpu_eth_init() failed: %d\n", ret);
695
696         return ret;
697 }
698 #endif /* CONFIG_FEC_MXC */
699
700 enum {
701         LED_STATE_INIT = -1,
702         LED_STATE_OFF,
703         LED_STATE_ON,
704 };
705
706 void show_activity(int arg)
707 {
708         static int led_state = LED_STATE_INIT;
709         static ulong last;
710
711         if (led_state == LED_STATE_INIT) {
712                 last = get_timer(0);
713                 gpio_set_value(TX53_LED_GPIO, 1);
714                 led_state = LED_STATE_ON;
715         } else {
716                 if (get_timer(last) > CONFIG_SYS_HZ) {
717                         last = get_timer(0);
718                         if (led_state == LED_STATE_ON) {
719                                 gpio_set_value(TX53_LED_GPIO, 0);
720                         } else {
721                                 gpio_set_value(TX53_LED_GPIO, 1);
722                         }
723                         led_state = 1 - led_state;
724                 }
725         }
726 }
727
728 static const iomux_v3_cfg_t stk5_pads[] = {
729         /* SW controlled LED on STK5 baseboard */
730         MX53_PAD_EIM_A18__GPIO2_20,
731
732         /* I2C bus on DIMM pins 40/41 */
733         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
734         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
735
736         /* TSC200x PEN IRQ */
737         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
738
739         /* EDT-FT5x06 Polytouch panel */
740         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
741         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
742         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
743
744         /* USBH1 */
745         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
746         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
747         /* USBOTG */
748         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
749         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
750
751         /* DS1339 Interrupt */
752         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
753 };
754
755 static const struct gpio stk5_gpios[] = {
756         { TX53_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
757
758         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
759         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
760         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
761         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
762 };
763
764 #ifdef CONFIG_LCD
765 vidinfo_t panel_info = {
766         /* set to max. size supported by SoC */
767         .vl_col = 1600,
768         .vl_row = 1200,
769
770         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
771 };
772
773 static struct fb_videomode tx53_fb_modes[] = {
774 #ifndef CONFIG_SYS_LVDS_IF
775         {
776                 /* Standard VGA timing */
777                 .name           = "VGA",
778                 .refresh        = 60,
779                 .xres           = 640,
780                 .yres           = 480,
781                 .pixclock       = KHZ2PICOS(25175),
782                 .left_margin    = 48,
783                 .hsync_len      = 96,
784                 .right_margin   = 16,
785                 .upper_margin   = 31,
786                 .vsync_len      = 2,
787                 .lower_margin   = 12,
788                 .sync           = FB_SYNC_CLK_LAT_FALL,
789         },
790         {
791                 /* Emerging ETV570 640 x 480 display. Syncs low active,
792                  * DE high active, 115.2 mm x 86.4 mm display area
793                  * VGA compatible timing
794                  */
795                 .name           = "ETV570",
796                 .refresh        = 60,
797                 .xres           = 640,
798                 .yres           = 480,
799                 .pixclock       = KHZ2PICOS(25175),
800                 .left_margin    = 114,
801                 .hsync_len      = 30,
802                 .right_margin   = 16,
803                 .upper_margin   = 32,
804                 .vsync_len      = 3,
805                 .lower_margin   = 10,
806                 .sync           = FB_SYNC_CLK_LAT_FALL,
807         },
808         {
809                 /* Emerging ET0350G0DH6 320 x 240 display.
810                  * 70.08 mm x 52.56 mm display area.
811                  */
812                 .name           = "ET0350",
813                 .refresh        = 60,
814                 .xres           = 320,
815                 .yres           = 240,
816                 .pixclock       = KHZ2PICOS(6500),
817                 .left_margin    = 68 - 34,
818                 .hsync_len      = 34,
819                 .right_margin   = 20,
820                 .upper_margin   = 18 - 3,
821                 .vsync_len      = 3,
822                 .lower_margin   = 4,
823                 .sync           = FB_SYNC_CLK_LAT_FALL,
824         },
825         {
826                 /* Emerging ET0430G0DH6 480 x 272 display.
827                  * 95.04 mm x 53.856 mm display area.
828                  */
829                 .name           = "ET0430",
830                 .refresh        = 60,
831                 .xres           = 480,
832                 .yres           = 272,
833                 .pixclock       = KHZ2PICOS(9000),
834                 .left_margin    = 2,
835                 .hsync_len      = 41,
836                 .right_margin   = 2,
837                 .upper_margin   = 2,
838                 .vsync_len      = 10,
839                 .lower_margin   = 2,
840         },
841         {
842                 /* Emerging ET0500G0DH6 800 x 480 display.
843                  * 109.6 mm x 66.4 mm display area.
844                  */
845                 .name           = "ET0500",
846                 .refresh        = 60,
847                 .xres           = 800,
848                 .yres           = 480,
849                 .pixclock       = KHZ2PICOS(33260),
850                 .left_margin    = 216 - 128,
851                 .hsync_len      = 128,
852                 .right_margin   = 1056 - 800 - 216,
853                 .upper_margin   = 35 - 2,
854                 .vsync_len      = 2,
855                 .lower_margin   = 525 - 480 - 35,
856                 .sync           = FB_SYNC_CLK_LAT_FALL,
857         },
858         {
859                 /* Emerging ETQ570G0DH6 320 x 240 display.
860                  * 115.2 mm x 86.4 mm display area.
861                  */
862                 .name           = "ETQ570",
863                 .refresh        = 60,
864                 .xres           = 320,
865                 .yres           = 240,
866                 .pixclock       = KHZ2PICOS(6400),
867                 .left_margin    = 38,
868                 .hsync_len      = 30,
869                 .right_margin   = 30,
870                 .upper_margin   = 16, /* 15 according to datasheet */
871                 .vsync_len      = 3, /* TVP -> 1>x>5 */
872                 .lower_margin   = 4, /* 4.5 according to datasheet */
873                 .sync           = FB_SYNC_CLK_LAT_FALL,
874         },
875         {
876                 /* Emerging ET0700G0DH6 800 x 480 display.
877                  * 152.4 mm x 91.44 mm display area.
878                  */
879                 .name           = "ET0700",
880                 .refresh        = 60,
881                 .xres           = 800,
882                 .yres           = 480,
883                 .pixclock       = KHZ2PICOS(33260),
884                 .left_margin    = 216 - 128,
885                 .hsync_len      = 128,
886                 .right_margin   = 1056 - 800 - 216,
887                 .upper_margin   = 35 - 2,
888                 .vsync_len      = 2,
889                 .lower_margin   = 525 - 480 - 35,
890                 .sync           = FB_SYNC_CLK_LAT_FALL,
891         },
892 #else
893         {
894                 /* HannStar HSD100PXN1
895                  * 202.7m mm x 152.06 mm display area.
896                  */
897                 .name           = "HSD100PXN1",
898                 .refresh        = 60,
899                 .xres           = 1024,
900                 .yres           = 768,
901                 .pixclock       = KHZ2PICOS(65000),
902                 .left_margin    = 0,
903                 .hsync_len      = 0,
904                 .right_margin   = 320,
905                 .upper_margin   = 0,
906                 .vsync_len      = 0,
907                 .lower_margin   = 38,
908                 .sync           = FB_SYNC_CLK_LAT_FALL,
909         },
910 #endif
911         {
912                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
913                 .refresh        = 60,
914                 .left_margin    = 48,
915                 .hsync_len      = 96,
916                 .right_margin   = 16,
917                 .upper_margin   = 31,
918                 .vsync_len      = 2,
919                 .lower_margin   = 12,
920                 .sync           = FB_SYNC_CLK_LAT_FALL,
921         },
922 };
923
924 static int lcd_enabled = 1;
925 static int lcd_bl_polarity;
926
927 static int lcd_backlight_polarity(void)
928 {
929         return lcd_bl_polarity;
930 }
931
932 void lcd_enable(void)
933 {
934         /* HACK ALERT:
935          * global variable from common/lcd.c
936          * Set to 0 here to prevent messages from going to LCD
937          * rather than serial console
938          */
939         lcd_is_enabled = 0;
940
941         if (lcd_enabled) {
942                 karo_load_splashimage(1);
943
944                 debug("Switching LCD on\n");
945                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
946                 udelay(100);
947                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
948                 udelay(300000);
949                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
950                         lcd_backlight_polarity());
951         }
952 }
953
954 void lcd_disable(void)
955 {
956         if (lcd_enabled) {
957                 printf("Disabling LCD\n");
958                 ipuv3_fb_shutdown();
959         }
960 }
961
962 void lcd_panel_disable(void)
963 {
964         if (lcd_enabled) {
965                 debug("Switching LCD off\n");
966                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
967                         !lcd_backlight_polarity());
968                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
969                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
970         }
971 }
972
973 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
974         /* LCD RESET */
975         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
976         /* LCD POWER_ENABLE */
977         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
978         /* LCD Backlight (PWM) */
979         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
980
981         /* Display */
982 #ifndef CONFIG_SYS_LVDS_IF
983         /* LCD option */
984         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
985         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
986         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
987         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
988         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
989         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
990         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
991         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
992         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
993         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
994         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
995         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
996         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
997         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
998         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
999         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
1000         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
1001         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
1002         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
1003         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
1004         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
1005         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
1006         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
1007         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
1008         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
1009         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
1010         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
1011         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
1012 #else
1013         /* LVDS option */
1014         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
1015         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
1016         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
1017         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
1018         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
1019         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
1020         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
1021         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
1022         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
1023         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
1024 #endif
1025 };
1026
1027 static const struct gpio stk5_lcd_gpios[] = {
1028         { TX53_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1029         { TX53_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1030         { TX53_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1031 };
1032
1033 void lcd_ctrl_init(void *lcdbase)
1034 {
1035         int color_depth = 24;
1036         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1037         const char *vm;
1038         unsigned long val;
1039         int refresh = 60;
1040         struct fb_videomode *p = &tx53_fb_modes[0];
1041         struct fb_videomode fb_mode;
1042         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1043         int pix_fmt;
1044         int lcd_bus_width;
1045         ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
1046         unsigned long di_clk_rate = 65000000;
1047
1048         if (!lcd_enabled) {
1049                 debug("LCD disabled\n");
1050                 return;
1051         }
1052
1053         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1054                 debug("Disabling LCD\n");
1055                 lcd_enabled = 0;
1056                 setenv("splashimage", NULL);
1057                 return;
1058         }
1059
1060         karo_fdt_move_fdt();
1061
1062         if (video_mode == NULL) {
1063                 debug("Disabling LCD\n");
1064                 lcd_enabled = 0;
1065                 return;
1066         }
1067
1068         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1069         vm = video_mode;
1070         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1071                 p = &fb_mode;
1072                 debug("Using video mode from FDT\n");
1073                 vm += strlen(vm);
1074                 if (fb_mode.xres > panel_info.vl_col ||
1075                         fb_mode.yres > panel_info.vl_row) {
1076                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1077                                 fb_mode.xres, fb_mode.yres,
1078                                 panel_info.vl_col, panel_info.vl_row);
1079                         lcd_enabled = 0;
1080                         return;
1081                 }
1082         }
1083         if (p->name != NULL)
1084                 debug("Trying compiled-in video modes\n");
1085         while (p->name != NULL) {
1086                 if (strcmp(p->name, vm) == 0) {
1087                         debug("Using video mode: '%s'\n", p->name);
1088                         vm += strlen(vm);
1089                         break;
1090                 }
1091                 p++;
1092         }
1093         if (*vm != '\0')
1094                 debug("Trying to decode video_mode: '%s'\n", vm);
1095         while (*vm != '\0') {
1096                 if (*vm >= '0' && *vm <= '9') {
1097                         char *end;
1098
1099                         val = simple_strtoul(vm, &end, 0);
1100                         if (end > vm) {
1101                                 if (!xres_set) {
1102                                         if (val > panel_info.vl_col)
1103                                                 val = panel_info.vl_col;
1104                                         p->xres = val;
1105                                         panel_info.vl_col = val;
1106                                         xres_set = 1;
1107                                 } else if (!yres_set) {
1108                                         if (val > panel_info.vl_row)
1109                                                 val = panel_info.vl_row;
1110                                         p->yres = val;
1111                                         panel_info.vl_row = val;
1112                                         yres_set = 1;
1113                                 } else if (!bpp_set) {
1114                                         switch (val) {
1115                                         case 32:
1116                                         case 24:
1117                                                 if (is_lvds())
1118                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1119                                                 /* fallthru */
1120                                         case 16:
1121                                         case 8:
1122                                                 color_depth = val;
1123                                                 break;
1124
1125                                         case 18:
1126                                                 if (is_lvds()) {
1127                                                         color_depth = val;
1128                                                         break;
1129                                                 }
1130                                                 /* fallthru */
1131                                         default:
1132                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1133                                                         end - vm, vm, color_depth);
1134                                         }
1135                                         bpp_set = 1;
1136                                 } else if (!refresh_set) {
1137                                         refresh = val;
1138                                         refresh_set = 1;
1139                                 }
1140                         }
1141                         vm = end;
1142                 }
1143                 switch (*vm) {
1144                 case '@':
1145                         bpp_set = 1;
1146                         /* fallthru */
1147                 case '-':
1148                         yres_set = 1;
1149                         /* fallthru */
1150                 case 'x':
1151                         xres_set = 1;
1152                         /* fallthru */
1153                 case 'M':
1154                 case 'R':
1155                         vm++;
1156                         break;
1157
1158                 default:
1159                         if (*vm != '\0')
1160                                 vm++;
1161                 }
1162         }
1163         if (p->xres == 0 || p->yres == 0) {
1164                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1165                 lcd_enabled = 0;
1166                 printf("Supported video modes are:");
1167                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
1168                         printf(" %s", p->name);
1169                 }
1170                 printf("\n");
1171                 return;
1172         }
1173         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1174                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1175                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1176                 lcd_enabled = 0;
1177                 return;
1178         }
1179         panel_info.vl_col = p->xres;
1180         panel_info.vl_row = p->yres;
1181
1182         switch (color_depth) {
1183         case 8:
1184                 panel_info.vl_bpix = LCD_COLOR8;
1185                 break;
1186         case 16:
1187                 panel_info.vl_bpix = LCD_COLOR16;
1188                 break;
1189         default:
1190                 panel_info.vl_bpix = LCD_COLOR32;
1191         }
1192
1193         p->pixclock = KHZ2PICOS(refresh *
1194                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1195                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1196                                 1000);
1197         debug("Pixel clock set to %lu.%03lu MHz\n",
1198                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1199
1200         if (p != &fb_mode) {
1201                 int ret;
1202
1203                 debug("Creating new display-timing node from '%s'\n",
1204                         video_mode);
1205                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1206                 if (ret)
1207                         printf("Failed to create new display-timing node from '%s': %d\n",
1208                                 video_mode, ret);
1209         }
1210
1211         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1212         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1213                                         ARRAY_SIZE(stk5_lcd_pads));
1214
1215         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1216         switch (lcd_bus_width) {
1217         case 24:
1218                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1219                 break;
1220
1221         case 18:
1222                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1223                 break;
1224
1225         case 16:
1226                 if (!is_lvds()) {
1227                         pix_fmt = IPU_PIX_FMT_RGB565;
1228                         break;
1229                 }
1230                 /* fallthru */
1231         default:
1232                 lcd_enabled = 0;
1233                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1234                         lcd_bus_width);
1235                 return;
1236         }
1237         if (is_lvds()) {
1238                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1239                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1240                 uint32_t gpr2;
1241
1242                 if (lvds_chan_mask == 0) {
1243                         printf("No LVDS channel active\n");
1244                         lcd_enabled = 0;
1245                         return;
1246                 }
1247
1248                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1249                 if (lcd_bus_width == 24)
1250                         gpr2 |= (1 << 5) | (1 << 7);
1251                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1252                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1253                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1254                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1255         }
1256         if (karo_load_splashimage(0) == 0) {
1257                 int ret;
1258
1259                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1260
1261                 debug("Initializing LCD controller\n");
1262                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1263                 if (ret) {
1264                         printf("Failed to initialize FB driver: %d\n", ret);
1265                         lcd_enabled = 0;
1266                 }
1267         } else {
1268                 debug("Skipping initialization of LCD controller\n");
1269         }
1270 }
1271 #else
1272 #define lcd_enabled 0
1273 #endif /* CONFIG_LCD */
1274
1275 static void stk5_board_init(void)
1276 {
1277         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1278         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1279 }
1280
1281 static void stk5v3_board_init(void)
1282 {
1283         stk5_board_init();
1284 }
1285
1286 static void stk5v5_board_init(void)
1287 {
1288         stk5_board_init();
1289
1290         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1291                         "Flexcan Transceiver");
1292         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1293 }
1294
1295 static void tx53_set_cpu_clock(void)
1296 {
1297         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1298
1299         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1300                 return;
1301
1302         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1303                 printf("%s detected; skipping cpu clock change\n",
1304                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1305                 return;
1306         }
1307
1308         if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1309                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1310                 printf("CPU clock set to %lu.%03lu MHz\n",
1311                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1312         } else {
1313                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1314         }
1315 }
1316
1317 static void tx53_init_mac(void)
1318 {
1319         u8 mac[ETH_ALEN];
1320
1321         imx_get_mac_from_fuse(0, mac);
1322         if (!is_valid_ethaddr(mac)) {
1323                 printf("No valid MAC address programmed\n");
1324                 return;
1325         }
1326
1327         printf("MAC addr from fuse: %pM\n", mac);
1328         eth_setenv_enetaddr("ethaddr", mac);
1329 }
1330
1331 int board_late_init(void)
1332 {
1333         const char *baseboard;
1334
1335         env_cleanup();
1336
1337         tx53_set_cpu_clock();
1338
1339         if (had_ctrlc())
1340                 setenv_ulong("safeboot", 1);
1341         else if (wrsr & WRSR_TOUT)
1342                 setenv_ulong("wdreset", 1);
1343         else
1344                 karo_fdt_move_fdt();
1345
1346         baseboard = getenv("baseboard");
1347         if (!baseboard)
1348                 goto exit;
1349
1350         printf("Baseboard: %s\n", baseboard);
1351
1352         if (strncmp(baseboard, "stk5", 4) == 0) {
1353                 if ((strlen(baseboard) == 4) ||
1354                         strcmp(baseboard, "stk5-v3") == 0) {
1355                         stk5v3_board_init();
1356                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1357                         const char *otg_mode = getenv("otg_mode");
1358
1359                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1360                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1361                                         otg_mode, baseboard);
1362                                 setenv("otg_mode", "none");
1363                         }
1364                         stk5v5_board_init();
1365                 } else {
1366                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1367                                 baseboard + 4);
1368                 }
1369         } else {
1370                 printf("WARNING: Unsupported baseboard: '%s'\n",
1371                         baseboard);
1372                 if (!had_ctrlc())
1373                         return -EINVAL;
1374         }
1375
1376 exit:
1377         tx53_init_mac();
1378
1379         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1380         clear_ctrlc();
1381
1382         get_hab_status();
1383
1384         return 0;
1385 }
1386
1387 int checkboard(void)
1388 {
1389         tx53_print_cpuinfo();
1390 #if CONFIG_SYS_SDRAM_SIZE < SZ_1G
1391         printf("Board: Ka-Ro TX53-8%d3%c\n",
1392                 is_lvds(), '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1393 #elif CONFIG_SYS_SDRAM_SIZE < SZ_2G
1394         printf("Board: Ka-Ro TX53-1%d3%c\n",
1395                 is_lvds() + 2, '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1396 #else
1397         printf("Board: Ka-Ro TX53-123%c\n",
1398                 '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1399 #endif
1400         return 0;
1401 }
1402
1403 #if defined(CONFIG_OF_BOARD_SETUP)
1404 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1405 #include <jffs2/jffs2.h>
1406 #include <mtd_node.h>
1407 static struct node_info nodes[] = {
1408         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1409 };
1410 #else
1411 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1412 #endif
1413
1414 #ifdef CONFIG_SYS_TX53_HWREV_2
1415 static void tx53_fixup_rtc(void *blob)
1416 {
1417         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1418         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1419 }
1420 #else
1421 static inline void tx53_fixup_rtc(void *blob)
1422 {
1423 }
1424 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1425
1426 static const char *tx53_touchpanels[] = {
1427         "ti,tsc2007",
1428         "edt,edt-ft5x06",
1429         "eeti,egalax_ts",
1430 };
1431
1432 int ft_board_setup(void *blob, bd_t *bd)
1433 {
1434         const char *baseboard = getenv("baseboard");
1435         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1436         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1437         int ret;
1438
1439         ret = fdt_increase_size(blob, 4096);
1440         if (ret) {
1441                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1442                 return ret;
1443         }
1444         if (stk5_v5)
1445                 karo_fdt_enable_node(blob, "stk5led", 0);
1446
1447         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1448
1449         karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1450                                 ARRAY_SIZE(tx53_touchpanels));
1451         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1452         karo_fdt_fixup_flexcan(blob, stk5_v5);
1453         tx53_fixup_rtc(blob);
1454         karo_fdt_update_fb_mode(blob, video_mode);
1455
1456         return 0;
1457 }
1458 #endif /* CONFIG_OF_BOARD_SETUP */