board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <i2c.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mxcfb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx53.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 #include "../common/karo.h"
  41
  42 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  43 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  44 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  45 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  46
  47 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  48 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  50
  51 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  56                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  57
  58 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  59                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  60
  61 static iomux_v3_cfg_t tx53_pads[] = {
  62         /* NAND flash pads are set up in lowlevel_init.S */
  63
  64         /* UART pads */
  65 #if CONFIG_MXC_UART_BASE == UART1_BASE
  66         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  67         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  68         MX53_PAD_PATA_IORDY__UART1_RTS,
  69         MX53_PAD_PATA_RESET_B__UART1_CTS,
  70 #endif
  71 #if CONFIG_MXC_UART_BASE == UART2_BASE
  72         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  73         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  74         MX53_PAD_PATA_DIOR__UART2_RTS,
  75         MX53_PAD_PATA_INTRQ__UART2_CTS,
  76 #endif
  77 #if CONFIG_MXC_UART_BASE == UART3_BASE
  78         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  79         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  80         MX53_PAD_PATA_DA_2__UART3_RTS,
  81         MX53_PAD_PATA_DA_1__UART3_CTS,
  82 #endif
  83         /* internal I2C */
  84         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  85         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  86
  87         /* FEC PHY GPIO functions */
  88         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  89         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  90         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  91
  92         /* FEC functions */
  93         MX53_PAD_FEC_MDC__FEC_MDC,
  94         MX53_PAD_FEC_MDIO__FEC_MDIO,
  95         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  96         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  97         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  98         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  99         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 100         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 101         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 102         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 103 };
 104
 105 static const struct gpio tx53_gpios[] = {
 106         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 107         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 108         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 109         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 110 };
 111
 112 /*
 113  * Functions
 114  */
 115 /* placed in section '.data' to prevent overwriting relocation info
 116  * overlayed with bss
 117  */
 118 static u32 wrsr __attribute__((section(".data")));
 119
 120 #define WRSR_POR        (1 << 4)
 121 #define WRSR_TOUT       (1 << 1)
 122 #define WRSR_SFTW       (1 << 0)
 123
 124 static void print_reset_cause(void)
 125 {
 126         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 127         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 128         u32 srsr;
 129         char *dlm = "";
 130
 131         printf("Reset cause: ");
 132
 133         srsr = readl(&src_regs->srsr);
 134         wrsr = readw(wdt_base + 4);
 135
 136         if (wrsr & WRSR_POR) {
 137                 printf("%sPOR", dlm);
 138                 dlm = " | ";
 139         }
 140         if (srsr & 0x00004) {
 141                 printf("%sCSU", dlm);
 142                 dlm = " | ";
 143         }
 144         if (srsr & 0x00008) {
 145                 printf("%sIPP USER", dlm);
 146                 dlm = " | ";
 147         }
 148         if (srsr & 0x00010) {
 149                 if (wrsr & WRSR_SFTW) {
 150                         printf("%sSOFT", dlm);
 151                         dlm = " | ";
 152                 }
 153                 if (wrsr & WRSR_TOUT) {
 154                         printf("%sWDOG", dlm);
 155                         dlm = " | ";
 156                 }
 157         }
 158         if (srsr & 0x00020) {
 159                 printf("%sJTAG HIGH-Z", dlm);
 160                 dlm = " | ";
 161         }
 162         if (srsr & 0x00040) {
 163                 printf("%sJTAG SW", dlm);
 164                 dlm = " | ";
 165         }
 166         if (srsr & 0x10000) {
 167                 printf("%sWARM BOOT", dlm);
 168                 dlm = " | ";
 169         }
 170         if (dlm[0] == '\0')
 171                 printf("unknown");
 172
 173         printf("\n");
 174 }
 175
 176 static void tx53_print_cpuinfo(void)
 177 {
 178         u32 cpurev;
 179
 180         cpurev = get_cpu_rev();
 181
 182         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 183                 (cpurev & 0x000F0) >> 4,
 184                 (cpurev & 0x0000F) >> 0,
 185                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 186
 187         print_reset_cause();
 188 }
 189
 190 enum LTC3589_REGS {
 191         LTC3589_SCR1 = 0x07,
 192         LTC3589_CLIRQ = 0x21,
 193         LTC3589_B1DTV1 = 0x23,
 194         LTC3589_B1DTV2 = 0x24,
 195         LTC3589_VRRCR = 0x25,
 196         LTC3589_B2DTV1 = 0x26,
 197         LTC3589_B2DTV2 = 0x27,
 198         LTC3589_B3DTV1 = 0x29,
 199         LTC3589_B3DTV2 = 0x2a,
 200         LTC3589_L2DTV1 = 0x32,
 201         LTC3589_L2DTV2 = 0x33,
 202 };
 203
 204 #define LTC3589_PGOOD_MASK      (1 << 5)
 205
 206 #define LTC3589_CLK_RATE_LOW    (1 << 5)
 207
 208 #define VDD_LDO2_VAL            mV_to_regval(vout_to_vref(1325 * 10, 2))
 209 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1240 * 10, 3))
 210 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1325 * 10, 4))
 211 #define VDD_BUCK3_VAL           mV_to_regval(vout_to_vref(2500 * 10, 5))
 212
 213 #ifndef CONFIG_SYS_TX53_HWREV_2
 214 /* LDO2 vref divider */
 215 #define R1_2    180
 216 #define R2_2    191
 217 /* BUCK1 vref divider */
 218 #define R1_3    150
 219 #define R2_3    180
 220 /* BUCK2 vref divider */
 221 #define R1_4    180
 222 #define R2_4    191
 223 /* BUCK3 vref divider */
 224 #define R1_5    270
 225 #define R2_5    100
 226 #else
 227 /* no dividers on vref */
 228 #define R1_2    0
 229 #define R2_2    1
 230 #define R1_3    0
 231 #define R2_3    1
 232 #define R1_4    0
 233 #define R2_4    1
 234 #define R1_5    0
 235 #define R2_5    1
 236 #endif
 237
 238 /* calculate voltages in 10mV */
 239 #define R1(idx)                 R1_##idx
 240 #define R2(idx)                 R2_##idx
 241
 242 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
 243 #define vref_to_vout(vref, idx) ((vref) * (R1(idx) + R2(idx)) / R2(idx))
 244
 245 #define mV_to_regval(mV)        (((((mV) < 3625) ? 3625 : (mV)) - 3625) / 125)
 246 #define regval_to_mV(v)         (((v) * 125 + 3625))
 247
 248 static struct pmic_regs {
 249         enum LTC3589_REGS addr;
 250         u8 val;
 251 } ltc3589_regs[] = {
 252         { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators */
 253
 254         { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_PGOOD_MASK, },
 255         { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
 256
 257         { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_PGOOD_MASK, },
 258         { LTC3589_B1DTV2, VDD_CORE_VAL, },
 259
 260         { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_PGOOD_MASK, },
 261         { LTC3589_B2DTV2, VDD_SOC_VAL, },
 262
 263         { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_PGOOD_MASK, },
 264         { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
 265
 266         { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
 267 };
 268
 269 static int setup_pmic_voltages(void)
 270 {
 271         int ret;
 272         unsigned char value;
 273         int i;
 274
 275         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 276         if (ret != 0) {
 277                 printf("Failed to initialize I2C\n");
 278                 return ret;
 279         }
 280
 281         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 282         if (ret) {
 283                 printf("%s: i2c_read error: %d\n", __func__, ret);
 284                 return ret;
 285         }
 286
 287         for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
 288                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 289                                 &value, 1);
 290                 debug("Writing %02x to reg %02x (%02x)\n",
 291                         ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
 292                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 293                                 &ltc3589_regs[i].val, 1);
 294                 if (ret) {
 295                         printf("%s: failed to write PMIC register %02x: %d\n",
 296                                 __func__, ltc3589_regs[i].addr, ret);
 297                         return ret;
 298                 }
 299         }
 300         printf("VDDCORE set to %umV\n",
 301                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
 302
 303         printf("VDDSOC  set to %umV\n",
 304                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
 305         return 0;
 306 }
 307
 308 int board_early_init_f(void)
 309 {
 310         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 311
 312         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 313         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 314
 315         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 316         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 317
 318         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 319         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 320         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 321         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 322         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 323
 324         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 325         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 326
 327         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 328         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 329         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 330         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 331         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 332
 333         writel(0xffcf0fff, &ccm_regs->CCGR0);
 334         writel(0x000fffc3, &ccm_regs->CCGR1);
 335         writel(0x033c0000, &ccm_regs->CCGR2);
 336         writel(0x000000ff, &ccm_regs->CCGR3);
 337         writel(0x00000000, &ccm_regs->CCGR4);
 338         writel(0x00fff033, &ccm_regs->CCGR5);
 339         writel(0x0f00030f, &ccm_regs->CCGR6);
 340         writel(0xfff00000, &ccm_regs->CCGR7);
 341         writel(0x00000000, &ccm_regs->cmeor);
 342
 343         return 0;
 344 }
 345
 346 int board_init(void)
 347 {
 348         int ret;
 349
 350         /* Address of boot parameters */
 351         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 352
 353         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 354                 printf("CTRL-C detected; Skipping PMIC setup\n");
 355                 return 1;
 356         }
 357
 358         ret = setup_pmic_voltages();
 359         if (ret) {
 360                 printf("Failed to setup PMIC voltages\n");
 361                 hang();
 362         }
 363         return 0;
 364 }
 365
 366 int dram_init(void)
 367 {
 368         int ret;
 369
 370         /* dram_init must store complete ramsize in gd->ram_size */
 371         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 372                                 PHYS_SDRAM_1_SIZE);
 373
 374         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 375                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 376         if (ret)
 377                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 378                         CONFIG_SYS_SDRAM_CLK, ret);
 379         else
 380                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 381                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 382                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 383                         CONFIG_SYS_SDRAM_CLK);
 384         return ret;
 385 }
 386
 387 void dram_init_banksize(void)
 388 {
 389         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 390         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 391                         PHYS_SDRAM_1_SIZE);
 392 #if CONFIG_NR_DRAM_BANKS > 1
 393         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 394         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 395                         PHYS_SDRAM_2_SIZE);
 396 #endif
 397 }
 398
 399 #ifdef  CONFIG_CMD_MMC
 400 static const iomux_v3_cfg_t mmc0_pads[] = {
 401         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 402         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 403         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 404         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 405         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 406         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 407         /* SD1 CD */
 408         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 409 };
 410
 411 static const iomux_v3_cfg_t mmc1_pads[] = {
 412         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 413         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 414         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 415         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 416         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 417         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 418         /* SD2 CD */
 419         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 420 };
 421
 422 static struct tx53_esdhc_cfg {
 423         const iomux_v3_cfg_t *pads;
 424         int num_pads;
 425         struct fsl_esdhc_cfg cfg;
 426         int cd_gpio;
 427 } tx53_esdhc_cfg[] = {
 428         {
 429                 .pads = mmc0_pads,
 430                 .num_pads = ARRAY_SIZE(mmc0_pads),
 431                 .cfg = {
 432                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 433                         .max_bus_width = 4,
 434                 },
 435                 .cd_gpio = IMX_GPIO_NR(3, 24),
 436         },
 437         {
 438                 .pads = mmc1_pads,
 439                 .num_pads = ARRAY_SIZE(mmc1_pads),
 440                 .cfg = {
 441                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 442                         .max_bus_width = 4,
 443                 },
 444                 .cd_gpio = IMX_GPIO_NR(3, 25),
 445         },
 446 };
 447
 448 #define to_tx53_esdhc_cfg(p) container_of(p, struct tx53_esdhc_cfg, cfg)
 449
 450 int board_mmc_getcd(struct mmc *mmc)
 451 {
 452         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
 453
 454         if (cfg->cd_gpio < 0)
 455                 return cfg->cd_gpio;
 456
 457         debug("SD card %d is %spresent\n",
 458                 cfg - tx53_esdhc_cfg,
 459                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 460         return !gpio_get_value(cfg->cd_gpio);
 461 }
 462
 463 int board_mmc_init(bd_t *bis)
 464 {
 465         int i;
 466
 467         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
 468                 struct mmc *mmc;
 469                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
 470                 int ret;
 471
 472                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 473                         break;
 474
 475                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 476                                                 cfg->num_pads);
 477                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 478
 479                 fsl_esdhc_initialize(bis, &cfg->cfg);
 480
 481                 ret = gpio_request_one(cfg->cd_gpio,
 482                                 GPIOF_INPUT, "MMC CD");
 483                 if (ret) {
 484                         printf("Error %d requesting GPIO%d_%d\n",
 485                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 486                         continue;
 487                 }
 488
 489                 mmc = find_mmc_device(i);
 490                 if (mmc == NULL)
 491                         continue;
 492                 if (board_mmc_getcd(mmc) > 0)
 493                         mmc_init(mmc);
 494         }
 495         return 0;
 496 }
 497 #endif /* CONFIG_CMD_MMC */
 498
 499 #ifdef CONFIG_FEC_MXC
 500
 501 #ifndef ETH_ALEN
 502 #define ETH_ALEN 6
 503 #endif
 504
 505 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 506 {
 507         int i;
 508         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 509         struct fuse_bank *bank = &iim->bank[1];
 510         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 511
 512         if (dev_id > 0)
 513                 return;
 514
 515         for (i = 0; i < ETH_ALEN; i++)
 516                 mac[i] = readl(&fuse->mac_addr[i]);
 517 }
 518
 519 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 520                         PAD_CTL_SRE_FAST)
 521 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 522 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 523
 524 int board_eth_init(bd_t *bis)
 525 {
 526         int ret;
 527
 528         /* delay at least 21ms for the PHY internal POR signal to deassert */
 529         udelay(22000);
 530
 531         /* Deassert RESET to the external phy */
 532         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 533
 534         ret = cpu_eth_init(bis);
 535         if (ret)
 536                 printf("cpu_eth_init() failed: %d\n", ret);
 537         return ret;
 538 }
 539 #endif /* CONFIG_FEC_MXC */
 540
 541 enum {
 542         LED_STATE_INIT = -1,
 543         LED_STATE_OFF,
 544         LED_STATE_ON,
 545 };
 546
 547 void show_activity(int arg)
 548 {
 549         static int led_state = LED_STATE_INIT;
 550         static ulong last;
 551
 552         if (led_state == LED_STATE_INIT) {
 553                 last = get_timer(0);
 554                 gpio_set_value(TX53_LED_GPIO, 1);
 555                 led_state = LED_STATE_ON;
 556         } else {
 557                 if (get_timer(last) > CONFIG_SYS_HZ) {
 558                         last = get_timer(0);
 559                         if (led_state == LED_STATE_ON) {
 560                                 gpio_set_value(TX53_LED_GPIO, 0);
 561                         } else {
 562                                 gpio_set_value(TX53_LED_GPIO, 1);
 563                         }
 564                         led_state = 1 - led_state;
 565                 }
 566         }
 567 }
 568
 569 static const iomux_v3_cfg_t stk5_pads[] = {
 570         /* SW controlled LED on STK5 baseboard */
 571         MX53_PAD_EIM_A18__GPIO2_20,
 572
 573         /* I2C bus on DIMM pins 40/41 */
 574         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 575         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 576
 577         /* TSC200x PEN IRQ */
 578         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 579
 580         /* EDT-FT5x06 Polytouch panel */
 581         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 582         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 583         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 584
 585         /* USBH1 */
 586         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 587         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 588         /* USBOTG */
 589         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 590         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 591
 592         /* DS1339 Interrupt */
 593         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 594 };
 595
 596 static const struct gpio stk5_gpios[] = {
 597         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 598
 599         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 600         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 601         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 602         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 603 };
 604
 605 #ifdef CONFIG_LCD
 606 vidinfo_t panel_info = {
 607         /* set to max. size supported by SoC */
 608         .vl_col = 1600,
 609         .vl_row = 1200,
 610
 611         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 612 };
 613
 614 static struct fb_videomode tx53_fb_modes[] = {
 615         {
 616                 /* Standard VGA timing */
 617                 .name           = "VGA",
 618                 .refresh        = 60,
 619                 .xres           = 640,
 620                 .yres           = 480,
 621                 .pixclock       = KHZ2PICOS(25175),
 622                 .left_margin    = 48,
 623                 .hsync_len      = 96,
 624                 .right_margin   = 16,
 625                 .upper_margin   = 31,
 626                 .vsync_len      = 2,
 627                 .lower_margin   = 12,
 628                 .sync           = FB_SYNC_CLK_LAT_FALL,
 629         },
 630         {
 631                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 632                  * DE high active, 115.2 mm x 86.4 mm display area
 633                  * VGA compatible timing
 634                  */
 635                 .name           = "ETV570",
 636                 .refresh        = 60,
 637                 .xres           = 640,
 638                 .yres           = 480,
 639                 .pixclock       = KHZ2PICOS(25175),
 640                 .left_margin    = 114,
 641                 .hsync_len      = 30,
 642                 .right_margin   = 16,
 643                 .upper_margin   = 32,
 644                 .vsync_len      = 3,
 645                 .lower_margin   = 10,
 646                 .sync           = FB_SYNC_CLK_LAT_FALL,
 647         },
 648         {
 649                 /* Emerging ET0350G0DH6 320 x 240 display.
 650                  * 70.08 mm x 52.56 mm display area.
 651                  */
 652                 .name           = "ET0350",
 653                 .refresh        = 60,
 654                 .xres           = 320,
 655                 .yres           = 240,
 656                 .pixclock       = KHZ2PICOS(6500),
 657                 .left_margin    = 68 - 34,
 658                 .hsync_len      = 34,
 659                 .right_margin   = 20,
 660                 .upper_margin   = 18 - 3,
 661                 .vsync_len      = 3,
 662                 .lower_margin   = 4,
 663                 .sync           = FB_SYNC_CLK_LAT_FALL,
 664         },
 665         {
 666                 /* Emerging ET0430G0DH6 480 x 272 display.
 667                  * 95.04 mm x 53.856 mm display area.
 668                  */
 669                 .name           = "ET0430",
 670                 .refresh        = 60,
 671                 .xres           = 480,
 672                 .yres           = 272,
 673                 .pixclock       = KHZ2PICOS(9000),
 674                 .left_margin    = 2,
 675                 .hsync_len      = 41,
 676                 .right_margin   = 2,
 677                 .upper_margin   = 2,
 678                 .vsync_len      = 10,
 679                 .lower_margin   = 2,
 680                 .sync           = FB_SYNC_CLK_LAT_FALL,
 681         },
 682         {
 683                 /* Emerging ET0500G0DH6 800 x 480 display.
 684                  * 109.6 mm x 66.4 mm display area.
 685                  */
 686                 .name           = "ET0500",
 687                 .refresh        = 60,
 688                 .xres           = 800,
 689                 .yres           = 480,
 690                 .pixclock       = KHZ2PICOS(33260),
 691                 .left_margin    = 216 - 128,
 692                 .hsync_len      = 128,
 693                 .right_margin   = 1056 - 800 - 216,
 694                 .upper_margin   = 35 - 2,
 695                 .vsync_len      = 2,
 696                 .lower_margin   = 525 - 480 - 35,
 697                 .sync           = FB_SYNC_CLK_LAT_FALL,
 698         },
 699         {
 700                 /* Emerging ETQ570G0DH6 320 x 240 display.
 701                  * 115.2 mm x 86.4 mm display area.
 702                  */
 703                 .name           = "ETQ570",
 704                 .refresh        = 60,
 705                 .xres           = 320,
 706                 .yres           = 240,
 707                 .pixclock       = KHZ2PICOS(6400),
 708                 .left_margin    = 38,
 709                 .hsync_len      = 30,
 710                 .right_margin   = 30,
 711                 .upper_margin   = 16, /* 15 according to datasheet */
 712                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 713                 .lower_margin   = 4, /* 4.5 according to datasheet */
 714                 .sync           = FB_SYNC_CLK_LAT_FALL,
 715         },
 716         {
 717                 /* Emerging ET0700G0DH6 800 x 480 display.
 718                  * 152.4 mm x 91.44 mm display area.
 719                  */
 720                 .name           = "ET0700",
 721                 .refresh        = 60,
 722                 .xres           = 800,
 723                 .yres           = 480,
 724                 .pixclock       = KHZ2PICOS(33260),
 725                 .left_margin    = 216 - 128,
 726                 .hsync_len      = 128,
 727                 .right_margin   = 1056 - 800 - 216,
 728                 .upper_margin   = 35 - 2,
 729                 .vsync_len      = 2,
 730                 .lower_margin   = 525 - 480 - 35,
 731                 .sync           = FB_SYNC_CLK_LAT_FALL,
 732         },
 733         {
 734                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 735                 .refresh        = 60,
 736                 .left_margin    = 48,
 737                 .hsync_len      = 96,
 738                 .right_margin   = 16,
 739                 .upper_margin   = 31,
 740                 .vsync_len      = 2,
 741                 .lower_margin   = 12,
 742                 .sync           = FB_SYNC_CLK_LAT_FALL,
 743         },
 744 };
 745
 746 static int lcd_enabled = 1;
 747
 748 void lcd_enable(void)
 749 {
 750         /* HACK ALERT:
 751          * global variable from common/lcd.c
 752          * Set to 0 here to prevent messages from going to LCD
 753          * rather than serial console
 754          */
 755         lcd_is_enabled = 0;
 756
 757         if (lcd_enabled) {
 758                 karo_load_splashimage(1);
 759
 760                 debug("Switching LCD on\n");
 761                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 762                 udelay(100);
 763                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 764                 udelay(300000);
 765                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
 766         }
 767 }
 768
 769 void lcd_disable(void)
 770 {
 771         if (lcd_enabled) {
 772                 printf("Disabling LCD\n");
 773                 ipuv3_fb_shutdown();
 774         }
 775 }
 776
 777 void lcd_panel_disable(void)
 778 {
 779         if (lcd_enabled) {
 780                 debug("Switching LCD off\n");
 781                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1);
 782                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 783                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 784         }
 785 }
 786
 787 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 788         /* LCD RESET */
 789         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 790         /* LCD POWER_ENABLE */
 791         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 792         /* LCD Backlight (PWM) */
 793         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 794
 795         /* Display */
 796         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 797         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 798         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 799         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 800         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 801         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 802         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 803         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 804         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 805         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 806         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 807         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 808         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 809         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 810         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 811         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 812         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 813         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 814         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 815         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 816         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 817         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 818         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 819         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 820         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 821         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 822         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 823         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 824
 825         /* LVDS option */
 826         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 827         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 828         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 829         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 830         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 831         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 832         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 833         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 834         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 835         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 836 };
 837
 838 static const struct gpio stk5_lcd_gpios[] = {
 839         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 840         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 841         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 842 };
 843
 844 void lcd_ctrl_init(void *lcdbase)
 845 {
 846         int color_depth = 24;
 847         const char *video_mode = getenv("video_mode");
 848         const char *vm;
 849         unsigned long val;
 850         int refresh = 60;
 851         struct fb_videomode *p = &tx53_fb_modes[0];
 852         struct fb_videomode fb_mode;
 853         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 854         int pix_fmt = 0;
 855         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 856         unsigned long di_clk_rate = 65000000;
 857
 858         if (!lcd_enabled) {
 859                 debug("LCD disabled\n");
 860                 return;
 861         }
 862
 863         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 864                 debug("Disabling LCD\n");
 865                 lcd_enabled = 0;
 866                 setenv("splashimage", NULL);
 867                 return;
 868         }
 869
 870         karo_fdt_move_fdt();
 871
 872         vm = karo_fdt_set_display(video_mode, "/soc", "/soc/aips/ldb");
 873         if (vm == NULL) {
 874                 debug("Disabling LCD\n");
 875                 lcd_enabled = 0;
 876                 return;
 877         }
 878         video_mode = vm;
 879         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 880                 p = &fb_mode;
 881                 debug("Using video mode from FDT\n");
 882                 vm += strlen(vm);
 883                 if (fb_mode.xres > panel_info.vl_col ||
 884                         fb_mode.yres > panel_info.vl_row) {
 885                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 886                                 fb_mode.xres, fb_mode.yres,
 887                                 panel_info.vl_col, panel_info.vl_row);
 888                         lcd_enabled = 0;
 889                         return;
 890                 }
 891         }
 892         if (p->name != NULL)
 893                 debug("Trying compiled-in video modes\n");
 894         while (p->name != NULL) {
 895                 if (strcmp(p->name, vm) == 0) {
 896                         debug("Using video mode: '%s'\n", p->name);
 897                         vm += strlen(vm);
 898                         break;
 899                 }
 900                 p++;
 901         }
 902         if (*vm != '\0')
 903                 debug("Trying to decode video_mode: '%s'\n", vm);
 904         while (*vm != '\0') {
 905                 if (*vm >= '0' && *vm <= '9') {
 906                         char *end;
 907
 908                         val = simple_strtoul(vm, &end, 0);
 909                         if (end > vm) {
 910                                 if (!xres_set) {
 911                                         if (val > panel_info.vl_col)
 912                                                 val = panel_info.vl_col;
 913                                         p->xres = val;
 914                                         panel_info.vl_col = val;
 915                                         xres_set = 1;
 916                                 } else if (!yres_set) {
 917                                         if (val > panel_info.vl_row)
 918                                                 val = panel_info.vl_row;
 919                                         p->yres = val;
 920                                         panel_info.vl_row = val;
 921                                         yres_set = 1;
 922                                 } else if (!bpp_set) {
 923                                         switch (val) {
 924                                         case 32:
 925                                         case 24:
 926                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 927                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 928                                                 /* fallthru */
 929                                         case 16:
 930                                         case 8:
 931                                                 color_depth = val;
 932                                                 break;
 933
 934                                         case 18:
 935                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 936                                                         color_depth = val;
 937                                                         break;
 938                                                 }
 939                                                 /* fallthru */
 940                                         default:
 941                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 942                                                         end - vm, vm, color_depth);
 943                                         }
 944                                         bpp_set = 1;
 945                                 } else if (!refresh_set) {
 946                                         refresh = val;
 947                                         refresh_set = 1;
 948                                 }
 949                         }
 950                         vm = end;
 951                 }
 952                 switch (*vm) {
 953                 case '@':
 954                         bpp_set = 1;
 955                         /* fallthru */
 956                 case '-':
 957                         yres_set = 1;
 958                         /* fallthru */
 959                 case 'x':
 960                         xres_set = 1;
 961                         /* fallthru */
 962                 case 'M':
 963                 case 'R':
 964                         vm++;
 965                         break;
 966
 967                 default:
 968                         if (!pix_fmt) {
 969                                 char *tmp;
 970
 971                                 if (strncmp(vm, "LVDS", 4) == 0) {
 972                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 973                                         di_clk_parent = DI_PCLK_LDB;
 974                                 } else {
 975                                         pix_fmt = IPU_PIX_FMT_RGB24;
 976                                 }
 977                                 tmp = strchr(vm, ':');
 978                                 if (tmp)
 979                                         vm = tmp;
 980                         }
 981                         if (*vm != '\0')
 982                                 vm++;
 983                 }
 984         }
 985         if (p->xres == 0 || p->yres == 0) {
 986                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 987                 lcd_enabled = 0;
 988                 printf("Supported video modes are:");
 989                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
 990                         printf(" %s", p->name);
 991                 }
 992                 printf("\n");
 993                 return;
 994         }
 995         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 996                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 997                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 998                 lcd_enabled = 0;
 999                 return;
1000         }
1001         panel_info.vl_col = p->xres;
1002         panel_info.vl_row = p->yres;
1003
1004         switch (color_depth) {
1005         case 8:
1006                 panel_info.vl_bpix = LCD_COLOR8;
1007                 break;
1008         case 16:
1009                 panel_info.vl_bpix = LCD_COLOR16;
1010                 break;
1011         default:
1012                 panel_info.vl_bpix = LCD_COLOR24;
1013         }
1014
1015         p->pixclock = KHZ2PICOS(refresh *
1016                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1017                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
1018                 / 1000);
1019         debug("Pixel clock set to %lu.%03lu MHz\n",
1020                 PICOS2KHZ(p->pixclock) / 1000,
1021                 PICOS2KHZ(p->pixclock) % 1000);
1022
1023         if (p != &fb_mode) {
1024                 int ret;
1025
1026                 debug("Creating new display-timing node from '%s'\n",
1027                         video_mode);
1028                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1029                 if (ret)
1030                         printf("Failed to create new display-timing node from '%s': %d\n",
1031                                 video_mode, ret);
1032         }
1033
1034         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1035         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1036                                         ARRAY_SIZE(stk5_lcd_pads));
1037
1038         debug("Initializing FB driver\n");
1039         if (!pix_fmt)
1040                 pix_fmt = IPU_PIX_FMT_RGB24;
1041         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
1042                 writel(0x01, IOMUXC_BASE_ADDR + 8);
1043         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
1044                 writel(0x21, IOMUXC_BASE_ADDR + 8);
1045         }
1046         if (pix_fmt != IPU_PIX_FMT_RGB24) {
1047                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1048                 /* enable LDB & DI0 clock */
1049                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
1050                         &ccm_regs->CCGR6);
1051         }
1052
1053         if (karo_load_splashimage(0) == 0) {
1054                 int ret;
1055
1056                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1057
1058                 debug("Initializing LCD controller\n");
1059                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1060                 if (ret) {
1061                         printf("Failed to initialize FB driver: %d\n", ret);
1062                         lcd_enabled = 0;
1063                 }
1064         } else {
1065                 debug("Skipping initialization of LCD controller\n");
1066         }
1067 }
1068 #else
1069 #define lcd_enabled 0
1070 #endif /* CONFIG_LCD */
1071
1072 static void stk5_board_init(void)
1073 {
1074         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1075         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1076 }
1077
1078 static void stk5v3_board_init(void)
1079 {
1080         stk5_board_init();
1081 }
1082
1083 static void stk5v5_board_init(void)
1084 {
1085         stk5_board_init();
1086
1087         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1088                         "Flexcan Transceiver");
1089         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1090 }
1091
1092 static void tx53_set_cpu_clock(void)
1093 {
1094         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1095         int ret;
1096
1097         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1098                 return;
1099
1100         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1101                 return;
1102
1103         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
1104         if (ret != 0) {
1105                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1106                 return;
1107         }
1108         printf("CPU clock set to %u.%03u MHz\n",
1109                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
1110                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
1111 }
1112
1113 static void tx53_init_mac(void)
1114 {
1115         u8 mac[ETH_ALEN];
1116
1117         imx_get_mac_from_fuse(0, mac);
1118         if (!is_valid_ether_addr(mac)) {
1119                 printf("No valid MAC address programmed\n");
1120                 return;
1121         }
1122
1123         eth_setenv_enetaddr("ethaddr", mac);
1124         printf("MAC addr from fuse: %pM\n", mac);
1125 }
1126
1127 int board_late_init(void)
1128 {
1129         int ret = 0;
1130         const char *baseboard;
1131
1132         tx53_set_cpu_clock();
1133         karo_fdt_move_fdt();
1134
1135         baseboard = getenv("baseboard");
1136         if (!baseboard)
1137                 goto exit;
1138
1139         if (strncmp(baseboard, "stk5", 4) == 0) {
1140                 printf("Baseboard: %s\n", baseboard);
1141                 if ((strlen(baseboard) == 4) ||
1142                         strcmp(baseboard, "stk5-v3") == 0) {
1143                         stk5v3_board_init();
1144                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1145                         stk5v5_board_init();
1146                 } else {
1147                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1148                                 baseboard + 4);
1149                 }
1150         } else {
1151                 printf("WARNING: Unsupported baseboard: '%s'\n",
1152                         baseboard);
1153                 ret = -EINVAL;
1154         }
1155
1156 exit:
1157         tx53_init_mac();
1158         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1159         clear_ctrlc();
1160         return ret;
1161 }
1162
1163 int checkboard(void)
1164 {
1165         tx53_print_cpuinfo();
1166
1167         printf("Board: Ka-Ro TX53-xx3%s\n",
1168                 TX53_MOD_SUFFIX);
1169
1170         return 0;
1171 }
1172
1173 #if defined(CONFIG_OF_BOARD_SETUP)
1174 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1175 #include <jffs2/jffs2.h>
1176 #include <mtd_node.h>
1177 struct node_info nodes[] = {
1178         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1179 };
1180
1181 #else
1182 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1183 #endif
1184
1185 #ifdef CONFIG_SYS_TX53_HWREV_2
1186 void tx53_fixup_rtc(void *blob)
1187 {
1188         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1189         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1190 }
1191 #else
1192 static inline void tx53_fixup_rtc(void *blob)
1193 {
1194 }
1195 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1196
1197 static const char *tx53_touchpanels[] = {
1198         "ti,tsc2007",
1199         "edt,edt-ft5x06",
1200 };
1201
1202 void ft_board_setup(void *blob, bd_t *bd)
1203 {
1204         const char *baseboard = getenv("baseboard");
1205         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1206         const char *video_mode = getenv("video_mode");
1207
1208         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1209         fdt_fixup_ethernet(blob);
1210
1211         karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1212                                 ARRAY_SIZE(tx53_touchpanels));
1213         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1214         karo_fdt_fixup_flexcan(blob, stk5_v5);
1215         tx53_fixup_rtc(blob);
1216         video_mode = karo_fdt_set_display(video_mode, "/soc", "/soc/aips/ldb");
1217         karo_fdt_update_fb_mode(blob, video_mode);
1218 }
1219 #endif /* CONFIG_OF_BOARD_SETUP */