board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <errno.h>
  26 #include <libfdt.h>
  27 #include <fsl_esdhc.h>
  28 #include <mmc.h>
  29 #include <netdev.h>
  30 #include <fdt_support.h>
  31 #include <lcd.h>
  32 #include <video_fb.h>
  33 #include <ipu_pixfmt.h>
  34 #include <mx2fb.h>
  35 #include <linux/fb.h>
  36 #include <asm/string.h>
  37 #include <asm/io.h>
  38 #include <asm/gpio.h>
  39 #include <asm/arch/sys_proto.h>
  40 #include <asm/arch/iomux-mx53.h>
  41 #include <asm/arch/clock.h>
  42 #include <asm/arch/imx-regs.h>
  43 #include <asm/arch/crm_regs.h>
  44
  45 #define IMX_GPIO_NR(b, o)       ((((b) - 1) << 5) | (o))
  46
  47 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  48 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  49 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  50 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  51
  52 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  53 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  54 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  55
  56 DECLARE_GLOBAL_DATA_PTR;
  57
  58 #define IOMUX_SION              IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  59
  60 #define MX53_GPIO_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE |            \
  61                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  62
  63 #define TX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_DSE_HIGH |       \
  64                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN)
  65
  66 static iomux_v3_cfg_t tx53_pads[] = {
  67         /* UART pads */
  68         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  69         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  70         MX53_PAD_PATA_IORDY__UART1_RTS,
  71         MX53_PAD_PATA_RESET_B__UART1_CTS,
  72
  73         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  74         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  75         MX53_PAD_PATA_DIOR__UART2_RTS,
  76         MX53_PAD_PATA_INTRQ__UART2_CTS,
  77
  78         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  79         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  80         MX53_PAD_PATA_DA_2__UART3_RTS,
  81         MX53_PAD_PATA_DA_1__UART3_CTS,
  82
  83         /* I2C */
  84         NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, MX53_GPIO_PAD_CTRL),
  85         NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, MX53_GPIO_PAD_CTRL),
  86
  87         /* SW controlled LED on STK5 baseboard */
  88         MX53_PAD_EIM_A18__GPIO2_20,
  89
  90         /* FEC */
  91         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  92         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  93         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  94
  95         /* FEC functions */
  96         MX53_PAD_FEC_MDC__FEC_MDC,
  97         MX53_PAD_FEC_MDIO__FEC_MDIO,
  98         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  99         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 100         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 101         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 102         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 103         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 104         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 105         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 106 };
 107
 108 static const struct gpio tx53_gpios[] = {
 109         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 110         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 111         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 112 };
 113
 114 /*
 115  * Functions
 116  */
 117 static u32 srsr;
 118 static u32 wrsr;
 119
 120 #define WRSR_POR        (1 << 4)
 121 #define WRSR_TOUT       (1 << 1)
 122 #define WRSR_SFTW       (1 << 0)
 123
 124 static void print_reset_cause(void)
 125 {
 126         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 127         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 128         char *dlm = "";
 129
 130         printf("Reset cause: ");
 131
 132         srsr = readl(&src_regs->srsr);
 133         wrsr = readw(wdt_base + 4);
 134
 135         if (wrsr & WRSR_POR) {
 136                 printf("%sPOR", dlm);
 137                 dlm = " | ";
 138         }
 139         if (srsr & 0x00004) {
 140                 printf("%sCSU", dlm);
 141                 dlm = " | ";
 142         }
 143         if (srsr & 0x00008) {
 144                 printf("%sIPP USER", dlm);
 145                 dlm = " | ";
 146         }
 147         if (srsr & 0x00010) {
 148                 if (wrsr & WRSR_SFTW) {
 149                         printf("%sSOFT", dlm);
 150                         dlm = " | ";
 151                 }
 152                 if (wrsr & WRSR_TOUT) {
 153                         printf("%sWDOG", dlm);
 154                         dlm = " | ";
 155                 }
 156         }
 157         if (srsr & 0x00020) {
 158                 printf("%sJTAG HIGH-Z", dlm);
 159                 dlm = " | ";
 160         }
 161         if (srsr & 0x00040) {
 162                 printf("%sJTAG SW", dlm);
 163                 dlm = " | ";
 164         }
 165         if (srsr & 0x10000) {
 166                 printf("%sWARM BOOT", dlm);
 167                 dlm = " | ";
 168         }
 169         if (dlm[0] == '\0')
 170                 printf("unknown");
 171
 172         printf("\n");
 173 }
 174
 175 static void print_cpuinfo(void)
 176 {
 177         u32 cpurev;
 178
 179         cpurev = get_cpu_rev();
 180
 181         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 182                 (cpurev & 0x000F0) >> 4,
 183                 (cpurev & 0x0000F) >> 0,
 184                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 185
 186         print_reset_cause();
 187 }
 188
 189 int board_early_init_f(void)
 190 {
 191         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 192         mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 193
 194         return 0;
 195 }
 196
 197 void coloured_LED_init(void)
 198 {
 199         /* Switch LED off */
 200         gpio_set_value(TX53_LED_GPIO, 0);
 201 }
 202
 203 int board_init(void)
 204 {
 205         /* Address of boot parameters */
 206         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 207         return 0;
 208 }
 209
 210 int dram_init(void)
 211 {
 212         int ret;
 213
 214         /* dram_init must store complete ramsize in gd->ram_size */
 215         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 216                                 PHYS_SDRAM_1_SIZE);
 217
 218         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 219                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 220         if (ret)
 221                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 222                         CONFIG_SYS_SDRAM_CLK, ret);
 223         else
 224                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 225                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 226                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 227                         CONFIG_SYS_SDRAM_CLK);
 228         return ret;
 229 }
 230
 231 void dram_init_banksize(void)
 232 {
 233         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 234         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 235                         PHYS_SDRAM_1_SIZE);
 236 #if CONFIG_NR_DRAM_BANKS > 1
 237         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 238         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 239                         PHYS_SDRAM_2_SIZE);
 240 #endif
 241 }
 242
 243 #ifdef  CONFIG_CMD_MMC
 244 int board_mmc_getcd(struct mmc *mmc)
 245 {
 246         struct fsl_esdhc_cfg *cfg = mmc->priv;
 247
 248         if (cfg->cd_gpio < 0)
 249                 return cfg->cd_gpio;
 250
 251         return !gpio_get_value(cfg->cd_gpio);
 252 }
 253
 254 static struct fsl_esdhc_cfg esdhc_cfg[] = {
 255         {
 256                 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 257                 .no_snoop = 1,
 258                 .cd_gpio = IMX_GPIO_NR(3, 24),
 259                 .wp_gpio = -EINVAL,
 260         },
 261         {
 262                 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 263                 .no_snoop = 1,
 264                 .cd_gpio = IMX_GPIO_NR(3, 25),
 265                 .wp_gpio = -EINVAL,
 266         },
 267 };
 268
 269 static const iomux_v3_cfg_t mmc0_pads[] = {
 270         NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, TX53_SDHC_PAD_CTRL),
 271         NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, TX53_SDHC_PAD_CTRL),
 272         NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, TX53_SDHC_PAD_CTRL),
 273         NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, TX53_SDHC_PAD_CTRL),
 274         NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, TX53_SDHC_PAD_CTRL),
 275         NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, TX53_SDHC_PAD_CTRL),
 276         /* SD1 CD */
 277         NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, MX53_GPIO_PAD_CTRL),
 278 };
 279
 280 static const iomux_v3_cfg_t mmc1_pads[] = {
 281         NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, TX53_SDHC_PAD_CTRL),
 282         NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, TX53_SDHC_PAD_CTRL),
 283         NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, TX53_SDHC_PAD_CTRL),
 284         NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, TX53_SDHC_PAD_CTRL),
 285         NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, TX53_SDHC_PAD_CTRL),
 286         NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, TX53_SDHC_PAD_CTRL),
 287         /* SD2 CD */
 288         NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, MX53_GPIO_PAD_CTRL),
 289 };
 290
 291 static struct {
 292         const iomux_v3_cfg_t *pads;
 293         int count;
 294 } mmc_pad_config[] = {
 295         { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
 296         { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
 297 };
 298
 299 int board_mmc_init(bd_t *bis)
 300 {
 301         int i;
 302
 303         for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
 304 //              struct mmc *mmc;
 305
 306                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 307                         break;
 308                 mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
 309                                                 mmc_pad_config[i].count);
 310                 fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
 311 #if 0
 312                 mmc = find_mmc_device(i);
 313                 if (mmc == NULL)
 314                         continue;
 315                 if (board_mmc_getcd(mmc) > 0)
 316                         mmc_init(mmc);
 317 #endif
 318         }
 319         return 0;
 320 }
 321 #endif /* CONFIG_CMD_MMC */
 322
 323 #ifdef CONFIG_FEC_MXC
 324
 325 #ifndef ETH_ALEN
 326 #define ETH_ALEN 6
 327 #endif
 328
 329 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 330 {
 331         int i;
 332         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 333         struct fuse_bank *bank = &iim->bank[1];
 334         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 335
 336         if (dev_id > 0)
 337                 return;
 338
 339         for (i = 0; i < ETH_ALEN; i++)
 340                 mac[i] = readl(&fuse->mac_addr[i]);
 341 }
 342
 343 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 344                         PAD_CTL_SRE_FAST)
 345 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 346 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 347
 348 int board_eth_init(bd_t *bis)
 349 {
 350         int ret;
 351         unsigned char mac[ETH_ALEN];
 352         char mac_str[ETH_ALEN * 3] = "";
 353
 354         /* delay at least 21ms for the PHY internal POR signal to deassert */
 355         udelay(22000);
 356         /* Deassert RESET to the external phy */
 357         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 358
 359         ret = cpu_eth_init(bis);
 360         if (ret) {
 361                 printf("cpu_eth_init() failed: %d\n", ret);
 362         }
 363
 364         imx_get_mac_from_fuse(0, mac);
 365         snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
 366                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 367         setenv("ethaddr", mac_str);
 368
 369         return ret;
 370 }
 371 #endif /* CONFIG_FEC_MXC */
 372
 373 enum {
 374         LED_STATE_INIT = -1,
 375         LED_STATE_OFF,
 376         LED_STATE_ON,
 377 };
 378
 379 void show_activity(int arg)
 380 {
 381         static int led_state = LED_STATE_INIT;
 382         static ulong last;
 383
 384         if (led_state == LED_STATE_INIT) {
 385                 last = get_timer(0);
 386                 gpio_set_value(TX53_LED_GPIO, 1);
 387                 led_state = LED_STATE_ON;
 388         } else {
 389                 if (get_timer(last) > CONFIG_SYS_HZ) {
 390                         last = get_timer(0);
 391                         if (led_state == LED_STATE_ON) {
 392                                 gpio_set_value(TX53_LED_GPIO, 0);
 393                         } else {
 394                                 gpio_set_value(TX53_LED_GPIO, 1);
 395                         }
 396                         led_state = 1 - led_state;
 397                 }
 398         }
 399 }
 400
 401 static const iomux_v3_cfg_t stk5_pads[] = {
 402         /* SW controlled LED on STK5 baseboard */
 403         MX53_PAD_EIM_A18__GPIO2_20,
 404
 405         /* I2C bus on DIMM pins 40/41 */
 406         NEW_PAD_CTRL(MX53_PAD_GPIO_6__I2C3_SDA, MX53_GPIO_PAD_CTRL),
 407         NEW_PAD_CTRL(MX53_PAD_GPIO_3__I2C3_SCL, MX53_GPIO_PAD_CTRL),
 408
 409         /* TSC200x PEN IRQ */
 410         NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, MX53_GPIO_PAD_CTRL),
 411
 412         /* EDT-FT5x06 Polytouch panel */
 413         NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, MX53_GPIO_PAD_CTRL), /* IRQ */
 414         NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, MX53_GPIO_PAD_CTRL), /* RESET */
 415         NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, MX53_GPIO_PAD_CTRL), /* WAKE */
 416
 417         /* USBH1 */
 418         NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, MX53_GPIO_PAD_CTRL), /* VBUSEN */
 419         NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, MX53_GPIO_PAD_CTRL), /* OC */
 420         /* USBOTG */
 421         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 422         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 423
 424         /* DS1339 Interrupt */
 425         NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, MX53_GPIO_PAD_CTRL),
 426 };
 427
 428 static const struct gpio stk5_gpios[] = {
 429         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 430
 431         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 432         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 433         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 434         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 435 };
 436
 437 #ifdef CONFIG_LCD
 438 static u16 tx53_cmap[256];
 439 vidinfo_t panel_info = {
 440         /* set to max. size supported by SoC */
 441         .vl_col = 1600,
 442         .vl_row = 1200,
 443
 444         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 445         .cmap = tx53_cmap,
 446 };
 447
 448 static struct fb_videomode tx53_fb_mode = {
 449         /* Standard VGA timing */
 450         .name           = "VGA",
 451         .refresh        = 60,
 452         .xres           = 640,
 453         .yres           = 480,
 454         .pixclock       = KHZ2PICOS(25175),
 455         .left_margin    = 48,
 456         .hsync_len      = 96,
 457         .right_margin   = 16,
 458         .upper_margin   = 31,
 459         .vsync_len      = 2,
 460         .lower_margin   = 12,
 461         .sync           = FB_SYNC_CLK_LAT_FALL,
 462         .vmode          = FB_VMODE_NONINTERLACED,
 463 };
 464
 465 void *lcd_base;                 /* Start of framebuffer memory  */
 466 void *lcd_console_address;      /* Start of console buffer      */
 467
 468 int lcd_line_length;
 469 int lcd_color_fg;
 470 int lcd_color_bg;
 471
 472 short console_col;
 473 short console_row;
 474
 475 void lcd_initcolregs(void)
 476 {
 477 }
 478
 479 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
 480 {
 481 }
 482
 483 void lcd_enable(void)
 484 {
 485         /* HACK ALERT:
 486          * global variable from common/lcd.c
 487          * Set to 0 here to prevent messages from going to LCD
 488          * rather than serial console
 489          */
 490         lcd_is_enabled = 0;
 491 }
 492
 493 void lcd_disable(void)
 494 {
 495 }
 496
 497 void lcd_panel_disable(void)
 498 {
 499 }
 500
 501 static int lcd_enabled = 1;
 502
 503 static inline int tx53_load_splashimage(void)
 504 {
 505         int ret = 0;
 506 #if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_LCD)
 507         int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]);
 508         cmd_tbl_t *cmd = find_cmd("nand");
 509         char *loadaddr = getenv("splashimage");
 510         char *argv[] = {
 511                 "nand",
 512                 "read",
 513                 loadaddr,
 514                 "logo",
 515         };
 516         const int argc = ARRAY_SIZE(argv);
 517         unsigned long la;
 518
 519         if (!loadaddr)
 520                 return 0;
 521
 522         if (tstc() || (wrsr & WRSR_TOUT))
 523                 return -ENODEV;
 524
 525         if (!cmd)
 526                 return -EINVAL;
 527
 528         la = simple_strtoul(loadaddr, NULL, 16);
 529         if (la == 0)
 530                 return -EINVAL;
 531
 532         /* clear BMP header in memory */
 533         memset((void *)la, 0, 64);
 534
 535         ret = do_nand(cmd, 0, argc, argv);
 536         if (ret) {
 537                 printf("Failed to load logo: %d\n", ret);
 538                 return ret;
 539         }
 540 #endif
 541         return ret;
 542 }
 543
 544 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 545         /* LCD RESET */
 546         NEW_PAD_CTRL(MX53_PAD_EIM_D29__GPIO3_29, MX53_GPIO_PAD_CTRL),
 547         /* LCD POWER_ENABLE */
 548         NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, MX53_GPIO_PAD_CTRL),
 549         /* LCD Backlight (PWM) */
 550         NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, MX53_GPIO_PAD_CTRL),
 551
 552         /* Display */
 553         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 554         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 555         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 556         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 557         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 558         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 559         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 560         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 561         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 562         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 563         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 564         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 565         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 566         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 567         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 568         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 569         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 570         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 571         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 572         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 573         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 574         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 575         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 576         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 577         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 578         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 579         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 580         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 581
 582         /* LVDS option */
 583         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 584         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 585         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 586         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 587         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 588         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 589         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 590         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 591         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 592         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 593 };
 594
 595 static const struct gpio stk5_lcd_gpios[] = {
 596         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 597         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 598         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 599 };
 600
 601 void lcd_ctrl_init(void *lcdbase)
 602 {
 603         int color_depth = 24;
 604         char *vm;
 605         unsigned long val;
 606         int refresh = 60;
 607         struct fb_videomode *p = &tx53_fb_mode;
 608         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 609         int pix_fmt = 0;
 610
 611         if (!lcd_enabled) {
 612                 printf("LCD disabled\n");
 613                 return;
 614         }
 615
 616         if (tstc() || (wrsr & WRSR_TOUT)) {
 617                 printf("%s@%d: Disabling LCD\n", __func__, __LINE__);
 618                 lcd_enabled = 0;
 619                 return;
 620         }
 621
 622         vm = getenv("video_mode");
 623         if (vm == NULL) {
 624                 printf("%s@%d: Disabling LCD\n", __func__, __LINE__);
 625                 lcd_enabled = 0;
 626                 return;
 627         }
 628         while (*vm != '\0') {
 629                 if (*vm >= '0' && *vm <= '9') {
 630                         char *end;
 631
 632                         val = simple_strtoul(vm, &end, 0);
 633                         if (end > vm) {
 634                                 if (!xres_set) {
 635                                         if (val > panel_info.vl_col)
 636                                                 val = panel_info.vl_col;
 637                                         p->xres = val;
 638                                         panel_info.vl_col = val;
 639                                         xres_set = 1;
 640                                 } else if (!yres_set) {
 641                                         if (val > panel_info.vl_row)
 642                                                 val = panel_info.vl_row;
 643                                         p->yres = val;
 644                                         panel_info.vl_row = val;
 645                                         yres_set = 1;
 646                                 } else if (!bpp_set) {
 647                                         switch (val) {
 648                                         case 24:
 649                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 650                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 651                                                 /* fallthru */
 652                                         case 16:
 653                                         case 8:
 654                                                 color_depth = val;
 655                                                 break;
 656
 657                                         case 18:
 658                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 659                                                         color_depth = val;
 660                                                         break;
 661                                                 }
 662                                                 /* fallthru */
 663                                         default:
 664                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 665                                                         end - vm, vm, color_depth);
 666                                         }
 667                                         bpp_set = 1;
 668                                 } else if (!refresh_set) {
 669                                         refresh = val;
 670                                         refresh_set = 1;
 671                                 }
 672                         }
 673                         vm = end;
 674                 }
 675                 switch (*vm) {
 676                 case '@':
 677                         bpp_set = 1;
 678                         /* fallthru */
 679                 case '-':
 680                         yres_set = 1;
 681                         /* fallthru */
 682                 case 'x':
 683                         xres_set = 1;
 684                         /* fallthru */
 685                 case 'M':
 686                 case 'R':
 687                         vm++;
 688                         break;
 689
 690                 default:
 691                         if (!pix_fmt) {
 692                                 char *tmp;
 693
 694                                 if (strncmp(vm, "LVDS", 4) == 0)
 695                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 696                                 else
 697                                         pix_fmt = IPU_PIX_FMT_RGB24;
 698                                 tmp = strchr(vm, ':');
 699                                 if (tmp)
 700                                         vm = tmp;
 701                         }
 702                         if (*vm != '\0')
 703                                 vm++;
 704                 }
 705         }
 706         switch (color_depth) {
 707         case 8:
 708                 panel_info.vl_bpix = 3;
 709                 break;
 710
 711         case 16:
 712                 panel_info.vl_bpix = 4;
 713                 break;
 714
 715         case 18:
 716         case 24:
 717                 panel_info.vl_bpix = 5;
 718         }
 719         lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col;
 720
 721         p->pixclock = KHZ2PICOS(refresh *
 722                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 723                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 724                 / 1000);
 725         debug("Pixel clock set to %lu.%03lu MHz\n",
 726                 PICOS2KHZ(p->pixclock) / 1000,
 727                 PICOS2KHZ(p->pixclock) % 1000);
 728
 729         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 730         mxc_iomux_v3_setup_multiple_pads(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
 731
 732         debug("Initializing FB driver\n");
 733         if (!pix_fmt)
 734                 pix_fmt = IPU_PIX_FMT_RGB24;
 735         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 736                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 737         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 738                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 739         }
 740         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 741                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 742                 /* enable LDB & DI0 clock */
 743                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
 744                         &ccm_regs->CCGR6);
 745         }
 746
 747         mx5_fb_init(p, 0, pix_fmt, 1 << panel_info.vl_bpix);
 748
 749         if (tx53_load_splashimage() == 0) {
 750                 debug("Initializing LCD controller\n");
 751                 video_hw_init();
 752         } else {
 753                 debug("Skipping initialization of LCD controller\n");
 754         }
 755 }
 756
 757 ulong calc_fbsize(void)
 758 {
 759         return panel_info.vl_row * panel_info.vl_col * 2 *
 760                 NBITS(panel_info.vl_bpix) / 8;
 761 }
 762 #else
 763 #define lcd_enabled 0
 764 #endif /* CONFIG_LCD */
 765
 766 static void stk5_board_init(void)
 767 {
 768         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 769         mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 770 }
 771
 772 static void stk5v3_board_init(void)
 773 {
 774         stk5_board_init();
 775 }
 776
 777 static void stk5v5_board_init(void)
 778 {
 779         stk5_board_init();
 780 }
 781
 782 static void tx53_move_fdt(void)
 783 {
 784         unsigned long fdt_addr = getenv_ulong("fdtcontroladdr", 16, 0);
 785         void *fdt = NULL;
 786
 787         if (!fdt_addr)
 788                 return;
 789
 790 #ifdef CONFIG_OF_EMBED
 791         fdt = _binary_dt_dtb_start;
 792 #elif defined CONFIG_OF_SEPARATE
 793         fdt = (void *)(_end_ofs + _TEXT_BASE);
 794 #endif
 795         if (!fdt)
 796                 return;
 797
 798         if (fdt_check_header(fdt)) {
 799                 printf("ERROR: No valid FDT found at %p\n", fdt);
 800                 return;
 801         }
 802         size_t fdt_len = fdt_totalsize(fdt);
 803
 804         memmove((void *)fdt_addr, fdt, fdt_len);
 805         set_working_fdt_addr((void *)fdt_addr);
 806 }
 807
 808 static void tx53_set_cpu_clock(void)
 809 {
 810         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 811         int ret;
 812
 813         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 814                 return;
 815
 816         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
 817         if (ret != 0) {
 818                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 819                 return;
 820         }
 821         printf("CPU clock set to %u.%03u MHz\n",
 822                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
 823                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
 824 }
 825
 826 int board_late_init(void)
 827 {
 828         const char *baseboard;
 829
 830         tx53_set_cpu_clock();
 831         tx53_move_fdt();
 832
 833         baseboard = getenv("baseboard");
 834         if (!baseboard)
 835                 return 0;
 836
 837         if (strncmp(baseboard, "stk5", 4) == 0) {
 838                 printf("Baseboard: %s\n", baseboard);
 839                 if ((strlen(baseboard) == 4) ||
 840                         strcmp(baseboard, "stk5-v3") == 0) {
 841                         stk5v3_board_init();
 842                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 843                         stk5v5_board_init();
 844                 } else {
 845                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 846                                 baseboard + 4);
 847                 }
 848         } else {
 849                 printf("WARNING: Unsupported baseboard: '%s'\n",
 850                         baseboard);
 851                 return -EINVAL;
 852         }
 853         if (lcd_enabled) {
 854                 printf("Switching LCD on\n");
 855                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 856                 udelay(100);
 857                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 858                 udelay(300000);
 859                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
 860         }
 861
 862         return 0;
 863 }
 864
 865 int checkboard(void)
 866 {
 867         print_cpuinfo();
 868
 869         printf("Board: Ka-Ro TX53-xx3%s\n",
 870                 TX53_MOD_SUFFIX);
 871
 872         return 0;
 873 }
 874
 875 #if defined(CONFIG_OF_BOARD_SETUP)
 876 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 877 #include <jffs2/jffs2.h>
 878 #include <mtd_node.h>
 879 struct node_info nodes[] = {
 880         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
 881 };
 882
 883 #else
 884 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 885 #endif
 886
 887 static const char *tx53_touchpanels[] = {
 888         "ti,tsc2007",
 889         "edt,edt-ft5x06",
 890 };
 891
 892 static void fdt_del_node_by_name(void *blob, const char *name)
 893 {
 894         int offs = fdt_node_offset_by_compatible(blob, -1, name);
 895
 896         if (offs < 0) {
 897                 debug("node '%s' not found: %d\n", name, offs);
 898                 return;
 899         }
 900         debug("Removing node '%s' from DT\n", name);
 901         fdt_del_node(blob, offs);
 902 }
 903
 904 static void tx53_fixup_touchpanel(void *blob)
 905 {
 906         int i;
 907         const char *model = getenv("touchpanel");
 908
 909         for (i = 0; i < ARRAY_SIZE(tx53_touchpanels); i++) {
 910                 const char *tp = tx53_touchpanels[i];
 911
 912                 if (model != NULL && strcmp(model, tp) == 0)
 913                         continue;
 914
 915                 tp = strchr(tp, ',');
 916                 if (tp != NULL && *tp != '\0' && strcmp(model, tp + 1) == 0)
 917                         continue;
 918
 919                 fdt_del_node_by_name(blob, tx53_touchpanels[i]);
 920         }
 921 }
 922
 923 static void tx53_fixup_usb_otg(void *blob)
 924 {
 925         const char *otg_mode = getenv("otg_mode");
 926         int usbphy = 2;
 927
 928         if (otg_mode == NULL || strcmp(otg_mode, "host") != 0) {
 929                 debug("Removing node %s from DT\n", "usbh1");
 930                 fdt_del_node_and_alias(blob, "usbh1");
 931                 usbphy--;
 932         }
 933         if (otg_mode == NULL || strcmp(otg_mode, "device") != 0) {
 934                 debug("Removing node %s from DT\n", "usbotg");
 935                 fdt_del_node_and_alias(blob, "usbotg");
 936                 usbphy--;
 937         }
 938         if (!usbphy) {
 939                 debug("Removing node %s from DT\n", "usbphy");
 940                 fdt_del_node_and_alias(blob, "usbphy");
 941         }
 942 }
 943
 944 void ft_board_setup(void *blob, bd_t *bd)
 945 {
 946         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 947         fdt_fixup_ethernet(blob);
 948
 949         tx53_fixup_touchpanel(blob);
 950         tx53_fixup_usb_otg(blob);
 951 }
 952 #endif