board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <i2c.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mxcfb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx53.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 #include "../common/karo.h"
  41
  42 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  43 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  44 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  45 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  46
  47 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  48 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  50
  51 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  56                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  57
  58 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  59                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  60
  61 static iomux_v3_cfg_t tx53_pads[] = {
  62         /* NAND flash pads are set up in lowlevel_init.S */
  63
  64         /* UART pads */
  65 #if CONFIG_MXC_UART_BASE == UART1_BASE
  66         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  67         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  68         MX53_PAD_PATA_IORDY__UART1_RTS,
  69         MX53_PAD_PATA_RESET_B__UART1_CTS,
  70 #endif
  71 #if CONFIG_MXC_UART_BASE == UART2_BASE
  72         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  73         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  74         MX53_PAD_PATA_DIOR__UART2_RTS,
  75         MX53_PAD_PATA_INTRQ__UART2_CTS,
  76 #endif
  77 #if CONFIG_MXC_UART_BASE == UART3_BASE
  78         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  79         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  80         MX53_PAD_PATA_DA_2__UART3_RTS,
  81         MX53_PAD_PATA_DA_1__UART3_CTS,
  82 #endif
  83         /* internal I2C */
  84         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  85         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  86
  87         /* FEC PHY GPIO functions */
  88         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  89         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  90         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  91
  92         /* FEC functions */
  93         MX53_PAD_FEC_MDC__FEC_MDC,
  94         MX53_PAD_FEC_MDIO__FEC_MDIO,
  95         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  96         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  97         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  98         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  99         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 100         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 101         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 102         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 103 };
 104
 105 static const struct gpio tx53_gpios[] = {
 106         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 107         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 108         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 109         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 110 };
 111
 112 /*
 113  * Functions
 114  */
 115 /* placed in section '.data' to prevent overwriting relocation info
 116  * overlayed with bss
 117  */
 118 static u32 wrsr __attribute__((section(".data")));
 119
 120 #define WRSR_POR        (1 << 4)
 121 #define WRSR_TOUT       (1 << 1)
 122 #define WRSR_SFTW       (1 << 0)
 123
 124 static void print_reset_cause(void)
 125 {
 126         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 127         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 128         u32 srsr;
 129         char *dlm = "";
 130
 131         printf("Reset cause: ");
 132
 133         srsr = readl(&src_regs->srsr);
 134         wrsr = readw(wdt_base + 4);
 135
 136         if (wrsr & WRSR_POR) {
 137                 printf("%sPOR", dlm);
 138                 dlm = " | ";
 139         }
 140         if (srsr & 0x00004) {
 141                 printf("%sCSU", dlm);
 142                 dlm = " | ";
 143         }
 144         if (srsr & 0x00008) {
 145                 printf("%sIPP USER", dlm);
 146                 dlm = " | ";
 147         }
 148         if (srsr & 0x00010) {
 149                 if (wrsr & WRSR_SFTW) {
 150                         printf("%sSOFT", dlm);
 151                         dlm = " | ";
 152                 }
 153                 if (wrsr & WRSR_TOUT) {
 154                         printf("%sWDOG", dlm);
 155                         dlm = " | ";
 156                 }
 157         }
 158         if (srsr & 0x00020) {
 159                 printf("%sJTAG HIGH-Z", dlm);
 160                 dlm = " | ";
 161         }
 162         if (srsr & 0x00040) {
 163                 printf("%sJTAG SW", dlm);
 164                 dlm = " | ";
 165         }
 166         if (srsr & 0x10000) {
 167                 printf("%sWARM BOOT", dlm);
 168                 dlm = " | ";
 169         }
 170         if (dlm[0] == '\0')
 171                 printf("unknown");
 172
 173         printf("\n");
 174 }
 175
 176 static void tx53_print_cpuinfo(void)
 177 {
 178         u32 cpurev;
 179
 180         cpurev = get_cpu_rev();
 181
 182         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 183                 (cpurev & 0x000F0) >> 4,
 184                 (cpurev & 0x0000F) >> 0,
 185                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 186
 187         print_reset_cause();
 188 }
 189
 190 enum LTC3589_REGS {
 191         LTC3589_SCR1 = 0x07,
 192         LTC3589_SCR2 = 0x12,
 193         LTC3589_VCCR = 0x20,
 194         LTC3589_CLIRQ = 0x21,
 195         LTC3589_B1DTV1 = 0x23,
 196         LTC3589_B1DTV2 = 0x24,
 197         LTC3589_VRRCR = 0x25,
 198         LTC3589_B2DTV1 = 0x26,
 199         LTC3589_B2DTV2 = 0x27,
 200         LTC3589_B3DTV1 = 0x29,
 201         LTC3589_B3DTV2 = 0x2a,
 202         LTC3589_L2DTV1 = 0x32,
 203         LTC3589_L2DTV2 = 0x33,
 204 };
 205
 206 #define LTC3589_BnDTV1_PGOOD_MASK       (1 << 5)
 207 #define LTC3589_BnDTV1_SLEW(n)          (((n) & 3) << 6)
 208
 209 #define LTC3589_CLK_RATE_LOW            (1 << 5)
 210
 211 #define LTC3589_SCR2_PGOOD_SHUTDWN      (1 << 7)
 212
 213 #define VDD_LDO2_VAL            mV_to_regval(vout_to_vref(1325 * 10, 2))
 214 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1100 * 10, 3))
 215 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1325 * 10, 4))
 216 #define VDD_BUCK3_VAL           mV_to_regval(vout_to_vref(2500 * 10, 5))
 217
 218 #ifndef CONFIG_SYS_TX53_HWREV_2
 219 /* LDO2 vref divider */
 220 #define R1_2    180
 221 #define R2_2    191
 222 /* BUCK1 vref divider */
 223 #define R1_3    150
 224 #define R2_3    180
 225 /* BUCK2 vref divider */
 226 #define R1_4    180
 227 #define R2_4    191
 228 /* BUCK3 vref divider */
 229 #define R1_5    270
 230 #define R2_5    100
 231 #else
 232 /* no dividers on vref */
 233 #define R1_2    0
 234 #define R2_2    1
 235 #define R1_3    0
 236 #define R2_3    1
 237 #define R1_4    0
 238 #define R2_4    1
 239 #define R1_5    0
 240 #define R2_5    1
 241 #endif
 242
 243 /* calculate voltages in 10mV */
 244 #define R1(idx)                 R1_##idx
 245 #define R2(idx)                 R2_##idx
 246
 247 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
 248 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
 249
 250 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
 251 #define regval_to_mV(v)         (((v) * 125 + 3625))
 252
 253 static struct pmic_regs {
 254         enum LTC3589_REGS addr;
 255         u8 val;
 256 } ltc3589_regs[] = {
 257         { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
 258         { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
 259
 260         { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 261         { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
 262
 263         { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 264         { LTC3589_B1DTV2, VDD_CORE_VAL, },
 265
 266         { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 267         { LTC3589_B2DTV2, VDD_SOC_VAL, },
 268
 269         { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 270         { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
 271
 272         /* Select ref 0 for all regulators and enable slew */
 273         { LTC3589_VCCR, 0x55, },
 274
 275         { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
 276 };
 277
 278 static int setup_pmic_voltages(void)
 279 {
 280         int ret;
 281         unsigned char value;
 282         int i;
 283
 284         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 285         if (ret != 0) {
 286                 printf("Failed to initialize I2C\n");
 287                 return ret;
 288         }
 289
 290         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 291         if (ret) {
 292                 printf("%s: i2c_read error: %d\n", __func__, ret);
 293                 return ret;
 294         }
 295
 296         for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
 297                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 298                                 &value, 1);
 299                 debug("Writing %02x to reg %02x (%02x)\n",
 300                         ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
 301                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 302                                 &ltc3589_regs[i].val, 1);
 303                 if (ret) {
 304                         printf("%s: failed to write PMIC register %02x: %d\n",
 305                                 __func__, ltc3589_regs[i].addr, ret);
 306                         return ret;
 307                 }
 308         }
 309         printf("VDDCORE set to %umV\n",
 310                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
 311
 312         printf("VDDSOC  set to %umV\n",
 313                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
 314         return 0;
 315 }
 316
 317 static struct {
 318         u32 max_freq;
 319         u32 mV;
 320 } tx53_core_voltages[] = {
 321         { 800000000, 1100, },
 322         { 1000000000, 1240, },
 323         { 1200000000, 1350, },
 324 };
 325
 326 int adjust_core_voltage(u32 freq)
 327 {
 328         int ret;
 329         int i;
 330
 331         printf("%s@%d\n", __func__, __LINE__);
 332
 333         for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
 334                 if (freq <= tx53_core_voltages[i].max_freq) {
 335                         int retries = 0;
 336                         const int max_tries = 10;
 337                         const int delay_us = 1;
 338                         u32 mV = tx53_core_voltages[i].mV;
 339                         u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
 340                         u8 v;
 341
 342                         printf("regval[%umV]=%02x\n", mV, val);
 343
 344                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
 345                                 &v, 1);
 346                         if (ret) {
 347                                 printf("%s: failed to read PMIC register %02x: %d\n",
 348                                         __func__, LTC3589_B1DTV1, ret);
 349                                 return ret;
 350                         }
 351                         printf("Changing reg %02x from %02x to %02x\n",
 352                                 LTC3589_B1DTV1, v, (v & ~0x1f) |
 353                                 mV_to_regval(vout_to_vref(mV * 10, 3)));
 354                         v &= ~0x1f;
 355                         v |= mV_to_regval(vout_to_vref(mV * 10, 3));
 356                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
 357                                         &v, 1);
 358                         if (ret) {
 359                                 printf("%s: failed to write PMIC register %02x: %d\n",
 360                                         __func__, LTC3589_B1DTV1, ret);
 361                                 return ret;
 362                         }
 363                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
 364                                         &v, 1);
 365                         if (ret) {
 366                                 printf("%s: failed to read PMIC register %02x: %d\n",
 367                                         __func__, LTC3589_VCCR, ret);
 368                                 return ret;
 369                         }
 370                         v |= 0x1;
 371                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
 372                                         &v, 1);
 373                         if (ret) {
 374                                 printf("%s: failed to write PMIC register %02x: %d\n",
 375                                         __func__, LTC3589_VCCR, ret);
 376                                 return ret;
 377                         }
 378                         for (retries = 0; retries < max_tries; retries++) {
 379                                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
 380                                         LTC3589_VCCR, 1, &v, 1);
 381                                 if (ret) {
 382                                         printf("%s: failed to read PMIC register %02x: %d\n",
 383                                                 __func__, LTC3589_VCCR, ret);
 384                                         return ret;
 385                                 }
 386                                 if (!(v & 1))
 387                                         break;
 388                                 udelay(delay_us);
 389                         }
 390                         if (v & 1) {
 391                                 printf("change of VDDCORE did not complete after %uµs\n",
 392                                         retries * delay_us);
 393                                 return -ETIMEDOUT;
 394                         }
 395
 396                         printf("VDDCORE set to %umV after %u loops\n",
 397                                 DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
 398                                         10), retries);
 399                         return 0;
 400                 }
 401         }
 402         return -EINVAL;
 403 }
 404
 405 int board_early_init_f(void)
 406 {
 407         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 408
 409         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 410         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 411
 412         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 413         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 414
 415         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 416         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 417         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 418         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 419         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 420
 421         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 422         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 423
 424         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 425         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 426         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 427         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 428         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 429
 430         writel(0xffcf0fff, &ccm_regs->CCGR0);
 431         writel(0x000fffcf, &ccm_regs->CCGR1);
 432         writel(0x033c0000, &ccm_regs->CCGR2);
 433         writel(0x000000ff, &ccm_regs->CCGR3);
 434         writel(0x00000000, &ccm_regs->CCGR4);
 435         writel(0x00fff033, &ccm_regs->CCGR5);
 436         writel(0x0f00030f, &ccm_regs->CCGR6);
 437         writel(0xfff00000, &ccm_regs->CCGR7);
 438         writel(0x00000000, &ccm_regs->cmeor);
 439
 440         return 0;
 441 }
 442
 443 int board_init(void)
 444 {
 445         int ret;
 446
 447         /* Address of boot parameters */
 448         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 449
 450         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 451                 printf("CTRL-C detected; Skipping PMIC setup\n");
 452                 return 1;
 453         }
 454
 455         ret = setup_pmic_voltages();
 456         if (ret) {
 457                 printf("Failed to setup PMIC voltages\n");
 458                 hang();
 459         }
 460         return 0;
 461 }
 462
 463 int dram_init(void)
 464 {
 465         int ret;
 466
 467         /* dram_init must store complete ramsize in gd->ram_size */
 468         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 469                                 PHYS_SDRAM_1_SIZE);
 470
 471         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 472                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 473         if (ret)
 474                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 475                         CONFIG_SYS_SDRAM_CLK, ret);
 476         else
 477                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 478                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 479                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 480                         CONFIG_SYS_SDRAM_CLK);
 481         return ret;
 482 }
 483
 484 void dram_init_banksize(void)
 485 {
 486         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 487         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 488                         PHYS_SDRAM_1_SIZE);
 489 #if CONFIG_NR_DRAM_BANKS > 1
 490         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 491         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 492                         PHYS_SDRAM_2_SIZE);
 493 #endif
 494 }
 495
 496 #ifdef  CONFIG_CMD_MMC
 497 static const iomux_v3_cfg_t mmc0_pads[] = {
 498         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 499         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 500         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 501         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 502         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 503         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 504         /* SD1 CD */
 505         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 506 };
 507
 508 static const iomux_v3_cfg_t mmc1_pads[] = {
 509         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 510         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 511         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 512         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 513         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 514         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 515         /* SD2 CD */
 516         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 517 };
 518
 519 static struct tx53_esdhc_cfg {
 520         const iomux_v3_cfg_t *pads;
 521         int num_pads;
 522         struct fsl_esdhc_cfg cfg;
 523         int cd_gpio;
 524 } tx53_esdhc_cfg[] = {
 525         {
 526                 .pads = mmc0_pads,
 527                 .num_pads = ARRAY_SIZE(mmc0_pads),
 528                 .cfg = {
 529                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 530                         .max_bus_width = 4,
 531                 },
 532                 .cd_gpio = IMX_GPIO_NR(3, 24),
 533         },
 534         {
 535                 .pads = mmc1_pads,
 536                 .num_pads = ARRAY_SIZE(mmc1_pads),
 537                 .cfg = {
 538                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 539                         .max_bus_width = 4,
 540                 },
 541                 .cd_gpio = IMX_GPIO_NR(3, 25),
 542         },
 543 };
 544
 545 static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 546 {
 547         return container_of(cfg, struct tx53_esdhc_cfg, cfg);
 548 }
 549
 550 int board_mmc_getcd(struct mmc *mmc)
 551 {
 552         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
 553
 554         if (cfg->cd_gpio < 0)
 555                 return cfg->cd_gpio;
 556
 557         debug("SD card %d is %spresent\n",
 558                 cfg - tx53_esdhc_cfg,
 559                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 560         return !gpio_get_value(cfg->cd_gpio);
 561 }
 562
 563 int board_mmc_init(bd_t *bis)
 564 {
 565         int i;
 566
 567         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
 568                 struct mmc *mmc;
 569                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
 570                 int ret;
 571
 572                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 573                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 574
 575                 ret = gpio_request_one(cfg->cd_gpio,
 576                                 GPIOF_INPUT, "MMC CD");
 577                 if (ret) {
 578                         printf("Error %d requesting GPIO%d_%d\n",
 579                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 580                         continue;
 581                 }
 582
 583                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 584                 fsl_esdhc_initialize(bis, &cfg->cfg);
 585
 586                 mmc = find_mmc_device(i);
 587                 if (mmc == NULL)
 588                         continue;
 589                 if (board_mmc_getcd(mmc) > 0)
 590                         mmc_init(mmc);
 591         }
 592         return 0;
 593 }
 594 #endif /* CONFIG_CMD_MMC */
 595
 596 #ifdef CONFIG_FEC_MXC
 597
 598 #ifndef ETH_ALEN
 599 #define ETH_ALEN 6
 600 #endif
 601
 602 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 603 {
 604         int i;
 605         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 606         struct fuse_bank *bank = &iim->bank[1];
 607         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 608
 609         if (dev_id > 0)
 610                 return;
 611
 612         for (i = 0; i < ETH_ALEN; i++)
 613                 mac[i] = readl(&fuse->mac_addr[i]);
 614 }
 615
 616 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 617                         PAD_CTL_SRE_FAST)
 618 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 619 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 620
 621 int board_eth_init(bd_t *bis)
 622 {
 623         int ret;
 624
 625         /* delay at least 21ms for the PHY internal POR signal to deassert */
 626         udelay(22000);
 627
 628         /* Deassert RESET to the external phy */
 629         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 630
 631         ret = cpu_eth_init(bis);
 632         if (ret)
 633                 printf("cpu_eth_init() failed: %d\n", ret);
 634
 635         return ret;
 636 }
 637 #endif /* CONFIG_FEC_MXC */
 638
 639 enum {
 640         LED_STATE_INIT = -1,
 641         LED_STATE_OFF,
 642         LED_STATE_ON,
 643 };
 644
 645 void show_activity(int arg)
 646 {
 647         static int led_state = LED_STATE_INIT;
 648         static ulong last;
 649
 650         if (led_state == LED_STATE_INIT) {
 651                 last = get_timer(0);
 652                 gpio_set_value(TX53_LED_GPIO, 1);
 653                 led_state = LED_STATE_ON;
 654         } else {
 655                 if (get_timer(last) > CONFIG_SYS_HZ) {
 656                         last = get_timer(0);
 657                         if (led_state == LED_STATE_ON) {
 658                                 gpio_set_value(TX53_LED_GPIO, 0);
 659                         } else {
 660                                 gpio_set_value(TX53_LED_GPIO, 1);
 661                         }
 662                         led_state = 1 - led_state;
 663                 }
 664         }
 665 }
 666
 667 static const iomux_v3_cfg_t stk5_pads[] = {
 668         /* SW controlled LED on STK5 baseboard */
 669         MX53_PAD_EIM_A18__GPIO2_20,
 670
 671         /* I2C bus on DIMM pins 40/41 */
 672         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 673         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 674
 675         /* TSC200x PEN IRQ */
 676         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 677
 678         /* EDT-FT5x06 Polytouch panel */
 679         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 680         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 681         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 682
 683         /* USBH1 */
 684         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 685         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 686         /* USBOTG */
 687         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 688         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 689
 690         /* DS1339 Interrupt */
 691         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 692 };
 693
 694 static const struct gpio stk5_gpios[] = {
 695         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 696
 697         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 698         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 699         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 700         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 701 };
 702
 703 #ifdef CONFIG_LCD
 704 static u16 tx53_cmap[256];
 705 vidinfo_t panel_info = {
 706         /* set to max. size supported by SoC */
 707         .vl_col = 1600,
 708         .vl_row = 1200,
 709
 710         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 711         .cmap = tx53_cmap,
 712 };
 713
 714 static struct fb_videomode tx53_fb_modes[] = {
 715 #ifndef CONFIG_SYS_LVDS_IF
 716         {
 717                 /* Standard VGA timing */
 718                 .name           = "VGA",
 719                 .refresh        = 60,
 720                 .xres           = 640,
 721                 .yres           = 480,
 722                 .pixclock       = KHZ2PICOS(25175),
 723                 .left_margin    = 48,
 724                 .hsync_len      = 96,
 725                 .right_margin   = 16,
 726                 .upper_margin   = 31,
 727                 .vsync_len      = 2,
 728                 .lower_margin   = 12,
 729                 .sync           = FB_SYNC_CLK_LAT_FALL,
 730         },
 731         {
 732                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 733                  * DE high active, 115.2 mm x 86.4 mm display area
 734                  * VGA compatible timing
 735                  */
 736                 .name           = "ETV570",
 737                 .refresh        = 60,
 738                 .xres           = 640,
 739                 .yres           = 480,
 740                 .pixclock       = KHZ2PICOS(25175),
 741                 .left_margin    = 114,
 742                 .hsync_len      = 30,
 743                 .right_margin   = 16,
 744                 .upper_margin   = 32,
 745                 .vsync_len      = 3,
 746                 .lower_margin   = 10,
 747                 .sync           = FB_SYNC_CLK_LAT_FALL,
 748         },
 749         {
 750                 /* Emerging ET0350G0DH6 320 x 240 display.
 751                  * 70.08 mm x 52.56 mm display area.
 752                  */
 753                 .name           = "ET0350",
 754                 .refresh        = 60,
 755                 .xres           = 320,
 756                 .yres           = 240,
 757                 .pixclock       = KHZ2PICOS(6500),
 758                 .left_margin    = 68 - 34,
 759                 .hsync_len      = 34,
 760                 .right_margin   = 20,
 761                 .upper_margin   = 18 - 3,
 762                 .vsync_len      = 3,
 763                 .lower_margin   = 4,
 764                 .sync           = FB_SYNC_CLK_LAT_FALL,
 765         },
 766         {
 767                 /* Emerging ET0430G0DH6 480 x 272 display.
 768                  * 95.04 mm x 53.856 mm display area.
 769                  */
 770                 .name           = "ET0430",
 771                 .refresh        = 60,
 772                 .xres           = 480,
 773                 .yres           = 272,
 774                 .pixclock       = KHZ2PICOS(9000),
 775                 .left_margin    = 2,
 776                 .hsync_len      = 41,
 777                 .right_margin   = 2,
 778                 .upper_margin   = 2,
 779                 .vsync_len      = 10,
 780                 .lower_margin   = 2,
 781                 .sync           = FB_SYNC_CLK_LAT_FALL,
 782         },
 783         {
 784                 /* Emerging ET0500G0DH6 800 x 480 display.
 785                  * 109.6 mm x 66.4 mm display area.
 786                  */
 787                 .name           = "ET0500",
 788                 .refresh        = 60,
 789                 .xres           = 800,
 790                 .yres           = 480,
 791                 .pixclock       = KHZ2PICOS(33260),
 792                 .left_margin    = 216 - 128,
 793                 .hsync_len      = 128,
 794                 .right_margin   = 1056 - 800 - 216,
 795                 .upper_margin   = 35 - 2,
 796                 .vsync_len      = 2,
 797                 .lower_margin   = 525 - 480 - 35,
 798                 .sync           = FB_SYNC_CLK_LAT_FALL,
 799         },
 800         {
 801                 /* Emerging ETQ570G0DH6 320 x 240 display.
 802                  * 115.2 mm x 86.4 mm display area.
 803                  */
 804                 .name           = "ETQ570",
 805                 .refresh        = 60,
 806                 .xres           = 320,
 807                 .yres           = 240,
 808                 .pixclock       = KHZ2PICOS(6400),
 809                 .left_margin    = 38,
 810                 .hsync_len      = 30,
 811                 .right_margin   = 30,
 812                 .upper_margin   = 16, /* 15 according to datasheet */
 813                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 814                 .lower_margin   = 4, /* 4.5 according to datasheet */
 815                 .sync           = FB_SYNC_CLK_LAT_FALL,
 816         },
 817         {
 818                 /* Emerging ET0700G0DH6 800 x 480 display.
 819                  * 152.4 mm x 91.44 mm display area.
 820                  */
 821                 .name           = "ET0700",
 822                 .refresh        = 60,
 823                 .xres           = 800,
 824                 .yres           = 480,
 825                 .pixclock       = KHZ2PICOS(33260),
 826                 .left_margin    = 216 - 128,
 827                 .hsync_len      = 128,
 828                 .right_margin   = 1056 - 800 - 216,
 829                 .upper_margin   = 35 - 2,
 830                 .vsync_len      = 2,
 831                 .lower_margin   = 525 - 480 - 35,
 832                 .sync           = FB_SYNC_CLK_LAT_FALL,
 833         },
 834 #else
 835         {
 836                 /* HannStar HSD100PXN1
 837                  * 202.7m mm x 152.06 mm display area.
 838                  */
 839                 .name           = "HSD100PXN1",
 840                 .refresh        = 60,
 841                 .xres           = 1024,
 842                 .yres           = 768,
 843                 .pixclock       = KHZ2PICOS(65000),
 844                 .left_margin    = 0,
 845                 .hsync_len      = 0,
 846                 .right_margin   = 320,
 847                 .upper_margin   = 0,
 848                 .vsync_len      = 0,
 849                 .lower_margin   = 38,
 850                 .sync           = FB_SYNC_CLK_LAT_FALL,
 851         },
 852 #endif
 853         {
 854                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 855                 .refresh        = 60,
 856                 .left_margin    = 48,
 857                 .hsync_len      = 96,
 858                 .right_margin   = 16,
 859                 .upper_margin   = 31,
 860                 .vsync_len      = 2,
 861                 .lower_margin   = 12,
 862                 .sync           = FB_SYNC_CLK_LAT_FALL,
 863         },
 864 };
 865
 866 static int lcd_enabled = 1;
 867 static int lcd_bl_polarity;
 868
 869 static int lcd_backlight_polarity(void)
 870 {
 871         return lcd_bl_polarity;
 872 }
 873
 874 void lcd_enable(void)
 875 {
 876         /* HACK ALERT:
 877          * global variable from common/lcd.c
 878          * Set to 0 here to prevent messages from going to LCD
 879          * rather than serial console
 880          */
 881         lcd_is_enabled = 0;
 882
 883         if (lcd_enabled) {
 884                 karo_load_splashimage(1);
 885
 886                 debug("Switching LCD on\n");
 887                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 888                 udelay(100);
 889                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 890                 udelay(300000);
 891                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
 892                         lcd_backlight_polarity());
 893         }
 894 }
 895
 896 void lcd_disable(void)
 897 {
 898         if (lcd_enabled) {
 899                 printf("Disabling LCD\n");
 900                 ipuv3_fb_shutdown();
 901         }
 902 }
 903
 904 void lcd_panel_disable(void)
 905 {
 906         if (lcd_enabled) {
 907                 debug("Switching LCD off\n");
 908                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
 909                         !lcd_backlight_polarity());
 910                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 911                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 912         }
 913 }
 914
 915 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 916         /* LCD RESET */
 917         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 918         /* LCD POWER_ENABLE */
 919         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 920         /* LCD Backlight (PWM) */
 921         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 922
 923         /* Display */
 924 #ifndef CONFIG_SYS_LVDS_IF
 925         /* LCD option */
 926         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 927         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 928         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 929         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 930         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 931         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 932         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 933         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 934         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 935         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 936         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 937         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 938         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 939         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 940         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 941         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 942         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 943         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 944         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 945         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 946         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 947         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 948         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 949         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 950         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 951         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 952         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 953         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 954 #else
 955         /* LVDS option */
 956         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 957         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 958         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 959         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 960         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 961         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 962         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 963         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 964         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 965         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 966 #endif
 967 };
 968
 969 static const struct gpio stk5_lcd_gpios[] = {
 970         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 971         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 972         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 973 };
 974
 975 void lcd_ctrl_init(void *lcdbase)
 976 {
 977         int color_depth = 24;
 978         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 979         const char *vm;
 980         unsigned long val;
 981         int refresh = 60;
 982         struct fb_videomode *p = &tx53_fb_modes[0];
 983         struct fb_videomode fb_mode;
 984         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 985         int pix_fmt;
 986         int lcd_bus_width;
 987         ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
 988         unsigned long di_clk_rate = 65000000;
 989
 990         if (!lcd_enabled) {
 991                 debug("LCD disabled\n");
 992                 return;
 993         }
 994
 995         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 996                 debug("Disabling LCD\n");
 997                 lcd_enabled = 0;
 998                 setenv("splashimage", NULL);
 999                 return;
1000         }
1001
1002         karo_fdt_move_fdt();
1003         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1004
1005         if (video_mode == NULL) {
1006                 debug("Disabling LCD\n");
1007                 lcd_enabled = 0;
1008                 return;
1009         }
1010         vm = video_mode;
1011         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1012                 p = &fb_mode;
1013                 debug("Using video mode from FDT\n");
1014                 vm += strlen(vm);
1015                 if (fb_mode.xres > panel_info.vl_col ||
1016                         fb_mode.yres > panel_info.vl_row) {
1017                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1018                                 fb_mode.xres, fb_mode.yres,
1019                                 panel_info.vl_col, panel_info.vl_row);
1020                         lcd_enabled = 0;
1021                         return;
1022                 }
1023         }
1024         if (p->name != NULL)
1025                 debug("Trying compiled-in video modes\n");
1026         while (p->name != NULL) {
1027                 if (strcmp(p->name, vm) == 0) {
1028                         debug("Using video mode: '%s'\n", p->name);
1029                         vm += strlen(vm);
1030                         break;
1031                 }
1032                 p++;
1033         }
1034         if (*vm != '\0')
1035                 debug("Trying to decode video_mode: '%s'\n", vm);
1036         while (*vm != '\0') {
1037                 if (*vm >= '0' && *vm <= '9') {
1038                         char *end;
1039
1040                         val = simple_strtoul(vm, &end, 0);
1041                         if (end > vm) {
1042                                 if (!xres_set) {
1043                                         if (val > panel_info.vl_col)
1044                                                 val = panel_info.vl_col;
1045                                         p->xres = val;
1046                                         panel_info.vl_col = val;
1047                                         xres_set = 1;
1048                                 } else if (!yres_set) {
1049                                         if (val > panel_info.vl_row)
1050                                                 val = panel_info.vl_row;
1051                                         p->yres = val;
1052                                         panel_info.vl_row = val;
1053                                         yres_set = 1;
1054                                 } else if (!bpp_set) {
1055                                         switch (val) {
1056                                         case 32:
1057                                         case 24:
1058                                                 if (is_lvds())
1059                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1060                                                 /* fallthru */
1061                                         case 16:
1062                                         case 8:
1063                                                 color_depth = val;
1064                                                 break;
1065
1066                                         case 18:
1067                                                 if (is_lvds()) {
1068                                                         color_depth = val;
1069                                                         break;
1070                                                 }
1071                                                 /* fallthru */
1072                                         default:
1073                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1074                                                         end - vm, vm, color_depth);
1075                                         }
1076                                         bpp_set = 1;
1077                                 } else if (!refresh_set) {
1078                                         refresh = val;
1079                                         refresh_set = 1;
1080                                 }
1081                         }
1082                         vm = end;
1083                 }
1084                 switch (*vm) {
1085                 case '@':
1086                         bpp_set = 1;
1087                         /* fallthru */
1088                 case '-':
1089                         yres_set = 1;
1090                         /* fallthru */
1091                 case 'x':
1092                         xres_set = 1;
1093                         /* fallthru */
1094                 case 'M':
1095                 case 'R':
1096                         vm++;
1097                         break;
1098
1099                 default:
1100                         if (*vm != '\0')
1101                                 vm++;
1102                 }
1103         }
1104         if (p->xres == 0 || p->yres == 0) {
1105                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1106                 lcd_enabled = 0;
1107                 printf("Supported video modes are:");
1108                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
1109                         printf(" %s", p->name);
1110                 }
1111                 printf("\n");
1112                 return;
1113         }
1114         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1115                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1116                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1117                 lcd_enabled = 0;
1118                 return;
1119         }
1120         panel_info.vl_col = p->xres;
1121         panel_info.vl_row = p->yres;
1122
1123         switch (color_depth) {
1124         case 8:
1125                 panel_info.vl_bpix = LCD_COLOR8;
1126                 break;
1127         case 16:
1128                 panel_info.vl_bpix = LCD_COLOR16;
1129                 break;
1130         default:
1131                 panel_info.vl_bpix = LCD_COLOR24;
1132         }
1133
1134         p->pixclock = KHZ2PICOS(refresh *
1135                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1136                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1137                                 1000);
1138         debug("Pixel clock set to %lu.%03lu MHz\n",
1139                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1140
1141         if (p != &fb_mode) {
1142                 int ret;
1143
1144                 debug("Creating new display-timing node from '%s'\n",
1145                         video_mode);
1146                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1147                 if (ret)
1148                         printf("Failed to create new display-timing node from '%s': %d\n",
1149                                 video_mode, ret);
1150         }
1151
1152         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1153         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1154                                         ARRAY_SIZE(stk5_lcd_pads));
1155
1156         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1157         switch (lcd_bus_width) {
1158         case 24:
1159                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1160                 break;
1161
1162         case 18:
1163                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1164                 break;
1165
1166         case 16:
1167                 if (!is_lvds()) {
1168                         pix_fmt = IPU_PIX_FMT_RGB565;
1169                         break;
1170                 }
1171                 /* fallthru */
1172         default:
1173                 lcd_enabled = 0;
1174                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1175                         lcd_bus_width);
1176                 return;
1177         }
1178         if (is_lvds()) {
1179                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1180                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1181                 uint32_t gpr2;
1182
1183                 if (lvds_chan_mask == 0) {
1184                         printf("No LVDS channel active\n");
1185                         lcd_enabled = 0;
1186                         return;
1187                 }
1188
1189                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1190                 if (lcd_bus_width == 24)
1191                         gpr2 |= (1 << 5) | (1 << 7);
1192                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1193                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1194                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1195                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1196         }
1197         if (karo_load_splashimage(0) == 0) {
1198                 int ret;
1199
1200                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1201
1202                 debug("Initializing LCD controller\n");
1203                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1204                 if (ret) {
1205                         printf("Failed to initialize FB driver: %d\n", ret);
1206                         lcd_enabled = 0;
1207                 }
1208         } else {
1209                 debug("Skipping initialization of LCD controller\n");
1210         }
1211 }
1212 #else
1213 #define lcd_enabled 0
1214 #endif /* CONFIG_LCD */
1215
1216 static void stk5_board_init(void)
1217 {
1218         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1219         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1220 }
1221
1222 static void stk5v3_board_init(void)
1223 {
1224         stk5_board_init();
1225 }
1226
1227 static void stk5v5_board_init(void)
1228 {
1229         stk5_board_init();
1230
1231         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1232                         "Flexcan Transceiver");
1233         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1234 }
1235
1236 static void tx53_set_cpu_clock(void)
1237 {
1238         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1239
1240         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1241                 return;
1242
1243         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1244                 return;
1245
1246         if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1247                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1248                 printf("CPU clock set to %lu.%03lu MHz\n",
1249                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1250         } else {
1251                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1252         }
1253 }
1254
1255 static void tx53_init_mac(void)
1256 {
1257         u8 mac[ETH_ALEN];
1258
1259         imx_get_mac_from_fuse(0, mac);
1260         if (!is_valid_ether_addr(mac)) {
1261                 printf("No valid MAC address programmed\n");
1262                 return;
1263         }
1264
1265         printf("MAC addr from fuse: %pM\n", mac);
1266         eth_setenv_enetaddr("ethaddr", mac);
1267 }
1268
1269 int board_late_init(void)
1270 {
1271         int ret = 0;
1272         const char *baseboard;
1273
1274         tx53_set_cpu_clock();
1275         karo_fdt_move_fdt();
1276
1277         baseboard = getenv("baseboard");
1278         if (!baseboard)
1279                 goto exit;
1280
1281         printf("Baseboard: %s\n", baseboard);
1282
1283         if (strncmp(baseboard, "stk5", 4) == 0) {
1284                 if ((strlen(baseboard) == 4) ||
1285                         strcmp(baseboard, "stk5-v3") == 0) {
1286                         stk5v3_board_init();
1287                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1288                         const char *otg_mode = getenv("otg_mode");
1289
1290                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1291                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1292                                         otg_mode, baseboard);
1293                                 setenv("otg_mode", "none");
1294                         }
1295                         stk5v5_board_init();
1296                 } else {
1297                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1298                                 baseboard + 4);
1299                 }
1300         } else {
1301                 printf("WARNING: Unsupported baseboard: '%s'\n",
1302                         baseboard);
1303                 ret = -EINVAL;
1304         }
1305
1306 exit:
1307         tx53_init_mac();
1308
1309         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1310         clear_ctrlc();
1311         return ret;
1312 }
1313
1314 int checkboard(void)
1315 {
1316         tx53_print_cpuinfo();
1317
1318         printf("Board: Ka-Ro TX53-x%d3%s\n",
1319                 is_lvds(), TX53_MOD_SUFFIX);
1320
1321         return 0;
1322 }
1323
1324 #if defined(CONFIG_OF_BOARD_SETUP)
1325 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1326 #include <jffs2/jffs2.h>
1327 #include <mtd_node.h>
1328 static struct node_info nodes[] = {
1329         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1330 };
1331 #else
1332 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1333 #endif
1334
1335 #ifdef CONFIG_SYS_TX53_HWREV_2
1336 static void tx53_fixup_rtc(void *blob)
1337 {
1338         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1339         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1340 }
1341 #else
1342 static inline void tx53_fixup_rtc(void *blob)
1343 {
1344 }
1345 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1346
1347 static const char *tx53_touchpanels[] = {
1348         "ti,tsc2007",
1349         "edt,edt-ft5x06",
1350         "eeti,egalax_ts",
1351 };
1352
1353 void ft_board_setup(void *blob, bd_t *bd)
1354 {
1355         const char *baseboard = getenv("baseboard");
1356         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1357         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1358         int ret;
1359
1360         ret = fdt_increase_size(blob, 4096);
1361         if (ret)
1362                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1363
1364         if (stk5_v5)
1365                 karo_fdt_enable_node(blob, "stk5led", 0);
1366
1367         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1368         fdt_fixup_ethernet(blob);
1369
1370         karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1371                                 ARRAY_SIZE(tx53_touchpanels));
1372         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1373         karo_fdt_fixup_flexcan(blob, stk5_v5);
1374         tx53_fixup_rtc(blob);
1375         karo_fdt_update_fb_mode(blob, video_mode);
1376 }
1377 #endif /* CONFIG_OF_BOARD_SETUP */