Remove unused definition IOMUX_SION
[karo-tx-uboot.git] / board / karo / tx53 / tx53.c
1 /*
2  * Copyright (C) 2011 Lothar WaƟmann <LW@KARO-electronics.de>
3  * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 #include <common.h>
25 #include <errno.h>
26 #include <libfdt.h>
27 #include <fsl_esdhc.h>
28 #include <mmc.h>
29 #include <netdev.h>
30 #include <fdt_support.h>
31 #include <lcd.h>
32 #include <video_fb.h>
33 #include <ipu_pixfmt.h>
34 #include <mx2fb.h>
35 #include <linux/fb.h>
36 #include <asm/string.h>
37 #include <asm/io.h>
38 #include <asm/gpio.h>
39 #include <asm/arch/sys_proto.h>
40 #include <asm/arch/iomux-mx53.h>
41 #include <asm/arch/clock.h>
42 #include <asm/arch/imx-regs.h>
43 #include <asm/arch/crm_regs.h>
44
45 #define IMX_GPIO_NR(b, o)       ((((b) - 1) << 5) | (o))
46
47 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
48 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
49 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
50 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
51
52 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
53 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
54 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
55
56 DECLARE_GLOBAL_DATA_PTR;
57
58 #define MX53_GPIO_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE |            \
59                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
60
61 #define TX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_DSE_HIGH |       \
62                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN)
63
64 static iomux_v3_cfg_t tx53_pads[] = {
65         /* UART pads */
66         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
67         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
68         MX53_PAD_PATA_IORDY__UART1_RTS,
69         MX53_PAD_PATA_RESET_B__UART1_CTS,
70
71         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
72         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
73         MX53_PAD_PATA_DIOR__UART2_RTS,
74         MX53_PAD_PATA_INTRQ__UART2_CTS,
75
76         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
77         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
78         MX53_PAD_PATA_DA_2__UART3_RTS,
79         MX53_PAD_PATA_DA_1__UART3_CTS,
80
81         /* I2C */
82         NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, MX53_GPIO_PAD_CTRL),
83         NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, MX53_GPIO_PAD_CTRL),
84
85         /* SW controlled LED on STK5 baseboard */
86         MX53_PAD_EIM_A18__GPIO2_20,
87
88         /* FEC */
89         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
90         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
91         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
92
93         /* FEC functions */
94         MX53_PAD_FEC_MDC__FEC_MDC,
95         MX53_PAD_FEC_MDIO__FEC_MDIO,
96         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
97         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
98         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
99         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
100         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
101         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
102         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
103         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
104 };
105
106 static const struct gpio tx53_gpios[] = {
107         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
108         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
109         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
110 };
111
112 /*
113  * Functions
114  */
115 static u32 srsr;
116 static u32 wrsr;
117
118 #define WRSR_POR        (1 << 4)
119 #define WRSR_TOUT       (1 << 1)
120 #define WRSR_SFTW       (1 << 0)
121
122 static void print_reset_cause(void)
123 {
124         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
125         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
126         char *dlm = "";
127
128         printf("Reset cause: ");
129
130         srsr = readl(&src_regs->srsr);
131         wrsr = readw(wdt_base + 4);
132
133         if (wrsr & WRSR_POR) {
134                 printf("%sPOR", dlm);
135                 dlm = " | ";
136         }
137         if (srsr & 0x00004) {
138                 printf("%sCSU", dlm);
139                 dlm = " | ";
140         }
141         if (srsr & 0x00008) {
142                 printf("%sIPP USER", dlm);
143                 dlm = " | ";
144         }
145         if (srsr & 0x00010) {
146                 if (wrsr & WRSR_SFTW) {
147                         printf("%sSOFT", dlm);
148                         dlm = " | ";
149                 }
150                 if (wrsr & WRSR_TOUT) {
151                         printf("%sWDOG", dlm);
152                         dlm = " | ";
153                 }
154         }
155         if (srsr & 0x00020) {
156                 printf("%sJTAG HIGH-Z", dlm);
157                 dlm = " | ";
158         }
159         if (srsr & 0x00040) {
160                 printf("%sJTAG SW", dlm);
161                 dlm = " | ";
162         }
163         if (srsr & 0x10000) {
164                 printf("%sWARM BOOT", dlm);
165                 dlm = " | ";
166         }
167         if (dlm[0] == '\0')
168                 printf("unknown");
169
170         printf("\n");
171 }
172
173 static void print_cpuinfo(void)
174 {
175         u32 cpurev;
176
177         cpurev = get_cpu_rev();
178
179         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
180                 (cpurev & 0x000F0) >> 4,
181                 (cpurev & 0x0000F) >> 0,
182                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
183
184         print_reset_cause();
185 }
186
187 int board_early_init_f(void)
188 {
189         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
190         mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
191
192         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
193         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
194
195         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
196         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
197         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
198         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
199         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
200
201         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
202         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
203
204         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
205         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
206         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
207         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
208         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
209
210         return 0;
211 }
212
213 void coloured_LED_init(void)
214 {
215         /* Switch LED off */
216         gpio_set_value(TX53_LED_GPIO, 0);
217 }
218
219 int board_init(void)
220 {
221         /* Address of boot parameters */
222         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
223         return 0;
224 }
225
226 int dram_init(void)
227 {
228         int ret;
229
230         /* dram_init must store complete ramsize in gd->ram_size */
231         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
232                                 PHYS_SDRAM_1_SIZE);
233
234         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
235                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
236         if (ret)
237                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
238                         CONFIG_SYS_SDRAM_CLK, ret);
239         else
240                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
241                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
242                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
243                         CONFIG_SYS_SDRAM_CLK);
244         return ret;
245 }
246
247 void dram_init_banksize(void)
248 {
249         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
250         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
251                         PHYS_SDRAM_1_SIZE);
252 #if CONFIG_NR_DRAM_BANKS > 1
253         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
254         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
255                         PHYS_SDRAM_2_SIZE);
256 #endif
257 }
258
259 #ifdef  CONFIG_CMD_MMC
260 int board_mmc_getcd(struct mmc *mmc)
261 {
262         struct fsl_esdhc_cfg *cfg = mmc->priv;
263
264         if (cfg->cd_gpio < 0)
265                 return cfg->cd_gpio;
266
267         return !gpio_get_value(cfg->cd_gpio);
268 }
269
270 static struct fsl_esdhc_cfg esdhc_cfg[] = {
271         {
272                 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
273                 .no_snoop = 1,
274                 .cd_gpio = IMX_GPIO_NR(3, 24),
275                 .wp_gpio = -EINVAL,
276         },
277         {
278                 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
279                 .no_snoop = 1,
280                 .cd_gpio = IMX_GPIO_NR(3, 25),
281                 .wp_gpio = -EINVAL,
282         },
283 };
284
285 static const iomux_v3_cfg_t mmc0_pads[] = {
286         NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, TX53_SDHC_PAD_CTRL),
287         NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, TX53_SDHC_PAD_CTRL),
288         NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, TX53_SDHC_PAD_CTRL),
289         NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, TX53_SDHC_PAD_CTRL),
290         NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, TX53_SDHC_PAD_CTRL),
291         NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, TX53_SDHC_PAD_CTRL),
292         /* SD1 CD */
293         NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, MX53_GPIO_PAD_CTRL),
294 };
295
296 static const iomux_v3_cfg_t mmc1_pads[] = {
297         NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, TX53_SDHC_PAD_CTRL),
298         NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, TX53_SDHC_PAD_CTRL),
299         NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, TX53_SDHC_PAD_CTRL),
300         NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, TX53_SDHC_PAD_CTRL),
301         NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, TX53_SDHC_PAD_CTRL),
302         NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, TX53_SDHC_PAD_CTRL),
303         /* SD2 CD */
304         NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, MX53_GPIO_PAD_CTRL),
305 };
306
307 static struct {
308         const iomux_v3_cfg_t *pads;
309         int count;
310 } mmc_pad_config[] = {
311         { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
312         { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
313 };
314
315 int board_mmc_init(bd_t *bis)
316 {
317         int i;
318
319         for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
320 //              struct mmc *mmc;
321
322                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
323                         break;
324                 mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
325                                                 mmc_pad_config[i].count);
326                 fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
327 #if 0
328                 mmc = find_mmc_device(i);
329                 if (mmc == NULL)
330                         continue;
331                 if (board_mmc_getcd(mmc) > 0)
332                         mmc_init(mmc);
333 #endif
334         }
335         return 0;
336 }
337 #endif /* CONFIG_CMD_MMC */
338
339 #ifdef CONFIG_FEC_MXC
340
341 #ifndef ETH_ALEN
342 #define ETH_ALEN 6
343 #endif
344
345 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
346 {
347         int i;
348         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
349         struct fuse_bank *bank = &iim->bank[1];
350         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
351
352         if (dev_id > 0)
353                 return;
354
355         for (i = 0; i < ETH_ALEN; i++)
356                 mac[i] = readl(&fuse->mac_addr[i]);
357 }
358
359 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
360                         PAD_CTL_SRE_FAST)
361 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
362 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
363
364 int board_eth_init(bd_t *bis)
365 {
366         int ret;
367         unsigned char mac[ETH_ALEN];
368         char mac_str[ETH_ALEN * 3] = "";
369
370         /* delay at least 21ms for the PHY internal POR signal to deassert */
371         udelay(22000);
372         /* Deassert RESET to the external phy */
373         gpio_set_value(TX53_FEC_RST_GPIO, 1);
374
375         ret = cpu_eth_init(bis);
376         if (ret) {
377                 printf("cpu_eth_init() failed: %d\n", ret);
378         }
379
380         imx_get_mac_from_fuse(0, mac);
381         snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
382                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
383         setenv("ethaddr", mac_str);
384
385         return ret;
386 }
387 #endif /* CONFIG_FEC_MXC */
388
389 enum {
390         LED_STATE_INIT = -1,
391         LED_STATE_OFF,
392         LED_STATE_ON,
393 };
394
395 void show_activity(int arg)
396 {
397         static int led_state = LED_STATE_INIT;
398         static ulong last;
399
400         if (led_state == LED_STATE_INIT) {
401                 last = get_timer(0);
402                 gpio_set_value(TX53_LED_GPIO, 1);
403                 led_state = LED_STATE_ON;
404         } else {
405                 if (get_timer(last) > CONFIG_SYS_HZ) {
406                         last = get_timer(0);
407                         if (led_state == LED_STATE_ON) {
408                                 gpio_set_value(TX53_LED_GPIO, 0);
409                         } else {
410                                 gpio_set_value(TX53_LED_GPIO, 1);
411                         }
412                         led_state = 1 - led_state;
413                 }
414         }
415 }
416
417 static const iomux_v3_cfg_t stk5_pads[] = {
418         /* SW controlled LED on STK5 baseboard */
419         MX53_PAD_EIM_A18__GPIO2_20,
420
421         /* I2C bus on DIMM pins 40/41 */
422         NEW_PAD_CTRL(MX53_PAD_GPIO_6__I2C3_SDA, MX53_GPIO_PAD_CTRL),
423         NEW_PAD_CTRL(MX53_PAD_GPIO_3__I2C3_SCL, MX53_GPIO_PAD_CTRL),
424
425         /* TSC200x PEN IRQ */
426         NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, MX53_GPIO_PAD_CTRL),
427
428         /* EDT-FT5x06 Polytouch panel */
429         NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, MX53_GPIO_PAD_CTRL), /* IRQ */
430         NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, MX53_GPIO_PAD_CTRL), /* RESET */
431         NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, MX53_GPIO_PAD_CTRL), /* WAKE */
432
433         /* USBH1 */
434         NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, MX53_GPIO_PAD_CTRL), /* VBUSEN */
435         NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, MX53_GPIO_PAD_CTRL), /* OC */
436         /* USBOTG */
437         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
438         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
439
440         /* DS1339 Interrupt */
441         NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, MX53_GPIO_PAD_CTRL),
442 };
443
444 static const struct gpio stk5_gpios[] = {
445         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
446
447         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
448         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
449         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
450         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
451 };
452
453 #ifdef CONFIG_LCD
454 static u16 tx53_cmap[256];
455 vidinfo_t panel_info = {
456         /* set to max. size supported by SoC */
457         .vl_col = 1600,
458         .vl_row = 1200,
459
460         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
461         .cmap = tx53_cmap,
462 };
463
464 static struct fb_videomode tx53_fb_mode = {
465         /* Standard VGA timing */
466         .name           = "VGA",
467         .refresh        = 60,
468         .xres           = 640,
469         .yres           = 480,
470         .pixclock       = KHZ2PICOS(25175),
471         .left_margin    = 48,
472         .hsync_len      = 96,
473         .right_margin   = 16,
474         .upper_margin   = 31,
475         .vsync_len      = 2,
476         .lower_margin   = 12,
477         .sync           = FB_SYNC_CLK_LAT_FALL,
478         .vmode          = FB_VMODE_NONINTERLACED,
479 };
480
481 void *lcd_base;                 /* Start of framebuffer memory  */
482 void *lcd_console_address;      /* Start of console buffer      */
483
484 int lcd_line_length;
485 int lcd_color_fg;
486 int lcd_color_bg;
487
488 short console_col;
489 short console_row;
490
491 void lcd_initcolregs(void)
492 {
493 }
494
495 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
496 {
497 }
498
499 void lcd_enable(void)
500 {
501         /* HACK ALERT:
502          * global variable from common/lcd.c
503          * Set to 0 here to prevent messages from going to LCD
504          * rather than serial console
505          */
506         lcd_is_enabled = 0;
507 }
508
509 void lcd_disable(void)
510 {
511 }
512
513 void lcd_panel_disable(void)
514 {
515 }
516
517 static int lcd_enabled = 1;
518
519 static inline int tx53_load_splashimage(void)
520 {
521         int ret = 0;
522 #if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_LCD)
523         int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]);
524         cmd_tbl_t *cmd = find_cmd("nand");
525         char *loadaddr = getenv("splashimage");
526         char *argv[] = {
527                 "nand",
528                 "read",
529                 loadaddr,
530                 "logo",
531         };
532         const int argc = ARRAY_SIZE(argv);
533         unsigned long la;
534
535         if (!loadaddr)
536                 return 0;
537
538         if (tstc() || (wrsr & WRSR_TOUT))
539                 return -ENODEV;
540
541         if (!cmd)
542                 return -EINVAL;
543
544         la = simple_strtoul(loadaddr, NULL, 16);
545         if (la == 0)
546                 return -EINVAL;
547
548         /* clear BMP header in memory */
549         memset((void *)la, 0, 64);
550
551         ret = do_nand(cmd, 0, argc, argv);
552         if (ret) {
553                 printf("Failed to load logo: %d\n", ret);
554                 return ret;
555         }
556 #endif
557         return ret;
558 }
559
560 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
561         /* LCD RESET */
562         NEW_PAD_CTRL(MX53_PAD_EIM_D29__GPIO3_29, MX53_GPIO_PAD_CTRL),
563         /* LCD POWER_ENABLE */
564         NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, MX53_GPIO_PAD_CTRL),
565         /* LCD Backlight (PWM) */
566         NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, MX53_GPIO_PAD_CTRL),
567
568         /* Display */
569         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
570         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
571         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
572         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
573         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
574         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
575         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
576         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
577         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
578         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
579         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
580         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
581         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
582         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
583         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
584         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
585         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
586         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
587         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
588         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
589         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
590         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
591         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
592         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
593         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
594         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
595         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
596         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
597
598         /* LVDS option */
599         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
600         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
601         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
602         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
603         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
604         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
605         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
606         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
607         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
608         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
609 };
610
611 static const struct gpio stk5_lcd_gpios[] = {
612         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
613         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
614         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
615 };
616
617 void lcd_ctrl_init(void *lcdbase)
618 {
619         int color_depth = 24;
620         char *vm;
621         unsigned long val;
622         int refresh = 60;
623         struct fb_videomode *p = &tx53_fb_mode;
624         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
625         int pix_fmt = 0;
626
627         if (!lcd_enabled) {
628                 printf("LCD disabled\n");
629                 return;
630         }
631
632         if (tstc() || (wrsr & WRSR_TOUT)) {
633                 printf("%s@%d: Disabling LCD\n", __func__, __LINE__);
634                 lcd_enabled = 0;
635                 return;
636         }
637
638         vm = getenv("video_mode");
639         if (vm == NULL) {
640                 printf("%s@%d: Disabling LCD\n", __func__, __LINE__);
641                 lcd_enabled = 0;
642                 return;
643         }
644         while (*vm != '\0') {
645                 if (*vm >= '0' && *vm <= '9') {
646                         char *end;
647
648                         val = simple_strtoul(vm, &end, 0);
649                         if (end > vm) {
650                                 if (!xres_set) {
651                                         if (val > panel_info.vl_col)
652                                                 val = panel_info.vl_col;
653                                         p->xres = val;
654                                         panel_info.vl_col = val;
655                                         xres_set = 1;
656                                 } else if (!yres_set) {
657                                         if (val > panel_info.vl_row)
658                                                 val = panel_info.vl_row;
659                                         p->yres = val;
660                                         panel_info.vl_row = val;
661                                         yres_set = 1;
662                                 } else if (!bpp_set) {
663                                         switch (val) {
664                                         case 24:
665                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
666                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
667                                                 /* fallthru */
668                                         case 16:
669                                         case 8:
670                                                 color_depth = val;
671                                                 break;
672
673                                         case 18:
674                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
675                                                         color_depth = val;
676                                                         break;
677                                                 }
678                                                 /* fallthru */
679                                         default:
680                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
681                                                         end - vm, vm, color_depth);
682                                         }
683                                         bpp_set = 1;
684                                 } else if (!refresh_set) {
685                                         refresh = val;
686                                         refresh_set = 1;
687                                 }
688                         }
689                         vm = end;
690                 }
691                 switch (*vm) {
692                 case '@':
693                         bpp_set = 1;
694                         /* fallthru */
695                 case '-':
696                         yres_set = 1;
697                         /* fallthru */
698                 case 'x':
699                         xres_set = 1;
700                         /* fallthru */
701                 case 'M':
702                 case 'R':
703                         vm++;
704                         break;
705
706                 default:
707                         if (!pix_fmt) {
708                                 char *tmp;
709
710                                 if (strncmp(vm, "LVDS", 4) == 0)
711                                         pix_fmt = IPU_PIX_FMT_LVDS666;
712                                 else
713                                         pix_fmt = IPU_PIX_FMT_RGB24;
714                                 tmp = strchr(vm, ':');
715                                 if (tmp)
716                                         vm = tmp;
717                         }
718                         if (*vm != '\0')
719                                 vm++;
720                 }
721         }
722         switch (color_depth) {
723         case 8:
724                 panel_info.vl_bpix = 3;
725                 break;
726
727         case 16:
728                 panel_info.vl_bpix = 4;
729                 break;
730
731         case 18:
732         case 24:
733                 panel_info.vl_bpix = 5;
734         }
735         lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col;
736
737         p->pixclock = KHZ2PICOS(refresh *
738                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
739                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
740                 / 1000);
741         debug("Pixel clock set to %lu.%03lu MHz\n",
742                 PICOS2KHZ(p->pixclock) / 1000,
743                 PICOS2KHZ(p->pixclock) % 1000);
744
745         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
746         mxc_iomux_v3_setup_multiple_pads(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
747
748         debug("Initializing FB driver\n");
749         if (!pix_fmt)
750                 pix_fmt = IPU_PIX_FMT_RGB24;
751         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
752                 writel(0x01, IOMUXC_BASE_ADDR + 8);
753         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
754                 writel(0x21, IOMUXC_BASE_ADDR + 8);
755         }
756         if (pix_fmt != IPU_PIX_FMT_RGB24) {
757                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
758                 /* enable LDB & DI0 clock */
759                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
760                         &ccm_regs->CCGR6);
761         }
762
763         mx5_fb_init(p, 0, pix_fmt, 1 << panel_info.vl_bpix);
764
765         if (tx53_load_splashimage() == 0) {
766                 debug("Initializing LCD controller\n");
767                 video_hw_init();
768         } else {
769                 debug("Skipping initialization of LCD controller\n");
770         }
771 }
772
773 ulong calc_fbsize(void)
774 {
775         return panel_info.vl_row * panel_info.vl_col * 2 *
776                 NBITS(panel_info.vl_bpix) / 8;
777 }
778 #else
779 #define lcd_enabled 0
780 #endif /* CONFIG_LCD */
781
782 static void stk5_board_init(void)
783 {
784         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
785         mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
786 }
787
788 static void stk5v3_board_init(void)
789 {
790         stk5_board_init();
791 }
792
793 static void stk5v5_board_init(void)
794 {
795         stk5_board_init();
796 }
797
798 static void tx53_move_fdt(void)
799 {
800         const void *fdt = gd->fdt_blob;
801         unsigned long fdt_addr = getenv_ulong("fdtaddr", 16, 0);
802
803         if (!fdt || !fdt_addr) {
804                 printf("fdt=%p fdt_addr=%08lx\n", fdt, fdt_addr);
805                 return;
806         }
807
808         if (fdt_check_header(fdt)) {
809                 printf("ERROR: No valid FDT found at %p\n", fdt);
810                 return;
811         }
812
813         memmove((void *)fdt_addr, fdt, fdt_totalsize(fdt));
814         set_working_fdt_addr((void *)fdt_addr);
815 }
816
817 static void tx53_set_cpu_clock(void)
818 {
819         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
820         int ret;
821
822         if (tstc() || (wrsr & WRSR_TOUT))
823                 return;
824
825         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
826                 return;
827
828         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
829         if (ret != 0) {
830                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
831                 return;
832         }
833         printf("CPU clock set to %u.%03u MHz\n",
834                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
835                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
836 }
837
838 int board_late_init(void)
839 {
840         const char *baseboard;
841
842         tx53_set_cpu_clock();
843         tx53_move_fdt();
844
845         baseboard = getenv("baseboard");
846         if (!baseboard)
847                 return 0;
848
849         if (strncmp(baseboard, "stk5", 4) == 0) {
850                 printf("Baseboard: %s\n", baseboard);
851                 if ((strlen(baseboard) == 4) ||
852                         strcmp(baseboard, "stk5-v3") == 0) {
853                         stk5v3_board_init();
854                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
855                         stk5v5_board_init();
856                 } else {
857                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
858                                 baseboard + 4);
859                 }
860         } else {
861                 printf("WARNING: Unsupported baseboard: '%s'\n",
862                         baseboard);
863                 return -EINVAL;
864         }
865         if (lcd_enabled) {
866                 printf("Switching LCD on\n");
867                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
868                 udelay(100);
869                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
870                 udelay(300000);
871                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
872         }
873
874         return 0;
875 }
876
877 int checkboard(void)
878 {
879         print_cpuinfo();
880
881         printf("Board: Ka-Ro TX53-xx3%s\n",
882                 TX53_MOD_SUFFIX);
883
884         return 0;
885 }
886
887 #if defined(CONFIG_OF_BOARD_SETUP)
888 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
889 #include <jffs2/jffs2.h>
890 #include <mtd_node.h>
891 struct node_info nodes[] = {
892         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
893 };
894
895 #else
896 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
897 #endif
898
899 static const char *tx53_touchpanels[] = {
900         "ti,tsc2007",
901         "edt,edt-ft5x06",
902 };
903
904 static void fdt_del_tp_node(void *blob, const char *name)
905 {
906         int offs = fdt_node_offset_by_compatible(blob, -1, name);
907         uint32_t ph1 = 0, ph2 = 0;
908         const uint32_t *prop;
909
910         if (offs < 0) {
911                 debug("node '%s' not found: %d\n", name, offs);
912                 return;
913         }
914
915         prop = fdt_getprop(blob, offs, "reset-switch", NULL);
916         if (prop)
917                 ph1 = be32_to_cpu(*prop);
918
919         prop = fdt_getprop(blob, offs, "wake-switch", NULL);
920         if (prop)
921                 ph2 = be32_to_cpu(*prop);
922
923         debug("Removing node '%s' from DT\n", name);
924         fdt_del_node(blob, offs);
925
926         if (ph1) {
927                 offs = fdt_node_offset_by_phandle(blob, ph1);
928                 if (offs > 0) {
929                         debug("Removing node @ %08x\n", offs);
930                         fdt_del_node(blob, offs);
931                 }
932         }
933         if (ph2) {
934                 offs = fdt_node_offset_by_phandle(blob, ph2);
935                 if (offs > 0) {
936                         debug("Removing node @ %08x\n", offs);
937                         fdt_del_node(blob, offs);
938                 }
939         }
940 }
941
942 static void tx53_fixup_touchpanel(void *blob)
943 {
944         int i;
945         const char *model = getenv("touchpanel");
946
947         for (i = 0; i < ARRAY_SIZE(tx53_touchpanels); i++) {
948                 const char *tp = tx53_touchpanels[i];
949
950                 if (model != NULL && strcmp(model, tp) == 0)
951                         continue;
952
953                 tp = strchr(tp, ',');
954                 if (tp != NULL && *tp != '\0' && strcmp(model, tp + 1) == 0)
955                         continue;
956
957                 fdt_del_tp_node(blob, tx53_touchpanels[i]);
958         }
959 }
960
961 static void tx53_fixup_usb_otg(void *blob)
962 {
963         const char *otg_mode = getenv("otg_mode");
964         int usbphy = 2;
965
966         if (otg_mode == NULL || strcmp(otg_mode, "host") != 0) {
967                 debug("Removing node %s from DT\n", "usbh1");
968                 fdt_del_node_and_alias(blob, "usbh1");
969                 usbphy--;
970         }
971         if (otg_mode == NULL || strcmp(otg_mode, "device") != 0) {
972                 debug("Removing node %s from DT\n", "usbotg");
973                 fdt_del_node_and_alias(blob, "usbotg");
974                 usbphy--;
975         }
976         if (!usbphy) {
977                 debug("Removing node %s from DT\n", "usbphy");
978                 fdt_del_node_and_alias(blob, "usbphy");
979         }
980 }
981
982 static void tx53_fdt_del_prop(void *blob, const char *compat, phys_addr_t offs,
983                         const char *prop)
984 {
985         int ret;
986         int offset;
987         const uint32_t *phandle;
988         uint32_t ph = 0;
989
990         offset = fdt_node_offset_by_compat_reg(blob, compat, offs);
991         if (offset <= 0)
992                 return;
993
994         phandle = fdt_getprop(blob, offset, "transceiver-switch", NULL);
995         if (phandle) {
996                 ph = be32_to_cpu(*phandle);
997                 printf("phandle=%08x\n", ph);
998         }
999
1000         debug("Removing property '%s' from node %s@%08lx\n", prop, compat, offs);
1001         ret = fdt_delprop(blob, offset, prop);
1002         if (ret)
1003                 printf("Failed to remove property '%s' from node %s@%08lx\n",
1004                         prop, compat, offs);
1005
1006         if (!ph)
1007                 return;
1008
1009         offset = fdt_node_offset_by_phandle(blob, ph);
1010         printf("Node offset[%x]=%08x\n", ph, offset);
1011         if (offset <= 0)
1012                 return;
1013
1014         debug("Removing node @ %08x\n", offset);
1015         fdt_del_node(blob, offset);
1016 }
1017
1018 static void tx53_fixup_flexcan(void *blob)
1019 {
1020         const char *baseboard = getenv("baseboard");
1021
1022         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1023                 return;
1024
1025         tx53_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch");
1026         tx53_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch");
1027 }
1028
1029 void ft_board_setup(void *blob, bd_t *bd)
1030 {
1031         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1032         fdt_fixup_ethernet(blob);
1033
1034         tx53_fixup_touchpanel(blob);
1035         tx53_fixup_usb_otg(blob);
1036         tx53_fixup_flexcan(blob);
1037 }
1038 #endif