board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <i2c.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mxcfb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx53.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 #include "../common/karo.h"
  41
  42 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  43 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  44 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  45 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  46
  47 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  48 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  50
  51 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  56                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  57
  58 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  59                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  60
  61 static iomux_v3_cfg_t tx53_pads[] = {
  62         /* NAND flash pads are set up in lowlevel_init.S */
  63
  64         /* UART pads */
  65 #if CONFIG_MXC_UART_BASE == UART1_BASE
  66         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  67         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  68         MX53_PAD_PATA_IORDY__UART1_RTS,
  69         MX53_PAD_PATA_RESET_B__UART1_CTS,
  70 #endif
  71 #if CONFIG_MXC_UART_BASE == UART2_BASE
  72         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  73         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  74         MX53_PAD_PATA_DIOR__UART2_RTS,
  75         MX53_PAD_PATA_INTRQ__UART2_CTS,
  76 #endif
  77 #if CONFIG_MXC_UART_BASE == UART3_BASE
  78         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  79         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  80         MX53_PAD_PATA_DA_2__UART3_RTS,
  81         MX53_PAD_PATA_DA_1__UART3_CTS,
  82 #endif
  83         /* internal I2C */
  84         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  85         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  86
  87         /* FEC PHY GPIO functions */
  88         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  89         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  90         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  91
  92         /* FEC functions */
  93         MX53_PAD_FEC_MDC__FEC_MDC,
  94         MX53_PAD_FEC_MDIO__FEC_MDIO,
  95         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  96         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  97         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  98         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  99         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 100         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 101         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 102         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 103 };
 104
 105 static const struct gpio tx53_gpios[] = {
 106         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 107         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 108         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 109         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 110 };
 111
 112 /*
 113  * Functions
 114  */
 115 /* placed in section '.data' to prevent overwriting relocation info
 116  * overlayed with bss
 117  */
 118 static u32 wrsr __attribute__((section(".data")));
 119
 120 #define WRSR_POR        (1 << 4)
 121 #define WRSR_TOUT       (1 << 1)
 122 #define WRSR_SFTW       (1 << 0)
 123
 124 static void print_reset_cause(void)
 125 {
 126         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 127         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 128         u32 srsr;
 129         char *dlm = "";
 130
 131         printf("Reset cause: ");
 132
 133         srsr = readl(&src_regs->srsr);
 134         wrsr = readw(wdt_base + 4);
 135
 136         if (wrsr & WRSR_POR) {
 137                 printf("%sPOR", dlm);
 138                 dlm = " | ";
 139         }
 140         if (srsr & 0x00004) {
 141                 printf("%sCSU", dlm);
 142                 dlm = " | ";
 143         }
 144         if (srsr & 0x00008) {
 145                 printf("%sIPP USER", dlm);
 146                 dlm = " | ";
 147         }
 148         if (srsr & 0x00010) {
 149                 if (wrsr & WRSR_SFTW) {
 150                         printf("%sSOFT", dlm);
 151                         dlm = " | ";
 152                 }
 153                 if (wrsr & WRSR_TOUT) {
 154                         printf("%sWDOG", dlm);
 155                         dlm = " | ";
 156                 }
 157         }
 158         if (srsr & 0x00020) {
 159                 printf("%sJTAG HIGH-Z", dlm);
 160                 dlm = " | ";
 161         }
 162         if (srsr & 0x00040) {
 163                 printf("%sJTAG SW", dlm);
 164                 dlm = " | ";
 165         }
 166         if (srsr & 0x10000) {
 167                 printf("%sWARM BOOT", dlm);
 168                 dlm = " | ";
 169         }
 170         if (dlm[0] == '\0')
 171                 printf("unknown");
 172
 173         printf("\n");
 174 }
 175
 176 static void tx53_print_cpuinfo(void)
 177 {
 178         u32 cpurev;
 179
 180         cpurev = get_cpu_rev();
 181
 182         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 183                 (cpurev & 0x000F0) >> 4,
 184                 (cpurev & 0x0000F) >> 0,
 185                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 186
 187         print_reset_cause();
 188 }
 189
 190 enum LTC3589_REGS {
 191         LTC3589_SCR1 = 0x07,
 192         LTC3589_CLIRQ = 0x21,
 193         LTC3589_B1DTV1 = 0x23,
 194         LTC3589_B1DTV2 = 0x24,
 195         LTC3589_VRRCR = 0x25,
 196         LTC3589_B2DTV1 = 0x26,
 197         LTC3589_B2DTV2 = 0x27,
 198         LTC3589_B3DTV1 = 0x29,
 199         LTC3589_B3DTV2 = 0x2a,
 200         LTC3589_L2DTV1 = 0x32,
 201         LTC3589_L2DTV2 = 0x33,
 202 };
 203
 204 #define LTC3589_PGOOD_MASK      (1 << 5)
 205
 206 #define LTC3589_CLK_RATE_LOW    (1 << 5)
 207
 208 #define VDD_LDO2_10mV           vout_to_vref(1325 * 10, 2)
 209 #define VDD_CORE_10mV           vout_to_vref(1240 * 10, 3)
 210 #define VDD_SOC_10mV            vout_to_vref(1325 * 10, 4)
 211 #define VDD_BUCK3_10mV          vout_to_vref(2500 * 10, 5)
 212
 213 #ifndef CONFIG_SYS_TX53_HWREV_2
 214 /* LDO2 vref divider */
 215 #define R1_2    180
 216 #define R2_2    191
 217 /* BUCK1 vref divider */
 218 #define R1_3    150
 219 #define R2_3    180
 220 /* BUCK2 vref divider */
 221 #define R1_4    180
 222 #define R2_4    191
 223 /* BUCK3 vref divider */
 224 #define R1_5    270
 225 #define R2_5    100
 226 #else
 227 /* no dividers on vref */
 228 #define R1_2    0
 229 #define R2_2    1
 230 #define R1_3    0
 231 #define R2_3    1
 232 #define R1_4    0
 233 #define R2_4    1
 234 #define R1_5    0
 235 #define R2_5    1
 236 #endif
 237
 238 /* calculate voltages in 10mV */
 239 #define R1(idx)                 R1_##idx
 240 #define R2(idx)                 R2_##idx
 241
 242 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
 243 #define vref_to_vout(vref, idx) ((vref) * (R1(idx) + R2(idx)) / R2(idx))
 244
 245 #define mV_to_regval(mV)        (((((mV) < 3625) ? 3625 : (mV)) - 3625) / 125)
 246 #define regval_to_mV(v)         (((v) * 125 + 3625))
 247
 248 static struct pmic_regs {
 249         enum LTC3589_REGS addr;
 250         u8 val;
 251 } ltc3589_regs[] = {
 252         { LTC3589_SCR1, 0x55, }, /* burst mode for all regulators */
 253
 254         { LTC3589_L2DTV1, mV_to_regval(VDD_LDO2_10mV) | LTC3589_PGOOD_MASK, },
 255         { LTC3589_L2DTV2, mV_to_regval(VDD_LDO2_10mV) | LTC3589_CLK_RATE_LOW, },
 256
 257         { LTC3589_B1DTV1, mV_to_regval(VDD_CORE_10mV) | LTC3589_PGOOD_MASK, },
 258         { LTC3589_B1DTV2, mV_to_regval(VDD_CORE_10mV) | LTC3589_CLK_RATE_LOW, },
 259
 260         { LTC3589_B2DTV1, mV_to_regval(VDD_SOC_10mV) | LTC3589_PGOOD_MASK, },
 261         { LTC3589_B2DTV2, mV_to_regval(VDD_SOC_10mV) | LTC3589_CLK_RATE_LOW, },
 262
 263         { LTC3589_B3DTV1, mV_to_regval(VDD_BUCK3_10mV) | LTC3589_PGOOD_MASK, },
 264         { LTC3589_B3DTV2, mV_to_regval(VDD_BUCK3_10mV) | LTC3589_CLK_RATE_LOW, },
 265
 266         { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
 267 };
 268
 269 static int setup_pmic_voltages(void)
 270 {
 271         int ret;
 272         unsigned char value;
 273         int i;
 274
 275         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 276         if (ret != 0) {
 277                 printf("Failed to initialize I2C\n");
 278                 return ret;
 279         }
 280
 281         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 282         if (ret) {
 283                 printf("%s: i2c_read error: %d\n", __func__, ret);
 284                 return ret;
 285         }
 286
 287         for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
 288                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 289                                 &value, 1);
 290                 debug("Writing %02x to reg %02x (%02x)\n",
 291                         ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
 292                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 293                                 &ltc3589_regs[i].val, 1);
 294                 if (ret) {
 295                         printf("%s: failed to write PMIC register %02x: %d\n",
 296                                 __func__, ltc3589_regs[i].addr, ret);
 297                         return ret;
 298                 }
 299         }
 300         printf("VDDCORE set to %3d.%dmV\n",
 301                 vref_to_vout(regval_to_mV(mV_to_regval(VDD_CORE_10mV)), 3) / 10,
 302                 vref_to_vout(regval_to_mV(mV_to_regval(VDD_CORE_10mV)), 3) % 10);
 303
 304         printf("VDDSOC  set to %3d.%dmV\n",
 305                 vref_to_vout(regval_to_mV(mV_to_regval(VDD_SOC_10mV)), 4) / 10,
 306                 vref_to_vout(regval_to_mV(mV_to_regval(VDD_SOC_10mV)), 4) % 10);
 307         return 0;
 308 }
 309
 310 int board_early_init_f(void)
 311 {
 312         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 313
 314         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 315         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 316
 317         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 318         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 319
 320         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 321         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 322         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 323         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 324         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 325
 326         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 327         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 328
 329         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 330         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 331         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 332         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 333         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 334
 335         writel(0xffcf0fff, &ccm_regs->CCGR0);
 336         writel(0x000fffc3, &ccm_regs->CCGR1);
 337         writel(0x033c0000, &ccm_regs->CCGR2);
 338         writel(0x000000ff, &ccm_regs->CCGR3);
 339         writel(0x00000000, &ccm_regs->CCGR4);
 340         writel(0x00fff033, &ccm_regs->CCGR5);
 341         writel(0x0f00030f, &ccm_regs->CCGR6);
 342         writel(0xfff00000, &ccm_regs->CCGR7);
 343         writel(0x00000000, &ccm_regs->cmeor);
 344
 345         return 0;
 346 }
 347
 348 int board_init(void)
 349 {
 350         int ret;
 351
 352         /* Address of boot parameters */
 353         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 354
 355         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 356                 printf("CTRL-C detected; Skipping PMIC setup\n");
 357                 return 1;
 358         }
 359
 360         ret = setup_pmic_voltages();
 361         if (ret) {
 362                 printf("Failed to setup PMIC voltages\n");
 363                 hang();
 364         }
 365         return 0;
 366 }
 367
 368 int dram_init(void)
 369 {
 370         int ret;
 371
 372         /* dram_init must store complete ramsize in gd->ram_size */
 373         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 374                                 PHYS_SDRAM_1_SIZE);
 375
 376         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 377                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 378         if (ret)
 379                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 380                         CONFIG_SYS_SDRAM_CLK, ret);
 381         else
 382                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 383                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 384                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 385                         CONFIG_SYS_SDRAM_CLK);
 386         return ret;
 387 }
 388
 389 void dram_init_banksize(void)
 390 {
 391         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 392         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 393                         PHYS_SDRAM_1_SIZE);
 394 #if CONFIG_NR_DRAM_BANKS > 1
 395         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 396         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 397                         PHYS_SDRAM_2_SIZE);
 398 #endif
 399 }
 400
 401 #ifdef  CONFIG_CMD_MMC
 402 static const iomux_v3_cfg_t mmc0_pads[] = {
 403         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 404         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 405         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 406         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 407         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 408         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 409         /* SD1 CD */
 410         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 411 };
 412
 413 static const iomux_v3_cfg_t mmc1_pads[] = {
 414         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 415         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 416         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 417         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 418         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 419         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 420         /* SD2 CD */
 421         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 422 };
 423
 424 static struct tx53_esdhc_cfg {
 425         const iomux_v3_cfg_t *pads;
 426         int num_pads;
 427         struct fsl_esdhc_cfg cfg;
 428         int cd_gpio;
 429 } tx53_esdhc_cfg[] = {
 430         {
 431                 .pads = mmc0_pads,
 432                 .num_pads = ARRAY_SIZE(mmc0_pads),
 433                 .cfg = {
 434                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 435                         .max_bus_width = 4,
 436                 },
 437                 .cd_gpio = IMX_GPIO_NR(3, 24),
 438         },
 439         {
 440                 .pads = mmc1_pads,
 441                 .num_pads = ARRAY_SIZE(mmc1_pads),
 442                 .cfg = {
 443                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 444                         .max_bus_width = 4,
 445                 },
 446                 .cd_gpio = IMX_GPIO_NR(3, 25),
 447         },
 448 };
 449
 450 #define to_tx53_esdhc_cfg(p) container_of(p, struct tx53_esdhc_cfg, cfg)
 451
 452 int board_mmc_getcd(struct mmc *mmc)
 453 {
 454         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
 455
 456         if (cfg->cd_gpio < 0)
 457                 return cfg->cd_gpio;
 458
 459         debug("SD card %d is %spresent\n",
 460                 cfg - tx53_esdhc_cfg,
 461                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 462         return !gpio_get_value(cfg->cd_gpio);
 463 }
 464
 465 int board_mmc_init(bd_t *bis)
 466 {
 467         int i;
 468
 469         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
 470                 struct mmc *mmc;
 471                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
 472                 int ret;
 473
 474                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 475                         break;
 476
 477                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 478                                                 cfg->num_pads);
 479                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 480
 481                 fsl_esdhc_initialize(bis, &cfg->cfg);
 482
 483                 ret = gpio_request_one(cfg->cd_gpio,
 484                                 GPIOF_INPUT, "MMC CD");
 485                 if (ret) {
 486                         printf("Error %d requesting GPIO%d_%d\n",
 487                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 488                         continue;
 489                 }
 490
 491                 mmc = find_mmc_device(i);
 492                 if (mmc == NULL)
 493                         continue;
 494                 if (board_mmc_getcd(mmc) > 0)
 495                         mmc_init(mmc);
 496         }
 497         return 0;
 498 }
 499 #endif /* CONFIG_CMD_MMC */
 500
 501 #ifdef CONFIG_FEC_MXC
 502
 503 #ifndef ETH_ALEN
 504 #define ETH_ALEN 6
 505 #endif
 506
 507 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 508 {
 509         int i;
 510         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 511         struct fuse_bank *bank = &iim->bank[1];
 512         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 513
 514         if (dev_id > 0)
 515                 return;
 516
 517         for (i = 0; i < ETH_ALEN; i++)
 518                 mac[i] = readl(&fuse->mac_addr[i]);
 519 }
 520
 521 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 522                         PAD_CTL_SRE_FAST)
 523 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 524 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 525
 526 int board_eth_init(bd_t *bis)
 527 {
 528         int ret;
 529
 530         /* delay at least 21ms for the PHY internal POR signal to deassert */
 531         udelay(22000);
 532
 533         /* Deassert RESET to the external phy */
 534         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 535
 536         ret = cpu_eth_init(bis);
 537         if (ret)
 538                 printf("cpu_eth_init() failed: %d\n", ret);
 539         return ret;
 540 }
 541 #endif /* CONFIG_FEC_MXC */
 542
 543 enum {
 544         LED_STATE_INIT = -1,
 545         LED_STATE_OFF,
 546         LED_STATE_ON,
 547 };
 548
 549 void show_activity(int arg)
 550 {
 551         static int led_state = LED_STATE_INIT;
 552         static ulong last;
 553
 554         if (led_state == LED_STATE_INIT) {
 555                 last = get_timer(0);
 556                 gpio_set_value(TX53_LED_GPIO, 1);
 557                 led_state = LED_STATE_ON;
 558         } else {
 559                 if (get_timer(last) > CONFIG_SYS_HZ) {
 560                         last = get_timer(0);
 561                         if (led_state == LED_STATE_ON) {
 562                                 gpio_set_value(TX53_LED_GPIO, 0);
 563                         } else {
 564                                 gpio_set_value(TX53_LED_GPIO, 1);
 565                         }
 566                         led_state = 1 - led_state;
 567                 }
 568         }
 569 }
 570
 571 static const iomux_v3_cfg_t stk5_pads[] = {
 572         /* SW controlled LED on STK5 baseboard */
 573         MX53_PAD_EIM_A18__GPIO2_20,
 574
 575         /* I2C bus on DIMM pins 40/41 */
 576         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 577         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 578
 579         /* TSC200x PEN IRQ */
 580         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 581
 582         /* EDT-FT5x06 Polytouch panel */
 583         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 584         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 585         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 586
 587         /* USBH1 */
 588         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 589         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 590         /* USBOTG */
 591         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 592         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 593
 594         /* DS1339 Interrupt */
 595         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 596 };
 597
 598 static const struct gpio stk5_gpios[] = {
 599         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 600
 601         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 602         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 603         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 604         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 605 };
 606
 607 #ifdef CONFIG_LCD
 608 vidinfo_t panel_info = {
 609         /* set to max. size supported by SoC */
 610         .vl_col = 1600,
 611         .vl_row = 1200,
 612
 613         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 614 };
 615
 616 static struct fb_videomode tx53_fb_modes[] = {
 617         {
 618                 /* Standard VGA timing */
 619                 .name           = "VGA",
 620                 .refresh        = 60,
 621                 .xres           = 640,
 622                 .yres           = 480,
 623                 .pixclock       = KHZ2PICOS(25175),
 624                 .left_margin    = 48,
 625                 .hsync_len      = 96,
 626                 .right_margin   = 16,
 627                 .upper_margin   = 31,
 628                 .vsync_len      = 2,
 629                 .lower_margin   = 12,
 630                 .sync           = FB_SYNC_CLK_LAT_FALL,
 631         },
 632         {
 633                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 634                  * DE high active, 115.2 mm x 86.4 mm display area
 635                  * VGA compatible timing
 636                  */
 637                 .name           = "ETV570",
 638                 .refresh        = 60,
 639                 .xres           = 640,
 640                 .yres           = 480,
 641                 .pixclock       = KHZ2PICOS(25175),
 642                 .left_margin    = 114,
 643                 .hsync_len      = 30,
 644                 .right_margin   = 16,
 645                 .upper_margin   = 32,
 646                 .vsync_len      = 3,
 647                 .lower_margin   = 10,
 648                 .sync           = FB_SYNC_CLK_LAT_FALL,
 649         },
 650         {
 651                 /* Emerging ET0350G0DH6 320 x 240 display.
 652                  * 70.08 mm x 52.56 mm display area.
 653                  */
 654                 .name           = "ET0350",
 655                 .refresh        = 60,
 656                 .xres           = 320,
 657                 .yres           = 240,
 658                 .pixclock       = KHZ2PICOS(6500),
 659                 .left_margin    = 68 - 34,
 660                 .hsync_len      = 34,
 661                 .right_margin   = 20,
 662                 .upper_margin   = 18 - 3,
 663                 .vsync_len      = 3,
 664                 .lower_margin   = 4,
 665                 .sync           = FB_SYNC_CLK_LAT_FALL,
 666         },
 667         {
 668                 /* Emerging ET0430G0DH6 480 x 272 display.
 669                  * 95.04 mm x 53.856 mm display area.
 670                  */
 671                 .name           = "ET0430",
 672                 .refresh        = 60,
 673                 .xres           = 480,
 674                 .yres           = 272,
 675                 .pixclock       = KHZ2PICOS(9000),
 676                 .left_margin    = 2,
 677                 .hsync_len      = 41,
 678                 .right_margin   = 2,
 679                 .upper_margin   = 2,
 680                 .vsync_len      = 10,
 681                 .lower_margin   = 2,
 682                 .sync           = FB_SYNC_CLK_LAT_FALL,
 683         },
 684         {
 685                 /* Emerging ET0500G0DH6 800 x 480 display.
 686                  * 109.6 mm x 66.4 mm display area.
 687                  */
 688                 .name           = "ET0500",
 689                 .refresh        = 60,
 690                 .xres           = 800,
 691                 .yres           = 480,
 692                 .pixclock       = KHZ2PICOS(33260),
 693                 .left_margin    = 216 - 128,
 694                 .hsync_len      = 128,
 695                 .right_margin   = 1056 - 800 - 216,
 696                 .upper_margin   = 35 - 2,
 697                 .vsync_len      = 2,
 698                 .lower_margin   = 525 - 480 - 35,
 699                 .sync           = FB_SYNC_CLK_LAT_FALL,
 700         },
 701         {
 702                 /* Emerging ETQ570G0DH6 320 x 240 display.
 703                  * 115.2 mm x 86.4 mm display area.
 704                  */
 705                 .name           = "ETQ570",
 706                 .refresh        = 60,
 707                 .xres           = 320,
 708                 .yres           = 240,
 709                 .pixclock       = KHZ2PICOS(6400),
 710                 .left_margin    = 38,
 711                 .hsync_len      = 30,
 712                 .right_margin   = 30,
 713                 .upper_margin   = 16, /* 15 according to datasheet */
 714                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 715                 .lower_margin   = 4, /* 4.5 according to datasheet */
 716                 .sync           = FB_SYNC_CLK_LAT_FALL,
 717         },
 718         {
 719                 /* Emerging ET0700G0DH6 800 x 480 display.
 720                  * 152.4 mm x 91.44 mm display area.
 721                  */
 722                 .name           = "ET0700",
 723                 .refresh        = 60,
 724                 .xres           = 800,
 725                 .yres           = 480,
 726                 .pixclock       = KHZ2PICOS(33260),
 727                 .left_margin    = 216 - 128,
 728                 .hsync_len      = 128,
 729                 .right_margin   = 1056 - 800 - 216,
 730                 .upper_margin   = 35 - 2,
 731                 .vsync_len      = 2,
 732                 .lower_margin   = 525 - 480 - 35,
 733                 .sync           = FB_SYNC_CLK_LAT_FALL,
 734         },
 735         {
 736                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 737                 .refresh        = 60,
 738                 .left_margin    = 48,
 739                 .hsync_len      = 96,
 740                 .right_margin   = 16,
 741                 .upper_margin   = 31,
 742                 .vsync_len      = 2,
 743                 .lower_margin   = 12,
 744                 .sync           = FB_SYNC_CLK_LAT_FALL,
 745         },
 746 };
 747
 748 static int lcd_enabled = 1;
 749
 750 void lcd_enable(void)
 751 {
 752         /* HACK ALERT:
 753          * global variable from common/lcd.c
 754          * Set to 0 here to prevent messages from going to LCD
 755          * rather than serial console
 756          */
 757         lcd_is_enabled = 0;
 758
 759         if (lcd_enabled) {
 760                 karo_load_splashimage(1);
 761
 762                 debug("Switching LCD on\n");
 763                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 764                 udelay(100);
 765                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 766                 udelay(300000);
 767                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
 768         }
 769 }
 770
 771 void lcd_disable(void)
 772 {
 773         if (lcd_enabled) {
 774                 printf("Disabling LCD\n");
 775                 ipuv3_fb_shutdown();
 776         }
 777 }
 778
 779 void lcd_panel_disable(void)
 780 {
 781         if (lcd_enabled) {
 782                 debug("Switching LCD off\n");
 783                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1);
 784                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 785                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 786         }
 787 }
 788
 789 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 790         /* LCD RESET */
 791         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 792         /* LCD POWER_ENABLE */
 793         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 794         /* LCD Backlight (PWM) */
 795         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 796
 797         /* Display */
 798         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 799         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 800         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 801         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 802         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 803         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 804         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 805         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 806         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 807         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 808         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 809         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 810         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 811         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 812         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 813         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 814         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 815         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 816         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 817         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 818         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 819         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 820         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 821         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 822         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 823         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 824         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 825         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 826
 827         /* LVDS option */
 828         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 829         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 830         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 831         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 832         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 833         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 834         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 835         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 836         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 837         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 838 };
 839
 840 static const struct gpio stk5_lcd_gpios[] = {
 841         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 842         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 843         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 844 };
 845
 846 void lcd_ctrl_init(void *lcdbase)
 847 {
 848         int color_depth = 24;
 849         const char *video_mode = getenv("video_mode");
 850         const char *vm;
 851         unsigned long val;
 852         int refresh = 60;
 853         struct fb_videomode *p = &tx53_fb_modes[0];
 854         struct fb_videomode fb_mode;
 855         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 856         int pix_fmt = 0;
 857         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 858         unsigned long di_clk_rate = 65000000;
 859
 860         if (!lcd_enabled) {
 861                 debug("LCD disabled\n");
 862                 return;
 863         }
 864
 865         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 866                 debug("Disabling LCD\n");
 867                 lcd_enabled = 0;
 868                 setenv("splashimage", NULL);
 869                 return;
 870         }
 871
 872         karo_fdt_move_fdt();
 873
 874         vm = karo_fdt_set_display(video_mode, "/soc", "/soc/aips/ldb");
 875         if (vm == NULL) {
 876                 debug("Disabling LCD\n");
 877                 lcd_enabled = 0;
 878                 return;
 879         }
 880         video_mode = vm;
 881         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 882                 p = &fb_mode;
 883                 debug("Using video mode from FDT\n");
 884                 vm += strlen(vm);
 885                 if (fb_mode.xres > panel_info.vl_col ||
 886                         fb_mode.yres > panel_info.vl_row) {
 887                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 888                                 fb_mode.xres, fb_mode.yres,
 889                                 panel_info.vl_col, panel_info.vl_row);
 890                         lcd_enabled = 0;
 891                         return;
 892                 }
 893         }
 894         if (p->name != NULL)
 895                 debug("Trying compiled-in video modes\n");
 896         while (p->name != NULL) {
 897                 if (strcmp(p->name, vm) == 0) {
 898                         debug("Using video mode: '%s'\n", p->name);
 899                         vm += strlen(vm);
 900                         break;
 901                 }
 902                 p++;
 903         }
 904         if (*vm != '\0')
 905                 debug("Trying to decode video_mode: '%s'\n", vm);
 906         while (*vm != '\0') {
 907                 if (*vm >= '0' && *vm <= '9') {
 908                         char *end;
 909
 910                         val = simple_strtoul(vm, &end, 0);
 911                         if (end > vm) {
 912                                 if (!xres_set) {
 913                                         if (val > panel_info.vl_col)
 914                                                 val = panel_info.vl_col;
 915                                         p->xres = val;
 916                                         panel_info.vl_col = val;
 917                                         xres_set = 1;
 918                                 } else if (!yres_set) {
 919                                         if (val > panel_info.vl_row)
 920                                                 val = panel_info.vl_row;
 921                                         p->yres = val;
 922                                         panel_info.vl_row = val;
 923                                         yres_set = 1;
 924                                 } else if (!bpp_set) {
 925                                         switch (val) {
 926                                         case 32:
 927                                         case 24:
 928                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 929                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 930                                                 /* fallthru */
 931                                         case 16:
 932                                         case 8:
 933                                                 color_depth = val;
 934                                                 break;
 935
 936                                         case 18:
 937                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 938                                                         color_depth = val;
 939                                                         break;
 940                                                 }
 941                                                 /* fallthru */
 942                                         default:
 943                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 944                                                         end - vm, vm, color_depth);
 945                                         }
 946                                         bpp_set = 1;
 947                                 } else if (!refresh_set) {
 948                                         refresh = val;
 949                                         refresh_set = 1;
 950                                 }
 951                         }
 952                         vm = end;
 953                 }
 954                 switch (*vm) {
 955                 case '@':
 956                         bpp_set = 1;
 957                         /* fallthru */
 958                 case '-':
 959                         yres_set = 1;
 960                         /* fallthru */
 961                 case 'x':
 962                         xres_set = 1;
 963                         /* fallthru */
 964                 case 'M':
 965                 case 'R':
 966                         vm++;
 967                         break;
 968
 969                 default:
 970                         if (!pix_fmt) {
 971                                 char *tmp;
 972
 973                                 if (strncmp(vm, "LVDS", 4) == 0) {
 974                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 975                                         di_clk_parent = DI_PCLK_LDB;
 976                                 } else {
 977                                         pix_fmt = IPU_PIX_FMT_RGB24;
 978                                 }
 979                                 tmp = strchr(vm, ':');
 980                                 if (tmp)
 981                                         vm = tmp;
 982                         }
 983                         if (*vm != '\0')
 984                                 vm++;
 985                 }
 986         }
 987         if (p->xres == 0 || p->yres == 0) {
 988                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 989                 lcd_enabled = 0;
 990                 printf("Supported video modes are:");
 991                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
 992                         printf(" %s", p->name);
 993                 }
 994                 printf("\n");
 995                 return;
 996         }
 997         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 998                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 999                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1000                 lcd_enabled = 0;
1001                 return;
1002         }
1003         panel_info.vl_col = p->xres;
1004         panel_info.vl_row = p->yres;
1005
1006         switch (color_depth) {
1007         case 8:
1008                 panel_info.vl_bpix = LCD_COLOR8;
1009                 break;
1010         case 16:
1011                 panel_info.vl_bpix = LCD_COLOR16;
1012                 break;
1013         default:
1014                 panel_info.vl_bpix = LCD_COLOR24;
1015         }
1016
1017         p->pixclock = KHZ2PICOS(refresh *
1018                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1019                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
1020                 / 1000);
1021         debug("Pixel clock set to %lu.%03lu MHz\n",
1022                 PICOS2KHZ(p->pixclock) / 1000,
1023                 PICOS2KHZ(p->pixclock) % 1000);
1024
1025         if (p != &fb_mode) {
1026                 int ret;
1027
1028                 debug("Creating new display-timing node from '%s'\n",
1029                         video_mode);
1030                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1031                 if (ret)
1032                         printf("Failed to create new display-timing node from '%s': %d\n",
1033                                 video_mode, ret);
1034         }
1035
1036         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1037         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1038                                         ARRAY_SIZE(stk5_lcd_pads));
1039
1040         debug("Initializing FB driver\n");
1041         if (!pix_fmt)
1042                 pix_fmt = IPU_PIX_FMT_RGB24;
1043         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
1044                 writel(0x01, IOMUXC_BASE_ADDR + 8);
1045         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
1046                 writel(0x21, IOMUXC_BASE_ADDR + 8);
1047         }
1048         if (pix_fmt != IPU_PIX_FMT_RGB24) {
1049                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1050                 /* enable LDB & DI0 clock */
1051                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
1052                         &ccm_regs->CCGR6);
1053         }
1054
1055         if (karo_load_splashimage(0) == 0) {
1056                 int ret;
1057
1058                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1059
1060                 debug("Initializing LCD controller\n");
1061                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1062                 if (ret) {
1063                         printf("Failed to initialize FB driver: %d\n", ret);
1064                         lcd_enabled = 0;
1065                 }
1066         } else {
1067                 debug("Skipping initialization of LCD controller\n");
1068         }
1069 }
1070 #else
1071 #define lcd_enabled 0
1072 #endif /* CONFIG_LCD */
1073
1074 static void stk5_board_init(void)
1075 {
1076         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1077         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1078 }
1079
1080 static void stk5v3_board_init(void)
1081 {
1082         stk5_board_init();
1083 }
1084
1085 static void stk5v5_board_init(void)
1086 {
1087         stk5_board_init();
1088
1089         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1090                         "Flexcan Transceiver");
1091         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1092 }
1093
1094 static void tx53_set_cpu_clock(void)
1095 {
1096         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1097         int ret;
1098
1099         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1100                 return;
1101
1102         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1103                 return;
1104
1105         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
1106         if (ret != 0) {
1107                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1108                 return;
1109         }
1110         printf("CPU clock set to %u.%03u MHz\n",
1111                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
1112                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
1113 }
1114
1115 static void tx53_init_mac(void)
1116 {
1117         u8 mac[ETH_ALEN];
1118
1119         imx_get_mac_from_fuse(0, mac);
1120         if (!is_valid_ether_addr(mac)) {
1121                 printf("No valid MAC address programmed\n");
1122                 return;
1123         }
1124
1125         eth_setenv_enetaddr("ethaddr", mac);
1126         printf("MAC addr from fuse: %pM\n", mac);
1127 }
1128
1129 int board_late_init(void)
1130 {
1131         int ret = 0;
1132         const char *baseboard;
1133
1134         tx53_set_cpu_clock();
1135         karo_fdt_move_fdt();
1136
1137         baseboard = getenv("baseboard");
1138         if (!baseboard)
1139                 goto exit;
1140
1141         if (strncmp(baseboard, "stk5", 4) == 0) {
1142                 printf("Baseboard: %s\n", baseboard);
1143                 if ((strlen(baseboard) == 4) ||
1144                         strcmp(baseboard, "stk5-v3") == 0) {
1145                         stk5v3_board_init();
1146                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1147                         stk5v5_board_init();
1148                 } else {
1149                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1150                                 baseboard + 4);
1151                 }
1152         } else {
1153                 printf("WARNING: Unsupported baseboard: '%s'\n",
1154                         baseboard);
1155                 ret = -EINVAL;
1156         }
1157
1158 exit:
1159         tx53_init_mac();
1160         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1161         clear_ctrlc();
1162         return ret;
1163 }
1164
1165 int checkboard(void)
1166 {
1167         tx53_print_cpuinfo();
1168
1169         printf("Board: Ka-Ro TX53-xx3%s\n",
1170                 TX53_MOD_SUFFIX);
1171
1172         return 0;
1173 }
1174
1175 #if defined(CONFIG_OF_BOARD_SETUP)
1176 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1177 #include <jffs2/jffs2.h>
1178 #include <mtd_node.h>
1179 struct node_info nodes[] = {
1180         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1181 };
1182
1183 #else
1184 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1185 #endif
1186
1187 #ifdef CONFIG_SYS_TX53_HWREV_2
1188 void tx53_fixup_rtc(void *blob)
1189 {
1190         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1191         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1192 }
1193 #else
1194 static inline void tx53_fixup_rtc(void *blob)
1195 {
1196 }
1197 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1198
1199 void ft_board_setup(void *blob, bd_t *bd)
1200 {
1201         const char *baseboard = getenv("baseboard");
1202         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1203         const char *video_mode = getenv("video_mode");
1204
1205         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1206         fdt_fixup_ethernet(blob);
1207
1208         karo_fdt_fixup_touchpanel(blob);
1209         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1210         karo_fdt_fixup_flexcan(blob, stk5_v5);
1211         tx53_fixup_rtc(blob);
1212         video_mode = karo_fdt_set_display(video_mode, "/soc", "/soc/aips/ldb");
1213         karo_fdt_update_fb_mode(blob, video_mode);
1214 }
1215 #endif /* CONFIG_OF_BOARD_SETUP */