board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <common.h>
  21 #include <errno.h>
  22 #include <libfdt.h>
  23 #include <fdt_support.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mx2fb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx53.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 #include "../common/karo.h"
  41
  42 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  43 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  44 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  45 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  46
  47 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  48 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  50
  51 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  56                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  57
  58 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  59                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  60
  61 static iomux_v3_cfg_t tx53_pads[] = {
  62         /* NAND flash pads are set up in lowlevel_init.S */
  63
  64         /* RESET_OUT */
  65         MX53_PAD_GPIO_17__GPIO7_12,
  66
  67         /* UART pads */
  68 #if CONFIG_MXC_UART_BASE == UART1_BASE
  69         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  70         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  71         MX53_PAD_PATA_IORDY__UART1_RTS,
  72         MX53_PAD_PATA_RESET_B__UART1_CTS,
  73 #endif
  74 #if CONFIG_MXC_UART_BASE == UART2_BASE
  75         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  76         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  77         MX53_PAD_PATA_DIOR__UART2_RTS,
  78         MX53_PAD_PATA_INTRQ__UART2_CTS,
  79 #endif
  80 #if CONFIG_MXC_UART_BASE == UART3_BASE
  81         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  82         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  83         MX53_PAD_PATA_DA_2__UART3_RTS,
  84         MX53_PAD_PATA_DA_1__UART3_CTS,
  85 #endif
  86         /* internal I2C */
  87         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  88         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  89
  90         /* FEC PHY GPIO functions */
  91         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  92         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  93         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  94
  95         /* FEC functions */
  96         MX53_PAD_FEC_MDC__FEC_MDC,
  97         MX53_PAD_FEC_MDIO__FEC_MDIO,
  98         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  99         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 100         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 101         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 102         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 103         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 104         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 105         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 106 };
 107
 108 static const struct gpio tx53_gpios[] = {
 109         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 110         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 111         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 112         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 113 };
 114
 115 /*
 116  * Functions
 117  */
 118 /* placed in section '.data' to prevent overwriting relocation info
 119  * overlayed with bss
 120  */
 121 static u32 wrsr __attribute__((section(".data")));
 122
 123 #define WRSR_POR        (1 << 4)
 124 #define WRSR_TOUT       (1 << 1)
 125 #define WRSR_SFTW       (1 << 0)
 126
 127 static void print_reset_cause(void)
 128 {
 129         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 130         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 131         u32 srsr;
 132         char *dlm = "";
 133
 134         printf("Reset cause: ");
 135
 136         srsr = readl(&src_regs->srsr);
 137         wrsr = readw(wdt_base + 4);
 138
 139         if (wrsr & WRSR_POR) {
 140                 printf("%sPOR", dlm);
 141                 dlm = " | ";
 142         }
 143         if (srsr & 0x00004) {
 144                 printf("%sCSU", dlm);
 145                 dlm = " | ";
 146         }
 147         if (srsr & 0x00008) {
 148                 printf("%sIPP USER", dlm);
 149                 dlm = " | ";
 150         }
 151         if (srsr & 0x00010) {
 152                 if (wrsr & WRSR_SFTW) {
 153                         printf("%sSOFT", dlm);
 154                         dlm = " | ";
 155                 }
 156                 if (wrsr & WRSR_TOUT) {
 157                         printf("%sWDOG", dlm);
 158                         dlm = " | ";
 159                 }
 160         }
 161         if (srsr & 0x00020) {
 162                 printf("%sJTAG HIGH-Z", dlm);
 163                 dlm = " | ";
 164         }
 165         if (srsr & 0x00040) {
 166                 printf("%sJTAG SW", dlm);
 167                 dlm = " | ";
 168         }
 169         if (srsr & 0x10000) {
 170                 printf("%sWARM BOOT", dlm);
 171                 dlm = " | ";
 172         }
 173         if (dlm[0] == '\0')
 174                 printf("unknown");
 175
 176         printf("\n");
 177 }
 178
 179 static void print_cpuinfo(void)
 180 {
 181         u32 cpurev;
 182
 183         cpurev = get_cpu_rev();
 184
 185         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 186                 (cpurev & 0x000F0) >> 4,
 187                 (cpurev & 0x0000F) >> 0,
 188                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 189
 190         print_reset_cause();
 191 }
 192
 193 int board_early_init_f(void)
 194 {
 195         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 196         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 197
 198         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 199         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 200
 201         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 202         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 203         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 204         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 205         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 206
 207         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 208         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 209
 210         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 211         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 212         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 213         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 214         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 215
 216         return 0;
 217 }
 218
 219 int board_init(void)
 220 {
 221         /* Address of boot parameters */
 222         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 223         return 0;
 224 }
 225
 226 int dram_init(void)
 227 {
 228         int ret;
 229
 230         /* dram_init must store complete ramsize in gd->ram_size */
 231         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 232                                 PHYS_SDRAM_1_SIZE);
 233
 234         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 235                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 236         if (ret)
 237                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 238                         CONFIG_SYS_SDRAM_CLK, ret);
 239         else
 240                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 241                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 242                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 243                         CONFIG_SYS_SDRAM_CLK);
 244         return ret;
 245 }
 246
 247 void dram_init_banksize(void)
 248 {
 249         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 250         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 251                         PHYS_SDRAM_1_SIZE);
 252 #if CONFIG_NR_DRAM_BANKS > 1
 253         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 254         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 255                         PHYS_SDRAM_2_SIZE);
 256 #endif
 257 }
 258
 259 #ifdef  CONFIG_CMD_MMC
 260 int board_mmc_getcd(struct mmc *mmc)
 261 {
 262         struct fsl_esdhc_cfg *cfg = mmc->priv;
 263
 264         if (cfg->cd_gpio < 0)
 265                 return cfg->cd_gpio;
 266
 267         return !gpio_get_value(cfg->cd_gpio);
 268 }
 269
 270 static struct fsl_esdhc_cfg esdhc_cfg[] = {
 271         {
 272                 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 273                 .cd_gpio = IMX_GPIO_NR(3, 24),
 274                 .wp_gpio = -EINVAL,
 275         },
 276         {
 277                 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 278                 .cd_gpio = IMX_GPIO_NR(3, 25),
 279                 .wp_gpio = -EINVAL,
 280         },
 281 };
 282
 283 static const iomux_v3_cfg_t mmc0_pads[] = {
 284         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 285         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 286         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 287         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 288         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 289         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 290         /* SD1 CD */
 291         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 292 };
 293
 294 static const iomux_v3_cfg_t mmc1_pads[] = {
 295         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 296         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 297         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 298         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 299         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 300         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 301         /* SD2 CD */
 302         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 303 };
 304
 305 static struct {
 306         const iomux_v3_cfg_t *pads;
 307         int count;
 308 } mmc_pad_config[] = {
 309         { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
 310         { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
 311 };
 312
 313 int board_mmc_init(bd_t *bis)
 314 {
 315         int i;
 316
 317         for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
 318                 struct mmc *mmc;
 319
 320                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 321                         break;
 322
 323                 imx_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
 324                                                 mmc_pad_config[i].count);
 325                 fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
 326
 327                 mmc = find_mmc_device(i);
 328                 if (mmc == NULL)
 329                         continue;
 330                 if (board_mmc_getcd(mmc) > 0)
 331                         mmc_init(mmc);
 332         }
 333         return 0;
 334 }
 335 #endif /* CONFIG_CMD_MMC */
 336
 337 #ifdef CONFIG_FEC_MXC
 338
 339 #ifndef ETH_ALEN
 340 #define ETH_ALEN 6
 341 #endif
 342
 343 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 344 {
 345         int i;
 346         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 347         struct fuse_bank *bank = &iim->bank[1];
 348         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 349
 350         if (dev_id > 0)
 351                 return;
 352
 353         for (i = 0; i < ETH_ALEN; i++)
 354                 mac[i] = readl(&fuse->mac_addr[i]);
 355 }
 356
 357 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 358                         PAD_CTL_SRE_FAST)
 359 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 360 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 361
 362 int board_eth_init(bd_t *bis)
 363 {
 364         int ret;
 365         unsigned char mac[ETH_ALEN];
 366         char mac_str[ETH_ALEN * 3] = "";
 367
 368         /* delay at least 21ms for the PHY internal POR signal to deassert */
 369         udelay(22000);
 370
 371         /* Deassert RESET to the external phy */
 372         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 373
 374         ret = cpu_eth_init(bis);
 375         if (ret) {
 376                 printf("cpu_eth_init() failed: %d\n", ret);
 377                 return ret;
 378         }
 379
 380         imx_get_mac_from_fuse(0, mac);
 381         snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
 382                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 383         setenv("ethaddr", mac_str);
 384
 385         return ret;
 386 }
 387 #endif /* CONFIG_FEC_MXC */
 388
 389 enum {
 390         LED_STATE_INIT = -1,
 391         LED_STATE_OFF,
 392         LED_STATE_ON,
 393 };
 394
 395 void show_activity(int arg)
 396 {
 397         static int led_state = LED_STATE_INIT;
 398         static ulong last;
 399
 400         if (led_state == LED_STATE_INIT) {
 401                 last = get_timer(0);
 402                 gpio_set_value(TX53_LED_GPIO, 1);
 403                 led_state = LED_STATE_ON;
 404         } else {
 405                 if (get_timer(last) > CONFIG_SYS_HZ) {
 406                         last = get_timer(0);
 407                         if (led_state == LED_STATE_ON) {
 408                                 gpio_set_value(TX53_LED_GPIO, 0);
 409                         } else {
 410                                 gpio_set_value(TX53_LED_GPIO, 1);
 411                         }
 412                         led_state = 1 - led_state;
 413                 }
 414         }
 415 }
 416
 417 static const iomux_v3_cfg_t stk5_pads[] = {
 418         /* SW controlled LED on STK5 baseboard */
 419         MX53_PAD_EIM_A18__GPIO2_20,
 420
 421         /* I2C bus on DIMM pins 40/41 */
 422         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 423         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 424
 425         /* TSC200x PEN IRQ */
 426         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 427
 428         /* EDT-FT5x06 Polytouch panel */
 429         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 430         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 431         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 432
 433         /* USBH1 */
 434         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 435         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 436         /* USBOTG */
 437         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 438         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 439
 440         /* DS1339 Interrupt */
 441         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 442 };
 443
 444 static const struct gpio stk5_gpios[] = {
 445         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 446
 447         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 448         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 449         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 450         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 451 };
 452
 453 #ifdef CONFIG_LCD
 454 static ushort tx53_cmap[256];
 455 vidinfo_t panel_info = {
 456         /* set to max. size supported by SoC */
 457         .vl_col = 1600,
 458         .vl_row = 1200,
 459
 460         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 461         .cmap = tx53_cmap,
 462 };
 463
 464 static struct fb_videomode tx53_fb_mode = {
 465         /* Standard VGA timing */
 466         .name           = "VGA",
 467         .refresh        = 60,
 468         .xres           = 640,
 469         .yres           = 480,
 470         .pixclock       = KHZ2PICOS(25175),
 471         .left_margin    = 48,
 472         .hsync_len      = 96,
 473         .right_margin   = 16,
 474         .upper_margin   = 31,
 475         .vsync_len      = 2,
 476         .lower_margin   = 12,
 477         .sync           = FB_SYNC_CLK_LAT_FALL,
 478         .vmode          = FB_VMODE_NONINTERLACED,
 479 };
 480
 481 static int lcd_enabled = 1;
 482
 483 void lcd_enable(void)
 484 {
 485         /* HACK ALERT:
 486          * global variable from common/lcd.c
 487          * Set to 0 here to prevent messages from going to LCD
 488          * rather than serial console
 489          */
 490         lcd_is_enabled = 0;
 491
 492         karo_load_splashimage(1);
 493         if (lcd_enabled) {
 494                 debug("Switching LCD on\n");
 495                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 496                 udelay(100);
 497                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 498                 udelay(300000);
 499                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
 500         }
 501 }
 502
 503 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 504         /* LCD RESET */
 505         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 506         /* LCD POWER_ENABLE */
 507         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 508         /* LCD Backlight (PWM) */
 509         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 510
 511         /* Display */
 512         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 513         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 514         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 515         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 516         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 517         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 518         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 519         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 520         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 521         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 522         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 523         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 524         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 525         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 526         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 527         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 528         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 529         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 530         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 531         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 532         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 533         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 534         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 535         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 536         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 537         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 538         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 539         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 540
 541         /* LVDS option */
 542         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 543         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 544         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 545         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 546         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 547         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 548         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 549         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 550         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 551         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 552 };
 553
 554 static const struct gpio stk5_lcd_gpios[] = {
 555         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 556         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 557         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 558 };
 559
 560 void lcd_ctrl_init(void *lcdbase)
 561 {
 562         int color_depth = 24;
 563         char *vm;
 564         unsigned long val;
 565         int refresh = 60;
 566         struct fb_videomode *p = &tx53_fb_mode;
 567         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 568         int pix_fmt = 0;
 569         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 570         unsigned long di_clk_rate = 65000000;
 571
 572         if (!lcd_enabled) {
 573                 debug("LCD disabled\n");
 574                 return;
 575         }
 576
 577         if (tstc() || (wrsr & WRSR_TOUT)) {
 578                 debug("Disabling LCD\n");
 579                 lcd_enabled = 0;
 580                 return;
 581         }
 582
 583         vm = getenv("video_mode");
 584         if (vm == NULL) {
 585                 debug("Disabling LCD\n");
 586                 lcd_enabled = 0;
 587                 return;
 588         }
 589         while (*vm != '\0') {
 590                 if (*vm >= '0' && *vm <= '9') {
 591                         char *end;
 592
 593                         val = simple_strtoul(vm, &end, 0);
 594                         if (end > vm) {
 595                                 if (!xres_set) {
 596                                         if (val > panel_info.vl_col)
 597                                                 val = panel_info.vl_col;
 598                                         p->xres = val;
 599                                         panel_info.vl_col = val;
 600                                         xres_set = 1;
 601                                 } else if (!yres_set) {
 602                                         if (val > panel_info.vl_row)
 603                                                 val = panel_info.vl_row;
 604                                         p->yres = val;
 605                                         panel_info.vl_row = val;
 606                                         yres_set = 1;
 607                                 } else if (!bpp_set) {
 608                                         switch (val) {
 609                                         case 24:
 610                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 611                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 612                                                 /* fallthru */
 613                                         case 16:
 614                                         case 8:
 615                                                 color_depth = val;
 616                                                 break;
 617
 618                                         case 18:
 619                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 620                                                         color_depth = val;
 621                                                         break;
 622                                                 }
 623                                                 /* fallthru */
 624                                         default:
 625                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 626                                                         end - vm, vm, color_depth);
 627                                         }
 628                                         bpp_set = 1;
 629                                 } else if (!refresh_set) {
 630                                         refresh = val;
 631                                         refresh_set = 1;
 632                                 }
 633                         }
 634                         vm = end;
 635                 }
 636                 switch (*vm) {
 637                 case '@':
 638                         bpp_set = 1;
 639                         /* fallthru */
 640                 case '-':
 641                         yres_set = 1;
 642                         /* fallthru */
 643                 case 'x':
 644                         xres_set = 1;
 645                         /* fallthru */
 646                 case 'M':
 647                 case 'R':
 648                         vm++;
 649                         break;
 650
 651                 default:
 652                         if (!pix_fmt) {
 653                                 char *tmp;
 654
 655                                 if (strncmp(vm, "LVDS", 4) == 0) {
 656                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 657                                         di_clk_parent = DI_PCLK_LDB;
 658                                 } else {
 659                                         pix_fmt = IPU_PIX_FMT_RGB24;
 660                                 }
 661                                 tmp = strchr(vm, ':');
 662                                 if (tmp)
 663                                         vm = tmp;
 664                         }
 665                         if (*vm != '\0')
 666                                 vm++;
 667                 }
 668         }
 669         switch (color_depth) {
 670         case 8:
 671                 panel_info.vl_bpix = 3;
 672                 break;
 673
 674         case 16:
 675                 panel_info.vl_bpix = 4;
 676                 break;
 677
 678         case 18:
 679         case 24:
 680                 panel_info.vl_bpix = 5;
 681         }
 682
 683         p->pixclock = KHZ2PICOS(refresh *
 684                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 685                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 686                 / 1000);
 687         debug("Pixel clock set to %lu.%03lu MHz\n",
 688                 PICOS2KHZ(p->pixclock) / 1000,
 689                 PICOS2KHZ(p->pixclock) % 1000);
 690
 691         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 692         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 693                                         ARRAY_SIZE(stk5_lcd_pads));
 694
 695         debug("Initializing FB driver\n");
 696         if (!pix_fmt)
 697                 pix_fmt = IPU_PIX_FMT_RGB24;
 698         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 699                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 700         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 701                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 702         }
 703         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 704                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 705                 /* enable LDB & DI0 clock */
 706                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
 707                         &ccm_regs->CCGR6);
 708         }
 709
 710         if (karo_load_splashimage(0) == 0) {
 711                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 712
 713                 debug("Initializing LCD controller\n");
 714 //              video_hw_init();
 715         } else {
 716                 debug("Skipping initialization of LCD controller\n");
 717         }
 718 }
 719 #else
 720 #define lcd_enabled 0
 721 #endif /* CONFIG_LCD */
 722
 723 static void stk5_board_init(void)
 724 {
 725         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 726         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 727 }
 728
 729 static void stk5v3_board_init(void)
 730 {
 731         stk5_board_init();
 732 }
 733
 734 static void stk5v5_board_init(void)
 735 {
 736         stk5_board_init();
 737
 738         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
 739                         "Flexcan Transceiver");
 740         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
 741 }
 742
 743 static void tx53_set_cpu_clock(void)
 744 {
 745         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 746         int ret;
 747
 748         if (tstc() || (wrsr & WRSR_TOUT))
 749                 return;
 750
 751         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 752                 return;
 753
 754         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
 755         if (ret != 0) {
 756                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 757                 return;
 758         }
 759         printf("CPU clock set to %u.%03u MHz\n",
 760                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
 761                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
 762 }
 763
 764 int board_late_init(void)
 765 {
 766         int ret = 0;
 767         const char *baseboard;
 768
 769         tx53_set_cpu_clock();
 770         karo_fdt_move_fdt();
 771
 772         baseboard = getenv("baseboard");
 773         if (!baseboard)
 774                 goto exit;
 775
 776         if (strncmp(baseboard, "stk5", 4) == 0) {
 777                 printf("Baseboard: %s\n", baseboard);
 778                 if ((strlen(baseboard) == 4) ||
 779                         strcmp(baseboard, "stk5-v3") == 0) {
 780                         stk5v3_board_init();
 781                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 782                         stk5v5_board_init();
 783                 } else {
 784                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 785                                 baseboard + 4);
 786                 }
 787         } else {
 788                 printf("WARNING: Unsupported baseboard: '%s'\n",
 789                         baseboard);
 790                 ret = -EINVAL;
 791         }
 792
 793 exit:
 794         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
 795         return ret;
 796 }
 797
 798 int checkboard(void)
 799 {
 800         print_cpuinfo();
 801
 802         printf("Board: Ka-Ro TX53-xx3%s\n",
 803                 TX53_MOD_SUFFIX);
 804
 805         return 0;
 806 }
 807
 808 #if defined(CONFIG_OF_BOARD_SETUP)
 809 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 810 #include <jffs2/jffs2.h>
 811 #include <mtd_node.h>
 812 struct node_info nodes[] = {
 813         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
 814 };
 815
 816 #else
 817 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 818 #endif
 819
 820 static void tx53_fixup_flexcan(void *blob)
 821 {
 822         const char *baseboard = getenv("baseboard");
 823
 824         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
 825                 return;
 826
 827         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch");
 828         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch");
 829 }
 830
 831 #ifdef CONFIG_SYS_TX53_HWREV_2
 832 void tx53_fixup_rtc(void *blob)
 833 {
 834         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
 835         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
 836 }
 837 #else
 838 static inline void tx53_fixup_rtc(void *blob)
 839 {
 840 }
 841 #endif
 842
 843 void ft_board_setup(void *blob, bd_t *bd)
 844 {
 845         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 846         fdt_fixup_ethernet(blob);
 847
 848         karo_fdt_enable_node(blob, "ipu", getenv("video_mode") != NULL);
 849         karo_fdt_fixup_touchpanel(blob);
 850         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", 0x53f80000);
 851         tx53_fixup_flexcan(blob);
 852         tx53_fixup_rtc(blob);
 853 }
 854 #endif