board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <errno.h>
  26 #include <libfdt.h>
  27 #include <fsl_esdhc.h>
  28 #include <mmc.h>
  29 #include <netdev.h>
  30 #include <fdt_support.h>
  31 #include <lcd.h>
  32 #include <video_fb.h>
  33 #include <ipu_pixfmt.h>
  34 #include <mx2fb.h>
  35 #include <linux/fb.h>
  36 #include <asm/string.h>
  37 #include <asm/io.h>
  38 #include <asm/gpio.h>
  39 #include <asm/arch/sys_proto.h>
  40 #include <asm/arch/iomux-mx53.h>
  41 #include <asm/arch/clock.h>
  42 #include <asm/arch/imx-regs.h>
  43 #include <asm/arch/crm_regs.h>
  44
  45 #define IMX_GPIO_NR(b, o)       ((((b) - 1) << 5) | (o))
  46
  47 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  48 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  49 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  50 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  51
  52 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  53 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  54 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  55
  56 DECLARE_GLOBAL_DATA_PTR;
  57
  58 #define IOMUX_SION              IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  59
  60 #define MX53_GPIO_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE |            \
  61                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  62
  63 #define TX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_DSE_HIGH |       \
  64                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN)
  65
  66 static iomux_v3_cfg_t tx53_pads[] = {
  67         /* UART pads */
  68         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  69         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  70         MX53_PAD_PATA_IORDY__UART1_RTS,
  71         MX53_PAD_PATA_RESET_B__UART1_CTS,
  72
  73         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  74         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  75         MX53_PAD_PATA_DIOR__UART2_RTS,
  76         MX53_PAD_PATA_INTRQ__UART2_CTS,
  77
  78         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  79         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  80         MX53_PAD_PATA_DA_2__UART3_RTS,
  81         MX53_PAD_PATA_DA_1__UART3_CTS,
  82
  83         /* I2C */
  84         NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, MX53_GPIO_PAD_CTRL),
  85         NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, MX53_GPIO_PAD_CTRL),
  86
  87         /* SW controlled LED on STK5 baseboard */
  88         MX53_PAD_EIM_A18__GPIO2_20,
  89
  90         /* FEC */
  91         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  92         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  93         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  94
  95         /* FEC functions */
  96         MX53_PAD_FEC_MDC__FEC_MDC,
  97         MX53_PAD_FEC_MDIO__FEC_MDIO,
  98         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  99         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 100         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 101         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 102         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 103         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 104         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 105         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 106 };
 107
 108 static const struct gpio tx53_gpios[] = {
 109         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 110         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 111         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 112 };
 113
 114 /*
 115  * Functions
 116  */
 117 static u32 srsr;
 118 static u32 wrsr;
 119
 120 #define WRSR_POR        (1 << 4)
 121 #define WRSR_TOUT       (1 << 1)
 122 #define WRSR_SFTW       (1 << 0)
 123
 124 static void print_reset_cause(void)
 125 {
 126         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 127         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 128         char *dlm = "";
 129
 130         printf("Reset cause: ");
 131
 132         srsr = readl(&src_regs->srsr);
 133         wrsr = readw(wdt_base + 4);
 134
 135         if (wrsr & WRSR_POR) {
 136                 printf("%sPOR", dlm);
 137                 dlm = " | ";
 138         }
 139         if (srsr & 0x00004) {
 140                 printf("%sCSU", dlm);
 141                 dlm = " | ";
 142         }
 143         if (srsr & 0x00008) {
 144                 printf("%sIPP USER", dlm);
 145                 dlm = " | ";
 146         }
 147         if (srsr & 0x00010) {
 148                 if (wrsr & WRSR_SFTW) {
 149                         printf("%sSOFT", dlm);
 150                         dlm = " | ";
 151                 }
 152                 if (wrsr & WRSR_TOUT) {
 153                         printf("%sWDOG", dlm);
 154                         dlm = " | ";
 155                 }
 156         }
 157         if (srsr & 0x00020) {
 158                 printf("%sJTAG HIGH-Z", dlm);
 159                 dlm = " | ";
 160         }
 161         if (srsr & 0x00040) {
 162                 printf("%sJTAG SW", dlm);
 163                 dlm = " | ";
 164         }
 165         if (srsr & 0x10000) {
 166                 printf("%sWARM BOOT", dlm);
 167                 dlm = " | ";
 168         }
 169         if (dlm[0] == '\0')
 170                 printf("unknown");
 171
 172         printf("\n");
 173 }
 174
 175 static void print_cpuinfo(void)
 176 {
 177         u32 cpurev;
 178
 179         cpurev = get_cpu_rev();
 180
 181         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 182                 (cpurev & 0x000F0) >> 4,
 183                 (cpurev & 0x0000F) >> 0,
 184                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 185
 186         print_reset_cause();
 187 }
 188
 189 int board_early_init_f(void)
 190 {
 191         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 192         mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 193
 194         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 195         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 196
 197         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 198         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 199         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 200         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 201         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 202
 203         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 204         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 205
 206         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 207         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 208         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 209         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 210         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 211
 212         return 0;
 213 }
 214
 215 void coloured_LED_init(void)
 216 {
 217         /* Switch LED off */
 218         gpio_set_value(TX53_LED_GPIO, 0);
 219 }
 220
 221 int board_init(void)
 222 {
 223         /* Address of boot parameters */
 224         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 225         return 0;
 226 }
 227
 228 int dram_init(void)
 229 {
 230         int ret;
 231
 232         /* dram_init must store complete ramsize in gd->ram_size */
 233         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 234                                 PHYS_SDRAM_1_SIZE);
 235
 236         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 237                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 238         if (ret)
 239                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 240                         CONFIG_SYS_SDRAM_CLK, ret);
 241         else
 242                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 243                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 244                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 245                         CONFIG_SYS_SDRAM_CLK);
 246         return ret;
 247 }
 248
 249 void dram_init_banksize(void)
 250 {
 251         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 252         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 253                         PHYS_SDRAM_1_SIZE);
 254 #if CONFIG_NR_DRAM_BANKS > 1
 255         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 256         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 257                         PHYS_SDRAM_2_SIZE);
 258 #endif
 259 }
 260
 261 #ifdef  CONFIG_CMD_MMC
 262 int board_mmc_getcd(struct mmc *mmc)
 263 {
 264         struct fsl_esdhc_cfg *cfg = mmc->priv;
 265
 266         if (cfg->cd_gpio < 0)
 267                 return cfg->cd_gpio;
 268
 269         return !gpio_get_value(cfg->cd_gpio);
 270 }
 271
 272 static struct fsl_esdhc_cfg esdhc_cfg[] = {
 273         {
 274                 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 275                 .no_snoop = 1,
 276                 .cd_gpio = IMX_GPIO_NR(3, 24),
 277                 .wp_gpio = -EINVAL,
 278         },
 279         {
 280                 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 281                 .no_snoop = 1,
 282                 .cd_gpio = IMX_GPIO_NR(3, 25),
 283                 .wp_gpio = -EINVAL,
 284         },
 285 };
 286
 287 static const iomux_v3_cfg_t mmc0_pads[] = {
 288         NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, TX53_SDHC_PAD_CTRL),
 289         NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, TX53_SDHC_PAD_CTRL),
 290         NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, TX53_SDHC_PAD_CTRL),
 291         NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, TX53_SDHC_PAD_CTRL),
 292         NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, TX53_SDHC_PAD_CTRL),
 293         NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, TX53_SDHC_PAD_CTRL),
 294         /* SD1 CD */
 295         NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, MX53_GPIO_PAD_CTRL),
 296 };
 297
 298 static const iomux_v3_cfg_t mmc1_pads[] = {
 299         NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, TX53_SDHC_PAD_CTRL),
 300         NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, TX53_SDHC_PAD_CTRL),
 301         NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, TX53_SDHC_PAD_CTRL),
 302         NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, TX53_SDHC_PAD_CTRL),
 303         NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, TX53_SDHC_PAD_CTRL),
 304         NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, TX53_SDHC_PAD_CTRL),
 305         /* SD2 CD */
 306         NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, MX53_GPIO_PAD_CTRL),
 307 };
 308
 309 static struct {
 310         const iomux_v3_cfg_t *pads;
 311         int count;
 312 } mmc_pad_config[] = {
 313         { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
 314         { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
 315 };
 316
 317 int board_mmc_init(bd_t *bis)
 318 {
 319         int i;
 320
 321         for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
 322 //              struct mmc *mmc;
 323
 324                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 325                         break;
 326                 mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
 327                                                 mmc_pad_config[i].count);
 328                 fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
 329 #if 0
 330                 mmc = find_mmc_device(i);
 331                 if (mmc == NULL)
 332                         continue;
 333                 if (board_mmc_getcd(mmc) > 0)
 334                         mmc_init(mmc);
 335 #endif
 336         }
 337         return 0;
 338 }
 339 #endif /* CONFIG_CMD_MMC */
 340
 341 #ifdef CONFIG_FEC_MXC
 342
 343 #ifndef ETH_ALEN
 344 #define ETH_ALEN 6
 345 #endif
 346
 347 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 348 {
 349         int i;
 350         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 351         struct fuse_bank *bank = &iim->bank[1];
 352         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 353
 354         if (dev_id > 0)
 355                 return;
 356
 357         for (i = 0; i < ETH_ALEN; i++)
 358                 mac[i] = readl(&fuse->mac_addr[i]);
 359 }
 360
 361 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 362                         PAD_CTL_SRE_FAST)
 363 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 364 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 365
 366 int board_eth_init(bd_t *bis)
 367 {
 368         int ret;
 369         unsigned char mac[ETH_ALEN];
 370         char mac_str[ETH_ALEN * 3] = "";
 371
 372         /* delay at least 21ms for the PHY internal POR signal to deassert */
 373         udelay(22000);
 374         /* Deassert RESET to the external phy */
 375         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 376
 377         ret = cpu_eth_init(bis);
 378         if (ret) {
 379                 printf("cpu_eth_init() failed: %d\n", ret);
 380         }
 381
 382         imx_get_mac_from_fuse(0, mac);
 383         snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
 384                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 385         setenv("ethaddr", mac_str);
 386
 387         return ret;
 388 }
 389 #endif /* CONFIG_FEC_MXC */
 390
 391 enum {
 392         LED_STATE_INIT = -1,
 393         LED_STATE_OFF,
 394         LED_STATE_ON,
 395 };
 396
 397 void show_activity(int arg)
 398 {
 399         static int led_state = LED_STATE_INIT;
 400         static ulong last;
 401
 402         if (led_state == LED_STATE_INIT) {
 403                 last = get_timer(0);
 404                 gpio_set_value(TX53_LED_GPIO, 1);
 405                 led_state = LED_STATE_ON;
 406         } else {
 407                 if (get_timer(last) > CONFIG_SYS_HZ) {
 408                         last = get_timer(0);
 409                         if (led_state == LED_STATE_ON) {
 410                                 gpio_set_value(TX53_LED_GPIO, 0);
 411                         } else {
 412                                 gpio_set_value(TX53_LED_GPIO, 1);
 413                         }
 414                         led_state = 1 - led_state;
 415                 }
 416         }
 417 }
 418
 419 static const iomux_v3_cfg_t stk5_pads[] = {
 420         /* SW controlled LED on STK5 baseboard */
 421         MX53_PAD_EIM_A18__GPIO2_20,
 422
 423         /* I2C bus on DIMM pins 40/41 */
 424         NEW_PAD_CTRL(MX53_PAD_GPIO_6__I2C3_SDA, MX53_GPIO_PAD_CTRL),
 425         NEW_PAD_CTRL(MX53_PAD_GPIO_3__I2C3_SCL, MX53_GPIO_PAD_CTRL),
 426
 427         /* TSC200x PEN IRQ */
 428         NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, MX53_GPIO_PAD_CTRL),
 429
 430         /* EDT-FT5x06 Polytouch panel */
 431         NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, MX53_GPIO_PAD_CTRL), /* IRQ */
 432         NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, MX53_GPIO_PAD_CTRL), /* RESET */
 433         NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, MX53_GPIO_PAD_CTRL), /* WAKE */
 434
 435         /* USBH1 */
 436         NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, MX53_GPIO_PAD_CTRL), /* VBUSEN */
 437         NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, MX53_GPIO_PAD_CTRL), /* OC */
 438         /* USBOTG */
 439         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 440         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 441
 442         /* DS1339 Interrupt */
 443         NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, MX53_GPIO_PAD_CTRL),
 444 };
 445
 446 static const struct gpio stk5_gpios[] = {
 447         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 448
 449         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 450         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 451         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 452         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 453 };
 454
 455 #ifdef CONFIG_LCD
 456 static u16 tx53_cmap[256];
 457 vidinfo_t panel_info = {
 458         /* set to max. size supported by SoC */
 459         .vl_col = 1600,
 460         .vl_row = 1200,
 461
 462         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 463         .cmap = tx53_cmap,
 464 };
 465
 466 static struct fb_videomode tx53_fb_mode = {
 467         /* Standard VGA timing */
 468         .name           = "VGA",
 469         .refresh        = 60,
 470         .xres           = 640,
 471         .yres           = 480,
 472         .pixclock       = KHZ2PICOS(25175),
 473         .left_margin    = 48,
 474         .hsync_len      = 96,
 475         .right_margin   = 16,
 476         .upper_margin   = 31,
 477         .vsync_len      = 2,
 478         .lower_margin   = 12,
 479         .sync           = FB_SYNC_CLK_LAT_FALL,
 480         .vmode          = FB_VMODE_NONINTERLACED,
 481 };
 482
 483 void *lcd_base;                 /* Start of framebuffer memory  */
 484 void *lcd_console_address;      /* Start of console buffer      */
 485
 486 int lcd_line_length;
 487 int lcd_color_fg;
 488 int lcd_color_bg;
 489
 490 short console_col;
 491 short console_row;
 492
 493 void lcd_initcolregs(void)
 494 {
 495 }
 496
 497 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
 498 {
 499 }
 500
 501 void lcd_enable(void)
 502 {
 503         /* HACK ALERT:
 504          * global variable from common/lcd.c
 505          * Set to 0 here to prevent messages from going to LCD
 506          * rather than serial console
 507          */
 508         lcd_is_enabled = 0;
 509 }
 510
 511 void lcd_disable(void)
 512 {
 513 }
 514
 515 void lcd_panel_disable(void)
 516 {
 517 }
 518
 519 static int lcd_enabled = 1;
 520
 521 static inline int tx53_load_splashimage(void)
 522 {
 523         int ret = 0;
 524 #if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_LCD)
 525         int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]);
 526         cmd_tbl_t *cmd = find_cmd("nand");
 527         char *loadaddr = getenv("splashimage");
 528         char *argv[] = {
 529                 "nand",
 530                 "read",
 531                 loadaddr,
 532                 "logo",
 533         };
 534         const int argc = ARRAY_SIZE(argv);
 535         unsigned long la;
 536
 537         if (!loadaddr)
 538                 return 0;
 539
 540         if (tstc() || (wrsr & WRSR_TOUT))
 541                 return -ENODEV;
 542
 543         if (!cmd)
 544                 return -EINVAL;
 545
 546         la = simple_strtoul(loadaddr, NULL, 16);
 547         if (la == 0)
 548                 return -EINVAL;
 549
 550         /* clear BMP header in memory */
 551         memset((void *)la, 0, 64);
 552
 553         ret = do_nand(cmd, 0, argc, argv);
 554         if (ret) {
 555                 printf("Failed to load logo: %d\n", ret);
 556                 return ret;
 557         }
 558 #endif
 559         return ret;
 560 }
 561
 562 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 563         /* LCD RESET */
 564         NEW_PAD_CTRL(MX53_PAD_EIM_D29__GPIO3_29, MX53_GPIO_PAD_CTRL),
 565         /* LCD POWER_ENABLE */
 566         NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, MX53_GPIO_PAD_CTRL),
 567         /* LCD Backlight (PWM) */
 568         NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, MX53_GPIO_PAD_CTRL),
 569
 570         /* Display */
 571         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 572         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 573         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 574         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 575         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 576         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 577         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 578         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 579         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 580         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 581         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 582         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 583         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 584         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 585         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 586         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 587         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 588         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 589         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 590         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 591         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 592         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 593         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 594         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 595         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 596         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 597         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 598         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 599
 600         /* LVDS option */
 601         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 602         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 603         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 604         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 605         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 606         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 607         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 608         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 609         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 610         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 611 };
 612
 613 static const struct gpio stk5_lcd_gpios[] = {
 614         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 615         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 616         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 617 };
 618
 619 void lcd_ctrl_init(void *lcdbase)
 620 {
 621         int color_depth = 24;
 622         char *vm;
 623         unsigned long val;
 624         int refresh = 60;
 625         struct fb_videomode *p = &tx53_fb_mode;
 626         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 627         int pix_fmt = 0;
 628
 629         if (!lcd_enabled) {
 630                 printf("LCD disabled\n");
 631                 return;
 632         }
 633
 634         if (tstc() || (wrsr & WRSR_TOUT)) {
 635                 printf("%s@%d: Disabling LCD\n", __func__, __LINE__);
 636                 lcd_enabled = 0;
 637                 return;
 638         }
 639
 640         vm = getenv("video_mode");
 641         if (vm == NULL) {
 642                 printf("%s@%d: Disabling LCD\n", __func__, __LINE__);
 643                 lcd_enabled = 0;
 644                 return;
 645         }
 646         while (*vm != '\0') {
 647                 if (*vm >= '0' && *vm <= '9') {
 648                         char *end;
 649
 650                         val = simple_strtoul(vm, &end, 0);
 651                         if (end > vm) {
 652                                 if (!xres_set) {
 653                                         if (val > panel_info.vl_col)
 654                                                 val = panel_info.vl_col;
 655                                         p->xres = val;
 656                                         panel_info.vl_col = val;
 657                                         xres_set = 1;
 658                                 } else if (!yres_set) {
 659                                         if (val > panel_info.vl_row)
 660                                                 val = panel_info.vl_row;
 661                                         p->yres = val;
 662                                         panel_info.vl_row = val;
 663                                         yres_set = 1;
 664                                 } else if (!bpp_set) {
 665                                         switch (val) {
 666                                         case 24:
 667                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 668                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 669                                                 /* fallthru */
 670                                         case 16:
 671                                         case 8:
 672                                                 color_depth = val;
 673                                                 break;
 674
 675                                         case 18:
 676                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 677                                                         color_depth = val;
 678                                                         break;
 679                                                 }
 680                                                 /* fallthru */
 681                                         default:
 682                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 683                                                         end - vm, vm, color_depth);
 684                                         }
 685                                         bpp_set = 1;
 686                                 } else if (!refresh_set) {
 687                                         refresh = val;
 688                                         refresh_set = 1;
 689                                 }
 690                         }
 691                         vm = end;
 692                 }
 693                 switch (*vm) {
 694                 case '@':
 695                         bpp_set = 1;
 696                         /* fallthru */
 697                 case '-':
 698                         yres_set = 1;
 699                         /* fallthru */
 700                 case 'x':
 701                         xres_set = 1;
 702                         /* fallthru */
 703                 case 'M':
 704                 case 'R':
 705                         vm++;
 706                         break;
 707
 708                 default:
 709                         if (!pix_fmt) {
 710                                 char *tmp;
 711
 712                                 if (strncmp(vm, "LVDS", 4) == 0)
 713                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 714                                 else
 715                                         pix_fmt = IPU_PIX_FMT_RGB24;
 716                                 tmp = strchr(vm, ':');
 717                                 if (tmp)
 718                                         vm = tmp;
 719                         }
 720                         if (*vm != '\0')
 721                                 vm++;
 722                 }
 723         }
 724         switch (color_depth) {
 725         case 8:
 726                 panel_info.vl_bpix = 3;
 727                 break;
 728
 729         case 16:
 730                 panel_info.vl_bpix = 4;
 731                 break;
 732
 733         case 18:
 734         case 24:
 735                 panel_info.vl_bpix = 5;
 736         }
 737         lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col;
 738
 739         p->pixclock = KHZ2PICOS(refresh *
 740                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 741                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 742                 / 1000);
 743         debug("Pixel clock set to %lu.%03lu MHz\n",
 744                 PICOS2KHZ(p->pixclock) / 1000,
 745                 PICOS2KHZ(p->pixclock) % 1000);
 746
 747         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 748         mxc_iomux_v3_setup_multiple_pads(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
 749
 750         debug("Initializing FB driver\n");
 751         if (!pix_fmt)
 752                 pix_fmt = IPU_PIX_FMT_RGB24;
 753         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 754                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 755         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 756                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 757         }
 758         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 759                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 760                 /* enable LDB & DI0 clock */
 761                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
 762                         &ccm_regs->CCGR6);
 763         }
 764
 765         mx5_fb_init(p, 0, pix_fmt, 1 << panel_info.vl_bpix);
 766
 767         if (tx53_load_splashimage() == 0) {
 768                 debug("Initializing LCD controller\n");
 769                 video_hw_init();
 770         } else {
 771                 debug("Skipping initialization of LCD controller\n");
 772         }
 773 }
 774
 775 ulong calc_fbsize(void)
 776 {
 777         return panel_info.vl_row * panel_info.vl_col * 2 *
 778                 NBITS(panel_info.vl_bpix) / 8;
 779 }
 780 #else
 781 #define lcd_enabled 0
 782 #endif /* CONFIG_LCD */
 783
 784 static void stk5_board_init(void)
 785 {
 786         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 787         mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 788 }
 789
 790 static void stk5v3_board_init(void)
 791 {
 792         stk5_board_init();
 793 }
 794
 795 static void stk5v5_board_init(void)
 796 {
 797         stk5_board_init();
 798 }
 799
 800 static void tx53_move_fdt(void)
 801 {
 802         const void *fdt = gd->fdt_blob;
 803         unsigned long fdt_addr = getenv_ulong("fdtaddr", 16, 0);
 804
 805         if (!fdt || !fdt_addr) {
 806                 printf("fdt=%p fdt_addr=%08lx\n", fdt, fdt_addr);
 807                 return;
 808         }
 809
 810         if (fdt_check_header(fdt)) {
 811                 printf("ERROR: No valid FDT found at %p\n", fdt);
 812                 return;
 813         }
 814
 815         memmove((void *)fdt_addr, fdt, fdt_totalsize(fdt));
 816         set_working_fdt_addr((void *)fdt_addr);
 817 }
 818
 819 static void tx53_set_cpu_clock(void)
 820 {
 821         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 822         int ret;
 823
 824         if (tstc() || (wrsr & WRSR_TOUT))
 825                 return;
 826
 827         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 828                 return;
 829
 830         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
 831         if (ret != 0) {
 832                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 833                 return;
 834         }
 835         printf("CPU clock set to %u.%03u MHz\n",
 836                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
 837                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
 838 }
 839
 840 int board_late_init(void)
 841 {
 842         const char *baseboard;
 843
 844         tx53_set_cpu_clock();
 845         tx53_move_fdt();
 846
 847         baseboard = getenv("baseboard");
 848         if (!baseboard)
 849                 return 0;
 850
 851         if (strncmp(baseboard, "stk5", 4) == 0) {
 852                 printf("Baseboard: %s\n", baseboard);
 853                 if ((strlen(baseboard) == 4) ||
 854                         strcmp(baseboard, "stk5-v3") == 0) {
 855                         stk5v3_board_init();
 856                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 857                         stk5v5_board_init();
 858                 } else {
 859                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 860                                 baseboard + 4);
 861                 }
 862         } else {
 863                 printf("WARNING: Unsupported baseboard: '%s'\n",
 864                         baseboard);
 865                 return -EINVAL;
 866         }
 867         if (lcd_enabled) {
 868                 printf("Switching LCD on\n");
 869                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 870                 udelay(100);
 871                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 872                 udelay(300000);
 873                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
 874         }
 875
 876         return 0;
 877 }
 878
 879 int checkboard(void)
 880 {
 881         print_cpuinfo();
 882
 883         printf("Board: Ka-Ro TX53-xx3%s\n",
 884                 TX53_MOD_SUFFIX);
 885
 886         return 0;
 887 }
 888
 889 #if defined(CONFIG_OF_BOARD_SETUP)
 890 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 891 #include <jffs2/jffs2.h>
 892 #include <mtd_node.h>
 893 struct node_info nodes[] = {
 894         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
 895 };
 896
 897 #else
 898 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 899 #endif
 900
 901 static const char *tx53_touchpanels[] = {
 902         "ti,tsc2007",
 903         "edt,edt-ft5x06",
 904 };
 905
 906 static void fdt_del_tp_node(void *blob, const char *name)
 907 {
 908         int offs = fdt_node_offset_by_compatible(blob, -1, name);
 909         uint32_t ph1 = 0, ph2 = 0;
 910         const uint32_t *prop;
 911
 912         if (offs < 0) {
 913                 debug("node '%s' not found: %d\n", name, offs);
 914                 return;
 915         }
 916
 917         prop = fdt_getprop(blob, offs, "reset-switch", NULL);
 918         if (prop)
 919                 ph1 = be32_to_cpu(*prop);
 920
 921         prop = fdt_getprop(blob, offs, "wake-switch", NULL);
 922         if (prop)
 923                 ph2 = be32_to_cpu(*prop);
 924
 925         debug("Removing node '%s' from DT\n", name);
 926         fdt_del_node(blob, offs);
 927
 928         if (ph1) {
 929                 offs = fdt_node_offset_by_phandle(blob, ph1);
 930                 if (offs > 0) {
 931                         debug("Removing node @ %08x\n", offs);
 932                         fdt_del_node(blob, offs);
 933                 }
 934         }
 935         if (ph2) {
 936                 offs = fdt_node_offset_by_phandle(blob, ph2);
 937                 if (offs > 0) {
 938                         debug("Removing node @ %08x\n", offs);
 939                         fdt_del_node(blob, offs);
 940                 }
 941         }
 942 }
 943
 944 static void tx53_fixup_touchpanel(void *blob)
 945 {
 946         int i;
 947         const char *model = getenv("touchpanel");
 948
 949         for (i = 0; i < ARRAY_SIZE(tx53_touchpanels); i++) {
 950                 const char *tp = tx53_touchpanels[i];
 951
 952                 if (model != NULL && strcmp(model, tp) == 0)
 953                         continue;
 954
 955                 tp = strchr(tp, ',');
 956                 if (tp != NULL && *tp != '\0' && strcmp(model, tp + 1) == 0)
 957                         continue;
 958
 959                 fdt_del_tp_node(blob, tx53_touchpanels[i]);
 960         }
 961 }
 962
 963 static void tx53_fixup_usb_otg(void *blob)
 964 {
 965         const char *otg_mode = getenv("otg_mode");
 966         int usbphy = 2;
 967
 968         if (otg_mode == NULL || strcmp(otg_mode, "host") != 0) {
 969                 debug("Removing node %s from DT\n", "usbh1");
 970                 fdt_del_node_and_alias(blob, "usbh1");
 971                 usbphy--;
 972         }
 973         if (otg_mode == NULL || strcmp(otg_mode, "device") != 0) {
 974                 debug("Removing node %s from DT\n", "usbotg");
 975                 fdt_del_node_and_alias(blob, "usbotg");
 976                 usbphy--;
 977         }
 978         if (!usbphy) {
 979                 debug("Removing node %s from DT\n", "usbphy");
 980                 fdt_del_node_and_alias(blob, "usbphy");
 981         }
 982 }
 983
 984 static void tx53_fdt_del_prop(void *blob, const char *compat, phys_addr_t offs,
 985                         const char *prop)
 986 {
 987         int ret;
 988         int offset;
 989         const uint32_t *phandle;
 990         uint32_t ph = 0;
 991
 992         offset = fdt_node_offset_by_compat_reg(blob, compat, offs);
 993         if (offset <= 0)
 994                 return;
 995
 996         phandle = fdt_getprop(blob, offset, "transceiver-switch", NULL);
 997         if (phandle) {
 998                 ph = be32_to_cpu(*phandle);
 999                 printf("phandle=%08x\n", ph);
1000         }
1001
1002         debug("Removing property '%s' from node %s@%08lx\n", prop, compat, offs);
1003         ret = fdt_delprop(blob, offset, prop);
1004         if (ret)
1005                 printf("Failed to remove property '%s' from node %s@%08lx\n",
1006                         prop, compat, offs);
1007
1008         if (!ph)
1009                 return;
1010
1011         offset = fdt_node_offset_by_phandle(blob, ph);
1012         printf("Node offset[%x]=%08x\n", ph, offset);
1013         if (offset <= 0)
1014                 return;
1015
1016         debug("Removing node @ %08x\n", offset);
1017         fdt_del_node(blob, offset);
1018 }
1019
1020 static void tx53_fixup_flexcan(void *blob)
1021 {
1022         const char *baseboard = getenv("baseboard");
1023
1024         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1025                 return;
1026
1027         tx53_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch");
1028         tx53_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch");
1029 }
1030
1031 void ft_board_setup(void *blob, bd_t *bd)
1032 {
1033         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1034         fdt_fixup_ethernet(blob);
1035
1036         tx53_fixup_touchpanel(blob);
1037         tx53_fixup_usb_otg(blob);
1038         tx53_fixup_flexcan(blob);
1039 }
1040 #endif