board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <lcd.h>
  24 #include <netdev.h>
  25 #include <mmc.h>
  26 #include <fsl_esdhc.h>
  27 #include <video_fb.h>
  28 #include <ipu.h>
  29 #include <mxcfb.h>
  30 #include <linux/fb.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/iomux-mx53.h>
  34 #include <asm/arch/clock.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40
  41 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  42 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  43 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  44 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  45
  46 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  47 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  48 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  49
  50 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  55                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  56
  57 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  58                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  59
  60 static iomux_v3_cfg_t tx53_pads[] = {
  61         /* NAND flash pads are set up in lowlevel_init.S */
  62
  63         /* UART pads */
  64 #if CONFIG_MXC_UART_BASE == UART1_BASE
  65         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  66         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  67         MX53_PAD_PATA_IORDY__UART1_RTS,
  68         MX53_PAD_PATA_RESET_B__UART1_CTS,
  69 #endif
  70 #if CONFIG_MXC_UART_BASE == UART2_BASE
  71         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  72         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  73         MX53_PAD_PATA_DIOR__UART2_RTS,
  74         MX53_PAD_PATA_INTRQ__UART2_CTS,
  75 #endif
  76 #if CONFIG_MXC_UART_BASE == UART3_BASE
  77         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  78         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  79         MX53_PAD_PATA_DA_2__UART3_RTS,
  80         MX53_PAD_PATA_DA_1__UART3_CTS,
  81 #endif
  82         /* internal I2C */
  83         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  84         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  85
  86         /* FEC PHY GPIO functions */
  87         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  88         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  89         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  90
  91         /* FEC functions */
  92         MX53_PAD_FEC_MDC__FEC_MDC,
  93         MX53_PAD_FEC_MDIO__FEC_MDIO,
  94         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  95         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  96         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  97         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  98         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  99         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 100         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 101         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 102 };
 103
 104 static const struct gpio tx53_gpios[] = {
 105         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 106         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 107         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 108         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 109 };
 110
 111 /*
 112  * Functions
 113  */
 114 /* placed in section '.data' to prevent overwriting relocation info
 115  * overlayed with bss
 116  */
 117 static u32 wrsr __attribute__((section(".data")));
 118
 119 #define WRSR_POR        (1 << 4)
 120 #define WRSR_TOUT       (1 << 1)
 121 #define WRSR_SFTW       (1 << 0)
 122
 123 static void print_reset_cause(void)
 124 {
 125         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 126         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 127         u32 srsr;
 128         char *dlm = "";
 129
 130         printf("Reset cause: ");
 131
 132         srsr = readl(&src_regs->srsr);
 133         wrsr = readw(wdt_base + 4);
 134
 135         if (wrsr & WRSR_POR) {
 136                 printf("%sPOR", dlm);
 137                 dlm = " | ";
 138         }
 139         if (srsr & 0x00004) {
 140                 printf("%sCSU", dlm);
 141                 dlm = " | ";
 142         }
 143         if (srsr & 0x00008) {
 144                 printf("%sIPP USER", dlm);
 145                 dlm = " | ";
 146         }
 147         if (srsr & 0x00010) {
 148                 if (wrsr & WRSR_SFTW) {
 149                         printf("%sSOFT", dlm);
 150                         dlm = " | ";
 151                 }
 152                 if (wrsr & WRSR_TOUT) {
 153                         printf("%sWDOG", dlm);
 154                         dlm = " | ";
 155                 }
 156         }
 157         if (srsr & 0x00020) {
 158                 printf("%sJTAG HIGH-Z", dlm);
 159                 dlm = " | ";
 160         }
 161         if (srsr & 0x00040) {
 162                 printf("%sJTAG SW", dlm);
 163                 dlm = " | ";
 164         }
 165         if (srsr & 0x10000) {
 166                 printf("%sWARM BOOT", dlm);
 167                 dlm = " | ";
 168         }
 169         if (dlm[0] == '\0')
 170                 printf("unknown");
 171
 172         printf("\n");
 173 }
 174
 175 static void tx53_print_cpuinfo(void)
 176 {
 177         u32 cpurev;
 178
 179         cpurev = get_cpu_rev();
 180
 181         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 182                 (cpurev & 0x000F0) >> 4,
 183                 (cpurev & 0x0000F) >> 0,
 184                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 185
 186         print_reset_cause();
 187 }
 188
 189 int board_early_init_f(void)
 190 {
 191         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 192
 193         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 194         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 195
 196         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 197         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 198
 199         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 200         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 201         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 202         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 203         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 204
 205         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 206         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 207
 208         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 209         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 210         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 211         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 212         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 213
 214         writel(0xffcf0fff, &ccm_regs->CCGR0);
 215         writel(0x000fffc3, &ccm_regs->CCGR1);
 216         writel(0x033c0000, &ccm_regs->CCGR2);
 217         writel(0x000000ff, &ccm_regs->CCGR3);
 218         writel(0x00000000, &ccm_regs->CCGR4);
 219         writel(0x00fff033, &ccm_regs->CCGR5);
 220         writel(0x0f00030f, &ccm_regs->CCGR6);
 221         writel(0xfff00000, &ccm_regs->CCGR7);
 222         writel(0x00000000, &ccm_regs->cmeor);
 223
 224         return 0;
 225 }
 226
 227 int board_init(void)
 228 {
 229         /* Address of boot parameters */
 230         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 231         return 0;
 232 }
 233
 234 int dram_init(void)
 235 {
 236         int ret;
 237
 238         /* dram_init must store complete ramsize in gd->ram_size */
 239         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 240                                 PHYS_SDRAM_1_SIZE);
 241
 242         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 243                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 244         if (ret)
 245                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 246                         CONFIG_SYS_SDRAM_CLK, ret);
 247         else
 248                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 249                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 250                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 251                         CONFIG_SYS_SDRAM_CLK);
 252         return ret;
 253 }
 254
 255 void dram_init_banksize(void)
 256 {
 257         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 258         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 259                         PHYS_SDRAM_1_SIZE);
 260 #if CONFIG_NR_DRAM_BANKS > 1
 261         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 262         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 263                         PHYS_SDRAM_2_SIZE);
 264 #endif
 265 }
 266
 267 #ifdef  CONFIG_CMD_MMC
 268 static const iomux_v3_cfg_t mmc0_pads[] = {
 269         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 270         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 271         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 272         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 273         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 274         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 275         /* SD1 CD */
 276         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 277 };
 278
 279 static const iomux_v3_cfg_t mmc1_pads[] = {
 280         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 281         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 282         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 283         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 284         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 285         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 286         /* SD2 CD */
 287         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 288 };
 289
 290 static struct tx53_esdhc_cfg {
 291         const iomux_v3_cfg_t *pads;
 292         int num_pads;
 293         struct fsl_esdhc_cfg cfg;
 294         int cd_gpio;
 295 } tx53_esdhc_cfg[] = {
 296         {
 297                 .pads = mmc0_pads,
 298                 .num_pads = ARRAY_SIZE(mmc0_pads),
 299                 .cfg = {
 300                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 301                         .max_bus_width = 4,
 302                 },
 303                 .cd_gpio = IMX_GPIO_NR(3, 24),
 304         },
 305         {
 306                 .pads = mmc1_pads,
 307                 .num_pads = ARRAY_SIZE(mmc1_pads),
 308                 .cfg = {
 309                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 310                         .max_bus_width = 4,
 311                 },
 312                 .cd_gpio = IMX_GPIO_NR(3, 25),
 313         },
 314 };
 315
 316 #define to_tx53_esdhc_cfg(p) container_of(p, struct tx53_esdhc_cfg, cfg)
 317
 318 int board_mmc_getcd(struct mmc *mmc)
 319 {
 320         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
 321
 322         if (cfg->cd_gpio < 0)
 323                 return cfg->cd_gpio;
 324
 325         debug("SD card %d is %spresent\n",
 326                 cfg - tx53_esdhc_cfg,
 327                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 328         return !gpio_get_value(cfg->cd_gpio);
 329 }
 330
 331 int board_mmc_init(bd_t *bis)
 332 {
 333         int i;
 334
 335         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
 336                 struct mmc *mmc;
 337                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
 338                 int ret;
 339
 340                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 341                         break;
 342
 343                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 344                                                 cfg->num_pads);
 345                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 346
 347                 fsl_esdhc_initialize(bis, &cfg->cfg);
 348
 349                 ret = gpio_request_one(cfg->cd_gpio,
 350                                 GPIOF_INPUT, "MMC CD");
 351                 if (ret) {
 352                         printf("Error %d requesting GPIO%d_%d\n",
 353                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 354                         continue;
 355                 }
 356
 357                 mmc = find_mmc_device(i);
 358                 if (mmc == NULL)
 359                         continue;
 360                 if (board_mmc_getcd(mmc) > 0)
 361                         mmc_init(mmc);
 362         }
 363         return 0;
 364 }
 365 #endif /* CONFIG_CMD_MMC */
 366
 367 #ifdef CONFIG_FEC_MXC
 368
 369 #ifndef ETH_ALEN
 370 #define ETH_ALEN 6
 371 #endif
 372
 373 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 374 {
 375         int i;
 376         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 377         struct fuse_bank *bank = &iim->bank[1];
 378         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 379
 380         if (dev_id > 0)
 381                 return;
 382
 383         for (i = 0; i < ETH_ALEN; i++)
 384                 mac[i] = readl(&fuse->mac_addr[i]);
 385 }
 386
 387 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 388                         PAD_CTL_SRE_FAST)
 389 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 390 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 391
 392 int board_eth_init(bd_t *bis)
 393 {
 394         int ret;
 395
 396         /* delay at least 21ms for the PHY internal POR signal to deassert */
 397         udelay(22000);
 398
 399         /* Deassert RESET to the external phy */
 400         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 401
 402         ret = cpu_eth_init(bis);
 403         if (ret)
 404                 printf("cpu_eth_init() failed: %d\n", ret);
 405         return ret;
 406 }
 407 #endif /* CONFIG_FEC_MXC */
 408
 409 enum {
 410         LED_STATE_INIT = -1,
 411         LED_STATE_OFF,
 412         LED_STATE_ON,
 413 };
 414
 415 void show_activity(int arg)
 416 {
 417         static int led_state = LED_STATE_INIT;
 418         static ulong last;
 419
 420         if (led_state == LED_STATE_INIT) {
 421                 last = get_timer(0);
 422                 gpio_set_value(TX53_LED_GPIO, 1);
 423                 led_state = LED_STATE_ON;
 424         } else {
 425                 if (get_timer(last) > CONFIG_SYS_HZ) {
 426                         last = get_timer(0);
 427                         if (led_state == LED_STATE_ON) {
 428                                 gpio_set_value(TX53_LED_GPIO, 0);
 429                         } else {
 430                                 gpio_set_value(TX53_LED_GPIO, 1);
 431                         }
 432                         led_state = 1 - led_state;
 433                 }
 434         }
 435 }
 436
 437 static const iomux_v3_cfg_t stk5_pads[] = {
 438         /* SW controlled LED on STK5 baseboard */
 439         MX53_PAD_EIM_A18__GPIO2_20,
 440
 441         /* I2C bus on DIMM pins 40/41 */
 442         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 443         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 444
 445         /* TSC200x PEN IRQ */
 446         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 447
 448         /* EDT-FT5x06 Polytouch panel */
 449         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 450         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 451         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 452
 453         /* USBH1 */
 454         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 455         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 456         /* USBOTG */
 457         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 458         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 459
 460         /* DS1339 Interrupt */
 461         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 462 };
 463
 464 static const struct gpio stk5_gpios[] = {
 465         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 466
 467         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 468         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 469         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 470         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 471 };
 472
 473 #ifdef CONFIG_LCD
 474 vidinfo_t panel_info = {
 475         /* set to max. size supported by SoC */
 476         .vl_col = 1600,
 477         .vl_row = 1200,
 478
 479         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 480 };
 481
 482 static struct fb_videomode tx53_fb_modes[] = {
 483         {
 484                 /* Standard VGA timing */
 485                 .name           = "VGA",
 486                 .refresh        = 60,
 487                 .xres           = 640,
 488                 .yres           = 480,
 489                 .pixclock       = KHZ2PICOS(25175),
 490                 .left_margin    = 48,
 491                 .hsync_len      = 96,
 492                 .right_margin   = 16,
 493                 .upper_margin   = 31,
 494                 .vsync_len      = 2,
 495                 .lower_margin   = 12,
 496                 .sync           = FB_SYNC_CLK_LAT_FALL,
 497         },
 498         {
 499                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 500                  * DE high active, 115.2 mm x 86.4 mm display area
 501                  * VGA compatible timing
 502                  */
 503                 .name           = "ETV570",
 504                 .refresh        = 60,
 505                 .xres           = 640,
 506                 .yres           = 480,
 507                 .pixclock       = KHZ2PICOS(25175),
 508                 .left_margin    = 114,
 509                 .hsync_len      = 30,
 510                 .right_margin   = 16,
 511                 .upper_margin   = 32,
 512                 .vsync_len      = 3,
 513                 .lower_margin   = 10,
 514                 .sync           = FB_SYNC_CLK_LAT_FALL,
 515         },
 516         {
 517                 /* Emerging ET0350G0DH6 320 x 240 display.
 518                  * 70.08 mm x 52.56 mm display area.
 519                  */
 520                 .name           = "ET0350",
 521                 .refresh        = 60,
 522                 .xres           = 320,
 523                 .yres           = 240,
 524                 .pixclock       = KHZ2PICOS(6500),
 525                 .left_margin    = 68 - 34,
 526                 .hsync_len      = 34,
 527                 .right_margin   = 20,
 528                 .upper_margin   = 18 - 3,
 529                 .vsync_len      = 3,
 530                 .lower_margin   = 4,
 531                 .sync           = FB_SYNC_CLK_LAT_FALL,
 532         },
 533         {
 534                 /* Emerging ET0430G0DH6 480 x 272 display.
 535                  * 95.04 mm x 53.856 mm display area.
 536                  */
 537                 .name           = "ET0430",
 538                 .refresh        = 60,
 539                 .xres           = 480,
 540                 .yres           = 272,
 541                 .pixclock       = KHZ2PICOS(9000),
 542                 .left_margin    = 2,
 543                 .hsync_len      = 41,
 544                 .right_margin   = 2,
 545                 .upper_margin   = 2,
 546                 .vsync_len      = 10,
 547                 .lower_margin   = 2,
 548                 .sync           = FB_SYNC_CLK_LAT_FALL,
 549         },
 550         {
 551                 /* Emerging ET0500G0DH6 800 x 480 display.
 552                  * 109.6 mm x 66.4 mm display area.
 553                  */
 554                 .name           = "ET0500",
 555                 .refresh        = 60,
 556                 .xres           = 800,
 557                 .yres           = 480,
 558                 .pixclock       = KHZ2PICOS(33260),
 559                 .left_margin    = 216 - 128,
 560                 .hsync_len      = 128,
 561                 .right_margin   = 1056 - 800 - 216,
 562                 .upper_margin   = 35 - 2,
 563                 .vsync_len      = 2,
 564                 .lower_margin   = 525 - 480 - 35,
 565                 .sync           = FB_SYNC_CLK_LAT_FALL,
 566         },
 567         {
 568                 /* Emerging ETQ570G0DH6 320 x 240 display.
 569                  * 115.2 mm x 86.4 mm display area.
 570                  */
 571                 .name           = "ETQ570",
 572                 .refresh        = 60,
 573                 .xres           = 320,
 574                 .yres           = 240,
 575                 .pixclock       = KHZ2PICOS(6400),
 576                 .left_margin    = 38,
 577                 .hsync_len      = 30,
 578                 .right_margin   = 30,
 579                 .upper_margin   = 16, /* 15 according to datasheet */
 580                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 581                 .lower_margin   = 4, /* 4.5 according to datasheet */
 582                 .sync           = FB_SYNC_CLK_LAT_FALL,
 583         },
 584         {
 585                 /* Emerging ET0700G0DH6 800 x 480 display.
 586                  * 152.4 mm x 91.44 mm display area.
 587                  */
 588                 .name           = "ET0700",
 589                 .refresh        = 60,
 590                 .xres           = 800,
 591                 .yres           = 480,
 592                 .pixclock       = KHZ2PICOS(33260),
 593                 .left_margin    = 216 - 128,
 594                 .hsync_len      = 128,
 595                 .right_margin   = 1056 - 800 - 216,
 596                 .upper_margin   = 35 - 2,
 597                 .vsync_len      = 2,
 598                 .lower_margin   = 525 - 480 - 35,
 599                 .sync           = FB_SYNC_CLK_LAT_FALL,
 600         },
 601         {
 602                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 603                 .refresh        = 60,
 604                 .left_margin    = 48,
 605                 .hsync_len      = 96,
 606                 .right_margin   = 16,
 607                 .upper_margin   = 31,
 608                 .vsync_len      = 2,
 609                 .lower_margin   = 12,
 610                 .sync           = FB_SYNC_CLK_LAT_FALL,
 611         },
 612 };
 613
 614 static int lcd_enabled = 1;
 615
 616 void lcd_enable(void)
 617 {
 618         /* HACK ALERT:
 619          * global variable from common/lcd.c
 620          * Set to 0 here to prevent messages from going to LCD
 621          * rather than serial console
 622          */
 623         lcd_is_enabled = 0;
 624
 625         if (lcd_enabled) {
 626                 karo_load_splashimage(1);
 627
 628                 debug("Switching LCD on\n");
 629                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 630                 udelay(100);
 631                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 632                 udelay(300000);
 633                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
 634         }
 635 }
 636
 637 void lcd_disable(void)
 638 {
 639         if (lcd_enabled) {
 640                 printf("Disabling LCD\n");
 641                 ipuv3_fb_shutdown();
 642         }
 643 }
 644
 645 void lcd_panel_disable(void)
 646 {
 647         if (lcd_enabled) {
 648                 debug("Switching LCD off\n");
 649                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1);
 650                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 651                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 652         }
 653 }
 654
 655 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 656         /* LCD RESET */
 657         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 658         /* LCD POWER_ENABLE */
 659         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 660         /* LCD Backlight (PWM) */
 661         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 662
 663         /* Display */
 664         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 665         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 666         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 667         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 668         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 669         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 670         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 671         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 672         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 673         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 674         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 675         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 676         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 677         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 678         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 679         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 680         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 681         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 682         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 683         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 684         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 685         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 686         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 687         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 688         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 689         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 690         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 691         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 692
 693         /* LVDS option */
 694         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 695         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 696         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 697         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 698         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 699         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 700         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 701         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 702         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 703         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 704 };
 705
 706 static const struct gpio stk5_lcd_gpios[] = {
 707         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 708         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 709         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 710 };
 711
 712 void lcd_ctrl_init(void *lcdbase)
 713 {
 714         int color_depth = 24;
 715         char *video_mode = getenv("video_mode");
 716         char *vm;
 717         unsigned long val;
 718         int refresh = 60;
 719         struct fb_videomode *p = &tx53_fb_modes[0];
 720         struct fb_videomode fb_mode;
 721         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 722         int pix_fmt = 0;
 723         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 724         unsigned long di_clk_rate = 65000000;
 725
 726         if (!lcd_enabled) {
 727                 debug("LCD disabled\n");
 728                 return;
 729         }
 730
 731         if (tstc() || (wrsr & WRSR_TOUT)) {
 732                 debug("Disabling LCD\n");
 733                 lcd_enabled = 0;
 734                 setenv("splashimage", NULL);
 735                 return;
 736         }
 737
 738         karo_fdt_move_fdt();
 739
 740         vm = karo_fdt_set_display(video_mode, "/soc", "/soc/aips/ldb");
 741         if (vm == NULL) {
 742                 debug("Disabling LCD\n");
 743                 lcd_enabled = 0;
 744                 return;
 745         }
 746         video_mode = vm;
 747         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 748                 p = &fb_mode;
 749                 debug("Using video mode from FDT\n");
 750                 vm += strlen(vm);
 751                 if (fb_mode.xres > panel_info.vl_col ||
 752                         fb_mode.yres > panel_info.vl_row) {
 753                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 754                                 fb_mode.xres, fb_mode.yres,
 755                                 panel_info.vl_col, panel_info.vl_row);
 756                         lcd_enabled = 0;
 757                         return;
 758                 }
 759         }
 760         if (p->name != NULL)
 761                 debug("Trying compiled-in video modes\n");
 762         while (p->name != NULL) {
 763                 if (strcmp(p->name, vm) == 0) {
 764                         debug("Using video mode: '%s'\n", p->name);
 765                         vm += strlen(vm);
 766                         break;
 767                 }
 768                 p++;
 769         }
 770         if (*vm != '\0')
 771                 debug("Trying to decode video_mode: '%s'\n", vm);
 772         while (*vm != '\0') {
 773                 if (*vm >= '0' && *vm <= '9') {
 774                         char *end;
 775
 776                         val = simple_strtoul(vm, &end, 0);
 777                         if (end > vm) {
 778                                 if (!xres_set) {
 779                                         if (val > panel_info.vl_col)
 780                                                 val = panel_info.vl_col;
 781                                         p->xres = val;
 782                                         panel_info.vl_col = val;
 783                                         xres_set = 1;
 784                                 } else if (!yres_set) {
 785                                         if (val > panel_info.vl_row)
 786                                                 val = panel_info.vl_row;
 787                                         p->yres = val;
 788                                         panel_info.vl_row = val;
 789                                         yres_set = 1;
 790                                 } else if (!bpp_set) {
 791                                         switch (val) {
 792                                         case 32:
 793                                         case 24:
 794                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 795                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 796                                                 /* fallthru */
 797                                         case 16:
 798                                         case 8:
 799                                                 color_depth = val;
 800                                                 break;
 801
 802                                         case 18:
 803                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 804                                                         color_depth = val;
 805                                                         break;
 806                                                 }
 807                                                 /* fallthru */
 808                                         default:
 809                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 810                                                         end - vm, vm, color_depth);
 811                                         }
 812                                         bpp_set = 1;
 813                                 } else if (!refresh_set) {
 814                                         refresh = val;
 815                                         refresh_set = 1;
 816                                 }
 817                         }
 818                         vm = end;
 819                 }
 820                 switch (*vm) {
 821                 case '@':
 822                         bpp_set = 1;
 823                         /* fallthru */
 824                 case '-':
 825                         yres_set = 1;
 826                         /* fallthru */
 827                 case 'x':
 828                         xres_set = 1;
 829                         /* fallthru */
 830                 case 'M':
 831                 case 'R':
 832                         vm++;
 833                         break;
 834
 835                 default:
 836                         if (!pix_fmt) {
 837                                 char *tmp;
 838
 839                                 if (strncmp(vm, "LVDS", 4) == 0) {
 840                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 841                                         di_clk_parent = DI_PCLK_LDB;
 842                                 } else {
 843                                         pix_fmt = IPU_PIX_FMT_RGB24;
 844                                 }
 845                                 tmp = strchr(vm, ':');
 846                                 if (tmp)
 847                                         vm = tmp;
 848                         }
 849                         if (*vm != '\0')
 850                                 vm++;
 851                 }
 852         }
 853         if (p->xres == 0 || p->yres == 0) {
 854                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 855                 lcd_enabled = 0;
 856                 printf("Supported video modes are:");
 857                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
 858                         printf(" %s", p->name);
 859                 }
 860                 printf("\n");
 861                 return;
 862         }
 863         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 864                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 865                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 866                 lcd_enabled = 0;
 867                 return;
 868         }
 869         panel_info.vl_col = p->xres;
 870         panel_info.vl_row = p->yres;
 871
 872         switch (color_depth) {
 873         case 8:
 874                 panel_info.vl_bpix = LCD_COLOR8;
 875                 break;
 876         case 16:
 877                 panel_info.vl_bpix = LCD_COLOR16;
 878                 break;
 879         default:
 880                 panel_info.vl_bpix = LCD_COLOR24;
 881         }
 882
 883         p->pixclock = KHZ2PICOS(refresh *
 884                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 885                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 886                 / 1000);
 887         debug("Pixel clock set to %lu.%03lu MHz\n",
 888                 PICOS2KHZ(p->pixclock) / 1000,
 889                 PICOS2KHZ(p->pixclock) % 1000);
 890
 891         if (p != &fb_mode) {
 892                 int ret;
 893
 894                 printf("Creating new display-timing node from '%s'\n",
 895                         video_mode);
 896                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
 897                 if (ret)
 898                         printf("Failed to create new display-timing node from '%s': %d\n",
 899                                 video_mode, ret);
 900         }
 901
 902         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 903         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 904                                         ARRAY_SIZE(stk5_lcd_pads));
 905
 906         debug("Initializing FB driver\n");
 907         if (!pix_fmt)
 908                 pix_fmt = IPU_PIX_FMT_RGB24;
 909         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 910                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 911         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 912                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 913         }
 914         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 915                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 916                 /* enable LDB & DI0 clock */
 917                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
 918                         &ccm_regs->CCGR6);
 919         }
 920
 921         if (karo_load_splashimage(0) == 0) {
 922                 int ret;
 923
 924                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
 925
 926                 debug("Initializing LCD controller\n");
 927                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 928                 if (ret) {
 929                         printf("Failed to initialize FB driver: %d\n", ret);
 930                         lcd_enabled = 0;
 931                 }
 932         } else {
 933                 debug("Skipping initialization of LCD controller\n");
 934         }
 935 }
 936 #else
 937 #define lcd_enabled 0
 938 #endif /* CONFIG_LCD */
 939
 940 static void stk5_board_init(void)
 941 {
 942         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 943         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 944 }
 945
 946 static void stk5v3_board_init(void)
 947 {
 948         stk5_board_init();
 949 }
 950
 951 static void stk5v5_board_init(void)
 952 {
 953         stk5_board_init();
 954
 955         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
 956                         "Flexcan Transceiver");
 957         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
 958 }
 959
 960 static void tx53_set_cpu_clock(void)
 961 {
 962         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 963         int ret;
 964
 965         if (tstc() || (wrsr & WRSR_TOUT))
 966                 return;
 967
 968         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 969                 return;
 970
 971         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
 972         if (ret != 0) {
 973                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 974                 return;
 975         }
 976         printf("CPU clock set to %u.%03u MHz\n",
 977                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
 978                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
 979 }
 980
 981 static void tx53_init_mac(void)
 982 {
 983         u8 mac[ETH_ALEN];
 984
 985         imx_get_mac_from_fuse(0, mac);
 986         if (!is_valid_ether_addr(mac)) {
 987                 printf("No valid MAC address programmed\n");
 988                 return;
 989         }
 990
 991         eth_setenv_enetaddr("ethaddr", mac);
 992         printf("MAC addr from fuse: %pM\n", mac);
 993 }
 994
 995 int board_late_init(void)
 996 {
 997         int ret = 0;
 998         const char *baseboard;
 999
1000         tx53_set_cpu_clock();
1001         karo_fdt_move_fdt();
1002
1003         baseboard = getenv("baseboard");
1004         if (!baseboard)
1005                 goto exit;
1006
1007         if (strncmp(baseboard, "stk5", 4) == 0) {
1008                 printf("Baseboard: %s\n", baseboard);
1009                 if ((strlen(baseboard) == 4) ||
1010                         strcmp(baseboard, "stk5-v3") == 0) {
1011                         stk5v3_board_init();
1012                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1013                         stk5v5_board_init();
1014                 } else {
1015                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1016                                 baseboard + 4);
1017                 }
1018         } else {
1019                 printf("WARNING: Unsupported baseboard: '%s'\n",
1020                         baseboard);
1021                 ret = -EINVAL;
1022         }
1023
1024 exit:
1025         tx53_init_mac();
1026         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1027         return ret;
1028 }
1029
1030 int checkboard(void)
1031 {
1032         tx53_print_cpuinfo();
1033
1034         printf("Board: Ka-Ro TX53-xx3%s\n",
1035                 TX53_MOD_SUFFIX);
1036
1037         return 0;
1038 }
1039
1040 #if defined(CONFIG_OF_BOARD_SETUP)
1041 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1042 #include <jffs2/jffs2.h>
1043 #include <mtd_node.h>
1044 struct node_info nodes[] = {
1045         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1046 };
1047
1048 #else
1049 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1050 #endif
1051
1052 #ifdef CONFIG_SYS_TX53_HWREV_2
1053 void tx53_fixup_rtc(void *blob)
1054 {
1055         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1056         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1057 }
1058 #else
1059 static inline void tx53_fixup_rtc(void *blob)
1060 {
1061 }
1062 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1063
1064 void ft_board_setup(void *blob, bd_t *bd)
1065 {
1066         const char *baseboard = getenv("baseboard");
1067         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1068         char *video_mode = getenv("video_mode");
1069
1070         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1071         fdt_fixup_ethernet(blob);
1072
1073         karo_fdt_fixup_touchpanel(blob);
1074         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1075         karo_fdt_fixup_flexcan(blob, stk5_v5);
1076         tx53_fixup_rtc(blob);
1077         video_mode = karo_fdt_set_display(video_mode, "/soc", "/soc/aips/ldb");
1078         karo_fdt_update_fb_mode(blob, video_mode);
1079 }
1080 #endif /* CONFIG_OF_BOARD_SETUP */