board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <errno.h>
  26 #include <libfdt.h>
  27 #include <fdt_support.h>
  28 #include <lcd.h>
  29 #include <netdev.h>
  30 #include <mmc.h>
  31 #include <fsl_esdhc.h>
  32 #include <video_fb.h>
  33 #include <ipu_pixfmt.h>
  34 #include <mx2fb.h>
  35 #include <linux/fb.h>
  36 #include <asm/io.h>
  37 #include <asm/gpio.h>
  38 #include <asm/arch/iomux-mx53.h>
  39 #include <asm/arch/clock.h>
  40 #include <asm/arch/imx-regs.h>
  41 #include <asm/arch/crm_regs.h>
  42 #include <asm/arch/sys_proto.h>
  43
  44 #include "../common/karo.h"
  45
  46 #define IMX_GPIO_NR(b, o)       ((((b) - 1) << 5) | (o))
  47
  48 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  49 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  50 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  51 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  52
  53 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  54 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  55 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  56
  57 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  58
  59 DECLARE_GLOBAL_DATA_PTR;
  60
  61 #define MX53_GPIO_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE |            \
  62                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  63
  64 #define TX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_DSE_HIGH |       \
  65                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN)
  66
  67 static iomux_v3_cfg_t tx53_pads[] = {
  68         /* NAND flash pads are set up in lowlevel_init.S */
  69
  70         /* RESET_OUT */
  71         MX53_PAD_GPIO_17__GPIO7_12,
  72
  73         /* UART pads */
  74 #if CONFIG_MXC_UART_BASE == UART1_BASE
  75         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  76         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  77         MX53_PAD_PATA_IORDY__UART1_RTS,
  78         MX53_PAD_PATA_RESET_B__UART1_CTS,
  79 #endif
  80 #if CONFIG_MXC_UART_BASE == UART2_BASE
  81         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  82         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  83         MX53_PAD_PATA_DIOR__UART2_RTS,
  84         MX53_PAD_PATA_INTRQ__UART2_CTS,
  85 #endif
  86 #if CONFIG_MXC_UART_BASE == UART3_BASE
  87         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  88         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  89         MX53_PAD_PATA_DA_2__UART3_RTS,
  90         MX53_PAD_PATA_DA_1__UART3_CTS,
  91 #endif
  92         /* internal I2C */
  93         NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, MX53_GPIO_PAD_CTRL),
  94         NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, MX53_GPIO_PAD_CTRL),
  95
  96         /* FEC PHY GPIO functions */
  97         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  98         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  99         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
 100
 101         /* FEC functions */
 102         MX53_PAD_FEC_MDC__FEC_MDC,
 103         MX53_PAD_FEC_MDIO__FEC_MDIO,
 104         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 105         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 106         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 107         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 108         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 109         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 110         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 111         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 112 };
 113
 114 static const struct gpio tx53_gpios[] = {
 115         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 116         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 117         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 118         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 119 };
 120
 121 /*
 122  * Functions
 123  */
 124 /* placed in section '.data' to prevent overwriting relocation info
 125  * overlayed with bss
 126  */
 127 static u32 wrsr __attribute__((section(".data")));
 128
 129 #define WRSR_POR        (1 << 4)
 130 #define WRSR_TOUT       (1 << 1)
 131 #define WRSR_SFTW       (1 << 0)
 132
 133 static void print_reset_cause(void)
 134 {
 135         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 136         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 137         u32 srsr;
 138         char *dlm = "";
 139
 140         printf("Reset cause: ");
 141
 142         srsr = readl(&src_regs->srsr);
 143         wrsr = readw(wdt_base + 4);
 144
 145         if (wrsr & WRSR_POR) {
 146                 printf("%sPOR", dlm);
 147                 dlm = " | ";
 148         }
 149         if (srsr & 0x00004) {
 150                 printf("%sCSU", dlm);
 151                 dlm = " | ";
 152         }
 153         if (srsr & 0x00008) {
 154                 printf("%sIPP USER", dlm);
 155                 dlm = " | ";
 156         }
 157         if (srsr & 0x00010) {
 158                 if (wrsr & WRSR_SFTW) {
 159                         printf("%sSOFT", dlm);
 160                         dlm = " | ";
 161                 }
 162                 if (wrsr & WRSR_TOUT) {
 163                         printf("%sWDOG", dlm);
 164                         dlm = " | ";
 165                 }
 166         }
 167         if (srsr & 0x00020) {
 168                 printf("%sJTAG HIGH-Z", dlm);
 169                 dlm = " | ";
 170         }
 171         if (srsr & 0x00040) {
 172                 printf("%sJTAG SW", dlm);
 173                 dlm = " | ";
 174         }
 175         if (srsr & 0x10000) {
 176                 printf("%sWARM BOOT", dlm);
 177                 dlm = " | ";
 178         }
 179         if (dlm[0] == '\0')
 180                 printf("unknown");
 181
 182         printf("\n");
 183 }
 184
 185 static void print_cpuinfo(void)
 186 {
 187         u32 cpurev;
 188
 189         cpurev = get_cpu_rev();
 190
 191         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 192                 (cpurev & 0x000F0) >> 4,
 193                 (cpurev & 0x0000F) >> 0,
 194                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 195
 196         print_reset_cause();
 197 }
 198
 199 int board_early_init_f(void)
 200 {
 201         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 202         mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 203
 204         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 205         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 206
 207         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 208         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 209         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 210         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 211         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 212
 213         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 214         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 215
 216         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 217         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 218         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 219         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 220         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 221
 222         return 0;
 223 }
 224
 225 int board_init(void)
 226 {
 227         /* Address of boot parameters */
 228         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 229         return 0;
 230 }
 231
 232 int dram_init(void)
 233 {
 234         int ret;
 235
 236         /* dram_init must store complete ramsize in gd->ram_size */
 237         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 238                                 PHYS_SDRAM_1_SIZE);
 239
 240         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 241                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 242         if (ret)
 243                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 244                         CONFIG_SYS_SDRAM_CLK, ret);
 245         else
 246                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 247                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 248                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 249                         CONFIG_SYS_SDRAM_CLK);
 250         return ret;
 251 }
 252
 253 void dram_init_banksize(void)
 254 {
 255         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 256         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 257                         PHYS_SDRAM_1_SIZE);
 258 #if CONFIG_NR_DRAM_BANKS > 1
 259         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 260         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 261                         PHYS_SDRAM_2_SIZE);
 262 #endif
 263 }
 264
 265 #ifdef  CONFIG_CMD_MMC
 266 int board_mmc_getcd(struct mmc *mmc)
 267 {
 268         struct fsl_esdhc_cfg *cfg = mmc->priv;
 269
 270         if (cfg->cd_gpio < 0)
 271                 return cfg->cd_gpio;
 272
 273         return !gpio_get_value(cfg->cd_gpio);
 274 }
 275
 276 static struct fsl_esdhc_cfg esdhc_cfg[] = {
 277         {
 278                 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 279                 .no_snoop = 1,
 280                 .cd_gpio = IMX_GPIO_NR(3, 24),
 281                 .wp_gpio = -EINVAL,
 282         },
 283         {
 284                 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 285                 .no_snoop = 1,
 286                 .cd_gpio = IMX_GPIO_NR(3, 25),
 287                 .wp_gpio = -EINVAL,
 288         },
 289 };
 290
 291 static const iomux_v3_cfg_t mmc0_pads[] = {
 292         NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, TX53_SDHC_PAD_CTRL),
 293         NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, TX53_SDHC_PAD_CTRL),
 294         NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, TX53_SDHC_PAD_CTRL),
 295         NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, TX53_SDHC_PAD_CTRL),
 296         NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, TX53_SDHC_PAD_CTRL),
 297         NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, TX53_SDHC_PAD_CTRL),
 298         /* SD1 CD */
 299         NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, MX53_GPIO_PAD_CTRL),
 300 };
 301
 302 static const iomux_v3_cfg_t mmc1_pads[] = {
 303         NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, TX53_SDHC_PAD_CTRL),
 304         NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, TX53_SDHC_PAD_CTRL),
 305         NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, TX53_SDHC_PAD_CTRL),
 306         NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, TX53_SDHC_PAD_CTRL),
 307         NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, TX53_SDHC_PAD_CTRL),
 308         NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, TX53_SDHC_PAD_CTRL),
 309         /* SD2 CD */
 310         NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, MX53_GPIO_PAD_CTRL),
 311 };
 312
 313 static struct {
 314         const iomux_v3_cfg_t *pads;
 315         int count;
 316 } mmc_pad_config[] = {
 317         { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
 318         { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
 319 };
 320
 321 int board_mmc_init(bd_t *bis)
 322 {
 323         int i;
 324
 325         for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
 326                 struct mmc *mmc;
 327
 328                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 329                         break;
 330
 331                 mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
 332                                                 mmc_pad_config[i].count);
 333                 fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
 334
 335                 mmc = find_mmc_device(i);
 336                 if (mmc == NULL)
 337                         continue;
 338                 if (board_mmc_getcd(mmc) > 0)
 339                         mmc_init(mmc);
 340         }
 341         return 0;
 342 }
 343 #endif /* CONFIG_CMD_MMC */
 344
 345 #ifdef CONFIG_FEC_MXC
 346
 347 #ifndef ETH_ALEN
 348 #define ETH_ALEN 6
 349 #endif
 350
 351 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 352 {
 353         int i;
 354         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 355         struct fuse_bank *bank = &iim->bank[1];
 356         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 357
 358         if (dev_id > 0)
 359                 return;
 360
 361         for (i = 0; i < ETH_ALEN; i++)
 362                 mac[i] = readl(&fuse->mac_addr[i]);
 363 }
 364
 365 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 366                         PAD_CTL_SRE_FAST)
 367 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 368 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 369
 370 int board_eth_init(bd_t *bis)
 371 {
 372         int ret;
 373         unsigned char mac[ETH_ALEN];
 374         char mac_str[ETH_ALEN * 3] = "";
 375
 376         /* delay at least 21ms for the PHY internal POR signal to deassert */
 377         udelay(22000);
 378
 379         /* Deassert RESET to the external phy */
 380         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 381
 382         ret = cpu_eth_init(bis);
 383         if (ret) {
 384                 printf("cpu_eth_init() failed: %d\n", ret);
 385                 return ret;
 386         }
 387
 388         imx_get_mac_from_fuse(0, mac);
 389         snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
 390                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 391         setenv("ethaddr", mac_str);
 392
 393         return ret;
 394 }
 395 #endif /* CONFIG_FEC_MXC */
 396
 397 enum {
 398         LED_STATE_INIT = -1,
 399         LED_STATE_OFF,
 400         LED_STATE_ON,
 401 };
 402
 403 void show_activity(int arg)
 404 {
 405         static int led_state = LED_STATE_INIT;
 406         static ulong last;
 407
 408         if (led_state == LED_STATE_INIT) {
 409                 last = get_timer(0);
 410                 gpio_set_value(TX53_LED_GPIO, 1);
 411                 led_state = LED_STATE_ON;
 412         } else {
 413                 if (get_timer(last) > CONFIG_SYS_HZ) {
 414                         last = get_timer(0);
 415                         if (led_state == LED_STATE_ON) {
 416                                 gpio_set_value(TX53_LED_GPIO, 0);
 417                         } else {
 418                                 gpio_set_value(TX53_LED_GPIO, 1);
 419                         }
 420                         led_state = 1 - led_state;
 421                 }
 422         }
 423 }
 424
 425 static const iomux_v3_cfg_t stk5_pads[] = {
 426         /* SW controlled LED on STK5 baseboard */
 427         MX53_PAD_EIM_A18__GPIO2_20,
 428
 429         /* I2C bus on DIMM pins 40/41 */
 430         NEW_PAD_CTRL(MX53_PAD_GPIO_6__I2C3_SDA, MX53_GPIO_PAD_CTRL),
 431         NEW_PAD_CTRL(MX53_PAD_GPIO_3__I2C3_SCL, MX53_GPIO_PAD_CTRL),
 432
 433         /* TSC200x PEN IRQ */
 434         NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, MX53_GPIO_PAD_CTRL),
 435
 436         /* EDT-FT5x06 Polytouch panel */
 437         NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, MX53_GPIO_PAD_CTRL), /* IRQ */
 438         NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, MX53_GPIO_PAD_CTRL), /* RESET */
 439         NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, MX53_GPIO_PAD_CTRL), /* WAKE */
 440
 441         /* USBH1 */
 442         NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, MX53_GPIO_PAD_CTRL), /* VBUSEN */
 443         NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, MX53_GPIO_PAD_CTRL), /* OC */
 444         /* USBOTG */
 445         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 446         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 447
 448         /* DS1339 Interrupt */
 449         NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, MX53_GPIO_PAD_CTRL),
 450 };
 451
 452 static const struct gpio stk5_gpios[] = {
 453         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 454
 455         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 456         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 457         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 458         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 459 };
 460
 461 #ifdef CONFIG_LCD
 462 static ushort tx53_cmap[256];
 463 vidinfo_t panel_info = {
 464         /* set to max. size supported by SoC */
 465         .vl_col = 1600,
 466         .vl_row = 1200,
 467
 468         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 469         .cmap = tx53_cmap,
 470 };
 471
 472 static struct fb_videomode tx53_fb_mode = {
 473         /* Standard VGA timing */
 474         .name           = "VGA",
 475         .refresh        = 60,
 476         .xres           = 640,
 477         .yres           = 480,
 478         .pixclock       = KHZ2PICOS(25175),
 479         .left_margin    = 48,
 480         .hsync_len      = 96,
 481         .right_margin   = 16,
 482         .upper_margin   = 31,
 483         .vsync_len      = 2,
 484         .lower_margin   = 12,
 485         .sync           = FB_SYNC_CLK_LAT_FALL,
 486         .vmode          = FB_VMODE_NONINTERLACED,
 487 };
 488
 489 void *lcd_base;                 /* Start of framebuffer memory  */
 490 void *lcd_console_address;      /* Start of console buffer      */
 491
 492 int lcd_line_length;
 493 int lcd_color_fg;
 494 int lcd_color_bg;
 495
 496 short console_col;
 497 short console_row;
 498
 499 void lcd_initcolregs(void)
 500 {
 501 }
 502
 503 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
 504 {
 505 }
 506
 507 static int lcd_enabled = 1;
 508
 509 void lcd_enable(void)
 510 {
 511         /* HACK ALERT:
 512          * global variable from common/lcd.c
 513          * Set to 0 here to prevent messages from going to LCD
 514          * rather than serial console
 515          */
 516         lcd_is_enabled = 0;
 517
 518         karo_load_splashimage(1);
 519         if (lcd_enabled) {
 520                 debug("Switching LCD on\n");
 521                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 522                 udelay(100);
 523                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 524                 udelay(300000);
 525                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
 526         }
 527 }
 528
 529 void mxcfb_disable(void);
 530
 531 void lcd_disable(void)
 532 {
 533         mxcfb_disable();
 534 }
 535
 536 void lcd_panel_disable(void)
 537 {
 538         if (lcd_enabled) {
 539                 debug("Switching LCD off\n");
 540                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1);
 541                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 542                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 543         }
 544 }
 545
 546 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 547         /* LCD RESET */
 548         NEW_PAD_CTRL(MX53_PAD_EIM_D29__GPIO3_29, MX53_GPIO_PAD_CTRL),
 549         /* LCD POWER_ENABLE */
 550         NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, MX53_GPIO_PAD_CTRL),
 551         /* LCD Backlight (PWM) */
 552         NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, MX53_GPIO_PAD_CTRL),
 553
 554         /* Display */
 555         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 556         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 557         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 558         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 559         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 560         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 561         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 562         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 563         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 564         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 565         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 566         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 567         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 568         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 569         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 570         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 571         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 572         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 573         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 574         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 575         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 576         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 577         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 578         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 579         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 580         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 581         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 582         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 583
 584         /* LVDS option */
 585         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 586         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 587         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 588         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 589         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 590         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 591         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 592         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 593         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 594         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 595 };
 596
 597 static const struct gpio stk5_lcd_gpios[] = {
 598         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 599         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 600         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 601 };
 602
 603 void lcd_ctrl_init(void *lcdbase)
 604 {
 605         int color_depth = 24;
 606         char *vm;
 607         unsigned long val;
 608         int refresh = 60;
 609         struct fb_videomode *p = &tx53_fb_mode;
 610         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 611         int pix_fmt = 0;
 612
 613         if (!lcd_enabled) {
 614                 debug("LCD disabled\n");
 615                 return;
 616         }
 617
 618         if (tstc() || (wrsr & WRSR_TOUT)) {
 619                 debug("Disabling LCD\n");
 620                 lcd_enabled = 0;
 621                 return;
 622         }
 623
 624         vm = getenv("video_mode");
 625         if (vm == NULL) {
 626                 debug("Disabling LCD\n");
 627                 lcd_enabled = 0;
 628                 return;
 629         }
 630         while (*vm != '\0') {
 631                 if (*vm >= '0' && *vm <= '9') {
 632                         char *end;
 633
 634                         val = simple_strtoul(vm, &end, 0);
 635                         if (end > vm) {
 636                                 if (!xres_set) {
 637                                         if (val > panel_info.vl_col)
 638                                                 val = panel_info.vl_col;
 639                                         p->xres = val;
 640                                         panel_info.vl_col = val;
 641                                         xres_set = 1;
 642                                 } else if (!yres_set) {
 643                                         if (val > panel_info.vl_row)
 644                                                 val = panel_info.vl_row;
 645                                         p->yres = val;
 646                                         panel_info.vl_row = val;
 647                                         yres_set = 1;
 648                                 } else if (!bpp_set) {
 649                                         switch (val) {
 650                                         case 24:
 651                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 652                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 653                                                 /* fallthru */
 654                                         case 16:
 655                                         case 8:
 656                                                 color_depth = val;
 657                                                 break;
 658
 659                                         case 18:
 660                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 661                                                         color_depth = val;
 662                                                         break;
 663                                                 }
 664                                                 /* fallthru */
 665                                         default:
 666                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 667                                                         end - vm, vm, color_depth);
 668                                         }
 669                                         bpp_set = 1;
 670                                 } else if (!refresh_set) {
 671                                         refresh = val;
 672                                         refresh_set = 1;
 673                                 }
 674                         }
 675                         vm = end;
 676                 }
 677                 switch (*vm) {
 678                 case '@':
 679                         bpp_set = 1;
 680                         /* fallthru */
 681                 case '-':
 682                         yres_set = 1;
 683                         /* fallthru */
 684                 case 'x':
 685                         xres_set = 1;
 686                         /* fallthru */
 687                 case 'M':
 688                 case 'R':
 689                         vm++;
 690                         break;
 691
 692                 default:
 693                         if (!pix_fmt) {
 694                                 char *tmp;
 695
 696                                 if (strncmp(vm, "LVDS", 4) == 0)
 697                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 698                                 else
 699                                         pix_fmt = IPU_PIX_FMT_RGB24;
 700                                 tmp = strchr(vm, ':');
 701                                 if (tmp)
 702                                         vm = tmp;
 703                         }
 704                         if (*vm != '\0')
 705                                 vm++;
 706                 }
 707         }
 708         switch (color_depth) {
 709         case 8:
 710                 panel_info.vl_bpix = 3;
 711                 break;
 712
 713         case 16:
 714                 panel_info.vl_bpix = 4;
 715                 break;
 716
 717         case 18:
 718         case 24:
 719                 panel_info.vl_bpix = 5;
 720         }
 721         lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col;
 722
 723         p->pixclock = KHZ2PICOS(refresh *
 724                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 725                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 726                 / 1000);
 727         debug("Pixel clock set to %lu.%03lu MHz\n",
 728                 PICOS2KHZ(p->pixclock) / 1000,
 729                 PICOS2KHZ(p->pixclock) % 1000);
 730
 731         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 732         mxc_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 733                                         ARRAY_SIZE(stk5_lcd_pads));
 734
 735         debug("Initializing FB driver\n");
 736         if (!pix_fmt)
 737                 pix_fmt = IPU_PIX_FMT_RGB24;
 738         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 739                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 740         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 741                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 742         }
 743         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 744                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 745                 /* enable LDB & DI0 clock */
 746                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
 747                         &ccm_regs->CCGR6);
 748         }
 749
 750         mx5_fb_init(p, 0, pix_fmt, 1 << panel_info.vl_bpix);
 751
 752         if (karo_load_splashimage(0) == 0) {
 753                 debug("Initializing LCD controller\n");
 754                 video_hw_init();
 755         } else {
 756                 debug("Skipping initialization of LCD controller\n");
 757         }
 758 }
 759 #else
 760 #define lcd_enabled 0
 761 #endif /* CONFIG_LCD */
 762
 763 static void stk5_board_init(void)
 764 {
 765         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 766         mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 767 }
 768
 769 static void stk5v3_board_init(void)
 770 {
 771         stk5_board_init();
 772 }
 773
 774 static void stk5v5_board_init(void)
 775 {
 776         stk5_board_init();
 777
 778         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
 779                         "Flexcan Transceiver");
 780         mxc_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
 781 }
 782
 783 static void tx53_set_cpu_clock(void)
 784 {
 785         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 786         int ret;
 787
 788         if (tstc() || (wrsr & WRSR_TOUT))
 789                 return;
 790
 791         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 792                 return;
 793
 794         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
 795         if (ret != 0) {
 796                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 797                 return;
 798         }
 799         printf("CPU clock set to %u.%03u MHz\n",
 800                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
 801                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
 802 }
 803
 804 int board_late_init(void)
 805 {
 806         int ret = 0;
 807         const char *baseboard;
 808
 809         tx53_set_cpu_clock();
 810         karo_fdt_move_fdt();
 811
 812         baseboard = getenv("baseboard");
 813         if (!baseboard)
 814                 goto exit;
 815
 816         if (strncmp(baseboard, "stk5", 4) == 0) {
 817                 printf("Baseboard: %s\n", baseboard);
 818                 if ((strlen(baseboard) == 4) ||
 819                         strcmp(baseboard, "stk5-v3") == 0) {
 820                         stk5v3_board_init();
 821                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 822                         stk5v5_board_init();
 823                 } else {
 824                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 825                                 baseboard + 4);
 826                 }
 827         } else {
 828                 printf("WARNING: Unsupported baseboard: '%s'\n",
 829                         baseboard);
 830                 ret = -EINVAL;
 831         }
 832
 833 exit:
 834         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
 835         return ret;
 836 }
 837
 838 int checkboard(void)
 839 {
 840         print_cpuinfo();
 841
 842         printf("Board: Ka-Ro TX53-xx3%s\n",
 843                 TX53_MOD_SUFFIX);
 844
 845         return 0;
 846 }
 847
 848 #if defined(CONFIG_OF_BOARD_SETUP)
 849 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 850 #include <jffs2/jffs2.h>
 851 #include <mtd_node.h>
 852 struct node_info nodes[] = {
 853         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
 854 };
 855
 856 #else
 857 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 858 #endif
 859
 860 static void tx53_fixup_flexcan(void *blob)
 861 {
 862         const char *baseboard = getenv("baseboard");
 863
 864         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
 865                 return;
 866
 867         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch");
 868         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch");
 869 }
 870
 871 #ifdef CONFIG_SYS_TX53_HWREV_2
 872 void tx53_fixup_rtc(void *blob)
 873 {
 874         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
 875         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
 876 }
 877 #else
 878 static inline void tx53_fixup_rtc(void *blob)
 879 {
 880 }
 881 #endif
 882
 883 void ft_board_setup(void *blob, bd_t *bd)
 884 {
 885         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 886         fdt_fixup_ethernet(blob);
 887
 888         karo_fdt_fixup_touchpanel(blob);
 889         karo_fdt_fixup_usb_otg(blob);
 890         tx53_fixup_flexcan(blob);
 891         tx53_fixup_rtc(blob);
 892 }
 893 #endif