board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <lcd.h>
  24 #include <netdev.h>
  25 #include <mmc.h>
  26 #include <fsl_esdhc.h>
  27 #include <video_fb.h>
  28 #include <ipu.h>
  29 #include <mxcfb.h>
  30 #include <linux/fb.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/iomux-mx53.h>
  34 #include <asm/arch/clock.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40
  41 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  42 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  43 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  44 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  45
  46 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  47 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  48 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  49
  50 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  55                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  56
  57 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  58                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  59
  60 static iomux_v3_cfg_t tx53_pads[] = {
  61         /* NAND flash pads are set up in lowlevel_init.S */
  62
  63         /* UART pads */
  64 #if CONFIG_MXC_UART_BASE == UART1_BASE
  65         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  66         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  67         MX53_PAD_PATA_IORDY__UART1_RTS,
  68         MX53_PAD_PATA_RESET_B__UART1_CTS,
  69 #endif
  70 #if CONFIG_MXC_UART_BASE == UART2_BASE
  71         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  72         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  73         MX53_PAD_PATA_DIOR__UART2_RTS,
  74         MX53_PAD_PATA_INTRQ__UART2_CTS,
  75 #endif
  76 #if CONFIG_MXC_UART_BASE == UART3_BASE
  77         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  78         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  79         MX53_PAD_PATA_DA_2__UART3_RTS,
  80         MX53_PAD_PATA_DA_1__UART3_CTS,
  81 #endif
  82         /* internal I2C */
  83         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  84         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  85
  86         /* FEC PHY GPIO functions */
  87         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  88         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  89         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  90
  91         /* FEC functions */
  92         MX53_PAD_FEC_MDC__FEC_MDC,
  93         MX53_PAD_FEC_MDIO__FEC_MDIO,
  94         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  95         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  96         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  97         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  98         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  99         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 100         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 101         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 102 };
 103
 104 static const struct gpio tx53_gpios[] = {
 105         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 106         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 107         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 108         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 109 };
 110
 111 /*
 112  * Functions
 113  */
 114 /* placed in section '.data' to prevent overwriting relocation info
 115  * overlayed with bss
 116  */
 117 static u32 wrsr __attribute__((section(".data")));
 118
 119 #define WRSR_POR        (1 << 4)
 120 #define WRSR_TOUT       (1 << 1)
 121 #define WRSR_SFTW       (1 << 0)
 122
 123 static void print_reset_cause(void)
 124 {
 125         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 126         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 127         u32 srsr;
 128         char *dlm = "";
 129
 130         printf("Reset cause: ");
 131
 132         srsr = readl(&src_regs->srsr);
 133         wrsr = readw(wdt_base + 4);
 134
 135         if (wrsr & WRSR_POR) {
 136                 printf("%sPOR", dlm);
 137                 dlm = " | ";
 138         }
 139         if (srsr & 0x00004) {
 140                 printf("%sCSU", dlm);
 141                 dlm = " | ";
 142         }
 143         if (srsr & 0x00008) {
 144                 printf("%sIPP USER", dlm);
 145                 dlm = " | ";
 146         }
 147         if (srsr & 0x00010) {
 148                 if (wrsr & WRSR_SFTW) {
 149                         printf("%sSOFT", dlm);
 150                         dlm = " | ";
 151                 }
 152                 if (wrsr & WRSR_TOUT) {
 153                         printf("%sWDOG", dlm);
 154                         dlm = " | ";
 155                 }
 156         }
 157         if (srsr & 0x00020) {
 158                 printf("%sJTAG HIGH-Z", dlm);
 159                 dlm = " | ";
 160         }
 161         if (srsr & 0x00040) {
 162                 printf("%sJTAG SW", dlm);
 163                 dlm = " | ";
 164         }
 165         if (srsr & 0x10000) {
 166                 printf("%sWARM BOOT", dlm);
 167                 dlm = " | ";
 168         }
 169         if (dlm[0] == '\0')
 170                 printf("unknown");
 171
 172         printf("\n");
 173 }
 174
 175 static void tx53_print_cpuinfo(void)
 176 {
 177         u32 cpurev;
 178
 179         cpurev = get_cpu_rev();
 180
 181         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 182                 (cpurev & 0x000F0) >> 4,
 183                 (cpurev & 0x0000F) >> 0,
 184                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 185
 186         print_reset_cause();
 187 }
 188
 189 int board_early_init_f(void)
 190 {
 191         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 192
 193         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 194         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 195
 196         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 197         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 198
 199         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 200         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 201         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 202         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 203         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 204
 205         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 206         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 207
 208         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 209         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 210         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 211         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 212         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 213
 214         writel(0xffcf0fff, &ccm_regs->CCGR0);
 215         writel(0x000fffc3, &ccm_regs->CCGR1);
 216         writel(0x033c0000, &ccm_regs->CCGR2);
 217         writel(0x000000ff, &ccm_regs->CCGR3);
 218         writel(0x00000000, &ccm_regs->CCGR4);
 219         writel(0x00fff033, &ccm_regs->CCGR5);
 220         writel(0x0f00030f, &ccm_regs->CCGR6);
 221         writel(0xfff00000, &ccm_regs->CCGR7);
 222         writel(0x00000000, &ccm_regs->cmeor);
 223
 224         return 0;
 225 }
 226
 227 int board_init(void)
 228 {
 229         /* Address of boot parameters */
 230         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 231         return 0;
 232 }
 233
 234 int dram_init(void)
 235 {
 236         int ret;
 237
 238         /* dram_init must store complete ramsize in gd->ram_size */
 239         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 240                                 PHYS_SDRAM_1_SIZE);
 241
 242         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 243                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 244         if (ret)
 245                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 246                         CONFIG_SYS_SDRAM_CLK, ret);
 247         else
 248                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 249                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 250                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 251                         CONFIG_SYS_SDRAM_CLK);
 252         return ret;
 253 }
 254
 255 void dram_init_banksize(void)
 256 {
 257         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 258         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 259                         PHYS_SDRAM_1_SIZE);
 260 #if CONFIG_NR_DRAM_BANKS > 1
 261         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 262         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 263                         PHYS_SDRAM_2_SIZE);
 264 #endif
 265 }
 266
 267 #ifdef  CONFIG_CMD_MMC
 268 static const iomux_v3_cfg_t mmc0_pads[] = {
 269         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 270         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 271         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 272         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 273         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 274         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 275         /* SD1 CD */
 276         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 277 };
 278
 279 static const iomux_v3_cfg_t mmc1_pads[] = {
 280         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 281         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 282         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 283         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 284         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 285         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 286         /* SD2 CD */
 287         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 288 };
 289
 290 static struct tx53_esdhc_cfg {
 291         const iomux_v3_cfg_t *pads;
 292         int num_pads;
 293         struct fsl_esdhc_cfg cfg;
 294         int cd_gpio;
 295 } tx53_esdhc_cfg[] = {
 296         {
 297                 .pads = mmc0_pads,
 298                 .num_pads = ARRAY_SIZE(mmc0_pads),
 299                 .cfg = {
 300                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 301                         .max_bus_width = 4,
 302                 },
 303                 .cd_gpio = IMX_GPIO_NR(3, 24),
 304         },
 305         {
 306                 .pads = mmc1_pads,
 307                 .num_pads = ARRAY_SIZE(mmc1_pads),
 308                 .cfg = {
 309                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 310                         .max_bus_width = 4,
 311                 },
 312                 .cd_gpio = IMX_GPIO_NR(3, 25),
 313         },
 314 };
 315
 316 #if 1
 317 #define to_tx53_esdhc_cfg(p) container_of(p, struct tx53_esdhc_cfg, cfg)
 318 #else
 319 static struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 320 {
 321         void *p = cfg;
 322
 323         return p - offsetof(struct tx53_esdhc_cfg, cfg);
 324 }
 325 #endif
 326
 327 int board_mmc_getcd(struct mmc *mmc)
 328 {
 329         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
 330
 331         if (cfg->cd_gpio < 0)
 332                 return cfg->cd_gpio;
 333
 334         debug("SD card %d is %spresent\n",
 335                 cfg - tx53_esdhc_cfg,
 336                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 337         return !gpio_get_value(cfg->cd_gpio);
 338 }
 339
 340 int board_mmc_init(bd_t *bis)
 341 {
 342         int i;
 343
 344         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
 345                 struct mmc *mmc;
 346                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
 347                 int ret;
 348
 349                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 350                         break;
 351
 352                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 353                                                 cfg->num_pads);
 354                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 355
 356                 fsl_esdhc_initialize(bis, &cfg->cfg);
 357
 358                 ret = gpio_request_one(cfg->cd_gpio,
 359                                 GPIOF_INPUT, "MMC CD");
 360                 if (ret) {
 361                         printf("Error %d requesting GPIO%d_%d\n",
 362                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 363                         continue;
 364                 }
 365
 366                 mmc = find_mmc_device(i);
 367                 if (mmc == NULL)
 368                         continue;
 369                 if (board_mmc_getcd(mmc) > 0)
 370                         mmc_init(mmc);
 371         }
 372         return 0;
 373 }
 374 #endif /* CONFIG_CMD_MMC */
 375
 376 #ifdef CONFIG_FEC_MXC
 377
 378 #ifndef ETH_ALEN
 379 #define ETH_ALEN 6
 380 #endif
 381
 382 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 383 {
 384         int i;
 385         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 386         struct fuse_bank *bank = &iim->bank[1];
 387         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 388
 389         if (dev_id > 0)
 390                 return;
 391
 392         for (i = 0; i < ETH_ALEN; i++)
 393                 mac[i] = readl(&fuse->mac_addr[i]);
 394 }
 395
 396 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 397                         PAD_CTL_SRE_FAST)
 398 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 399 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 400
 401 int board_eth_init(bd_t *bis)
 402 {
 403         int ret;
 404         unsigned char mac[ETH_ALEN];
 405
 406         /* delay at least 21ms for the PHY internal POR signal to deassert */
 407         udelay(22000);
 408
 409         /* Deassert RESET to the external phy */
 410         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 411
 412         ret = cpu_eth_init(bis);
 413         if (ret) {
 414                 printf("cpu_eth_init() failed: %d\n", ret);
 415                 return ret;
 416         }
 417
 418         imx_get_mac_from_fuse(0, mac);
 419         eth_setenv_enetaddr("ethaddr", mac);
 420         printf("MAC addr from fuse: %pM\n", mac);
 421
 422         return ret;
 423 }
 424 #endif /* CONFIG_FEC_MXC */
 425
 426 enum {
 427         LED_STATE_INIT = -1,
 428         LED_STATE_OFF,
 429         LED_STATE_ON,
 430 };
 431
 432 void show_activity(int arg)
 433 {
 434         static int led_state = LED_STATE_INIT;
 435         static ulong last;
 436
 437         if (led_state == LED_STATE_INIT) {
 438                 last = get_timer(0);
 439                 gpio_set_value(TX53_LED_GPIO, 1);
 440                 led_state = LED_STATE_ON;
 441         } else {
 442                 if (get_timer(last) > CONFIG_SYS_HZ) {
 443                         last = get_timer(0);
 444                         if (led_state == LED_STATE_ON) {
 445                                 gpio_set_value(TX53_LED_GPIO, 0);
 446                         } else {
 447                                 gpio_set_value(TX53_LED_GPIO, 1);
 448                         }
 449                         led_state = 1 - led_state;
 450                 }
 451         }
 452 }
 453
 454 static const iomux_v3_cfg_t stk5_pads[] = {
 455         /* SW controlled LED on STK5 baseboard */
 456         MX53_PAD_EIM_A18__GPIO2_20,
 457
 458         /* I2C bus on DIMM pins 40/41 */
 459         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 460         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 461
 462         /* TSC200x PEN IRQ */
 463         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 464
 465         /* EDT-FT5x06 Polytouch panel */
 466         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 467         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 468         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 469
 470         /* USBH1 */
 471         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 472         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 473         /* USBOTG */
 474         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 475         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 476
 477         /* DS1339 Interrupt */
 478         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 479 };
 480
 481 static const struct gpio stk5_gpios[] = {
 482         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 483
 484         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 485         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 486         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 487         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 488 };
 489
 490 #ifdef CONFIG_LCD
 491 static ushort tx53_cmap[256];
 492 vidinfo_t panel_info = {
 493         /* set to max. size supported by SoC */
 494         .vl_col = 1600,
 495         .vl_row = 1200,
 496
 497         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 498         .cmap = tx53_cmap,
 499 };
 500
 501 static struct fb_videomode tx53_fb_modes[] = {
 502         {
 503                 /* Standard VGA timing */
 504                 .name           = "VGA",
 505                 .refresh        = 60,
 506                 .xres           = 640,
 507                 .yres           = 480,
 508                 .pixclock       = KHZ2PICOS(25175),
 509                 .left_margin    = 48,
 510                 .hsync_len      = 96,
 511                 .right_margin   = 16,
 512                 .upper_margin   = 31,
 513                 .vsync_len      = 2,
 514                 .lower_margin   = 12,
 515                 .sync           = FB_SYNC_CLK_LAT_FALL,
 516         },
 517         {
 518                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 519                  * DE high active, 115.2 mm x 86.4 mm display area
 520                  * VGA compatible timing
 521                  */
 522                 .name           = "ETV570",
 523                 .refresh        = 60,
 524                 .xres           = 640,
 525                 .yres           = 480,
 526                 .pixclock       = KHZ2PICOS(25175),
 527                 .left_margin    = 114,
 528                 .hsync_len      = 30,
 529                 .right_margin   = 16,
 530                 .upper_margin   = 32,
 531                 .vsync_len      = 3,
 532                 .lower_margin   = 10,
 533                 .sync           = FB_SYNC_CLK_LAT_FALL,
 534         },
 535         {
 536                 /* Emerging ET0350G0DH6 320 x 240 display.
 537                  * 70.08 mm x 52.56 mm display area.
 538                  */
 539                 .name           = "ET0350",
 540                 .refresh        = 60,
 541                 .xres           = 320,
 542                 .yres           = 240,
 543                 .pixclock       = KHZ2PICOS(6500),
 544                 .left_margin    = 68 - 34,
 545                 .hsync_len      = 34,
 546                 .right_margin   = 20,
 547                 .upper_margin   = 18 - 3,
 548                 .vsync_len      = 3,
 549                 .lower_margin   = 4,
 550                 .sync           = FB_SYNC_CLK_LAT_FALL,
 551         },
 552         {
 553                 /* Emerging ET0430G0DH6 480 x 272 display.
 554                  * 95.04 mm x 53.856 mm display area.
 555                  */
 556                 .name           = "ET0430",
 557                 .refresh        = 60,
 558                 .xres           = 480,
 559                 .yres           = 272,
 560                 .pixclock       = KHZ2PICOS(9000),
 561                 .left_margin    = 2,
 562                 .hsync_len      = 41,
 563                 .right_margin   = 2,
 564                 .upper_margin   = 2,
 565                 .vsync_len      = 10,
 566                 .lower_margin   = 2,
 567                 .sync           = FB_SYNC_CLK_LAT_FALL,
 568         },
 569         {
 570                 /* Emerging ET0500G0DH6 800 x 480 display.
 571                  * 109.6 mm x 66.4 mm display area.
 572                  */
 573                 .name           = "ET0500",
 574                 .refresh        = 60,
 575                 .xres           = 800,
 576                 .yres           = 480,
 577                 .pixclock       = KHZ2PICOS(33260),
 578                 .left_margin    = 216 - 128,
 579                 .hsync_len      = 128,
 580                 .right_margin   = 1056 - 800 - 216,
 581                 .upper_margin   = 35 - 2,
 582                 .vsync_len      = 2,
 583                 .lower_margin   = 525 - 480 - 35,
 584                 .sync           = FB_SYNC_CLK_LAT_FALL,
 585         },
 586         {
 587                 /* Emerging ETQ570G0DH6 320 x 240 display.
 588                  * 115.2 mm x 86.4 mm display area.
 589                  */
 590                 .name           = "ETQ570",
 591                 .refresh        = 60,
 592                 .xres           = 320,
 593                 .yres           = 240,
 594                 .pixclock       = KHZ2PICOS(6400),
 595                 .left_margin    = 38,
 596                 .hsync_len      = 30,
 597                 .right_margin   = 30,
 598                 .upper_margin   = 16, /* 15 according to datasheet */
 599                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 600                 .lower_margin   = 4, /* 4.5 according to datasheet */
 601                 .sync           = FB_SYNC_CLK_LAT_FALL,
 602         },
 603         {
 604                 /* Emerging ET0700G0DH6 800 x 480 display.
 605                  * 152.4 mm x 91.44 mm display area.
 606                  */
 607                 .name           = "ET0700",
 608                 .refresh        = 60,
 609                 .xres           = 800,
 610                 .yres           = 480,
 611                 .pixclock       = KHZ2PICOS(33260),
 612                 .left_margin    = 216 - 128,
 613                 .hsync_len      = 128,
 614                 .right_margin   = 1056 - 800 - 216,
 615                 .upper_margin   = 35 - 2,
 616                 .vsync_len      = 2,
 617                 .lower_margin   = 525 - 480 - 35,
 618                 .sync           = FB_SYNC_CLK_LAT_FALL,
 619         },
 620         {
 621                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 622                 .refresh        = 60,
 623                 .left_margin    = 48,
 624                 .hsync_len      = 96,
 625                 .right_margin   = 16,
 626                 .upper_margin   = 31,
 627                 .vsync_len      = 2,
 628                 .lower_margin   = 12,
 629                 .sync           = FB_SYNC_CLK_LAT_FALL,
 630         },
 631 };
 632
 633 static int lcd_enabled = 1;
 634
 635 void lcd_enable(void)
 636 {
 637         /* HACK ALERT:
 638          * global variable from common/lcd.c
 639          * Set to 0 here to prevent messages from going to LCD
 640          * rather than serial console
 641          */
 642         lcd_is_enabled = 0;
 643
 644         karo_load_splashimage(1);
 645         if (lcd_enabled) {
 646                 debug("Switching LCD on\n");
 647                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 648                 udelay(100);
 649                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 650                 udelay(300000);
 651                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
 652         }
 653 }
 654
 655 void lcd_disable(void)
 656 {
 657         printf("Disabling LCD\n");
 658 }
 659
 660 void lcd_panel_disable(void)
 661 {
 662         if (lcd_enabled) {
 663                 debug("Switching LCD off\n");
 664                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1);
 665                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 666                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 667         }
 668 }
 669
 670 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 671         /* LCD RESET */
 672         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 673         /* LCD POWER_ENABLE */
 674         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 675         /* LCD Backlight (PWM) */
 676         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 677
 678         /* Display */
 679         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 680         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 681         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 682         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 683         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 684         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 685         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 686         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 687         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 688         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 689         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 690         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 691         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 692         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 693         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 694         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 695         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 696         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 697         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 698         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 699         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 700         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 701         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 702         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 703         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 704         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 705         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 706         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 707
 708         /* LVDS option */
 709         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 710         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 711         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 712         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 713         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 714         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 715         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 716         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 717         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 718         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 719 };
 720
 721 static const struct gpio stk5_lcd_gpios[] = {
 722         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 723         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 724         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 725 };
 726
 727 void lcd_ctrl_init(void *lcdbase)
 728 {
 729         int color_depth = 24;
 730         char *vm;
 731         unsigned long val;
 732         int refresh = 60;
 733         struct fb_videomode *p = &tx53_fb_modes[0];
 734         struct fb_videomode fb_mode;
 735         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 736         int pix_fmt = 0;
 737         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 738         unsigned long di_clk_rate = 65000000;
 739
 740         if (!lcd_enabled) {
 741                 debug("LCD disabled\n");
 742                 return;
 743         }
 744
 745         if (tstc() || (wrsr & WRSR_TOUT)) {
 746                 debug("Disabling LCD\n");
 747                 lcd_enabled = 0;
 748                 return;
 749         }
 750
 751         karo_fdt_move_fdt();
 752
 753         vm = getenv("video_mode");
 754         if (vm == NULL) {
 755                 debug("Disabling LCD\n");
 756                 lcd_enabled = 0;
 757                 return;
 758         }
 759         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 760                 p = &fb_mode;
 761                 debug("Using video mode from FDT\n");
 762                 vm += strlen(vm);
 763                 if (fb_mode.xres < panel_info.vl_col)
 764                         panel_info.vl_col = fb_mode.xres;
 765                 if (fb_mode.yres < panel_info.vl_row)
 766                         panel_info.vl_row = fb_mode.yres;
 767         }
 768         if (p->name != NULL)
 769                 debug("Trying compiled-in video modes\n");
 770         while (p->name != NULL) {
 771                 if (strcmp(p->name, vm) == 0) {
 772                         debug("Using video mode: '%s'\n", p->name);
 773                         vm += strlen(vm);
 774                         break;
 775                 }
 776                 p++;
 777         }
 778         if (*vm != '\0')
 779                 debug("Trying to decode video_mode: '%s'\n", vm);
 780         while (*vm != '\0') {
 781                 if (*vm >= '0' && *vm <= '9') {
 782                         char *end;
 783
 784                         val = simple_strtoul(vm, &end, 0);
 785                         if (end > vm) {
 786                                 if (!xres_set) {
 787                                         if (val > panel_info.vl_col)
 788                                                 val = panel_info.vl_col;
 789                                         p->xres = val;
 790                                         panel_info.vl_col = val;
 791                                         xres_set = 1;
 792                                 } else if (!yres_set) {
 793                                         if (val > panel_info.vl_row)
 794                                                 val = panel_info.vl_row;
 795                                         p->yres = val;
 796                                         panel_info.vl_row = val;
 797                                         yres_set = 1;
 798                                 } else if (!bpp_set) {
 799                                         switch (val) {
 800                                         case 32:
 801                                         case 24:
 802                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 803                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 804                                                 /* fallthru */
 805                                         case 16:
 806                                         case 8:
 807                                                 color_depth = val;
 808                                                 break;
 809
 810                                         case 18:
 811                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 812                                                         color_depth = val;
 813                                                         break;
 814                                                 }
 815                                                 /* fallthru */
 816                                         default:
 817                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 818                                                         end - vm, vm, color_depth);
 819                                         }
 820                                         bpp_set = 1;
 821                                 } else if (!refresh_set) {
 822                                         refresh = val;
 823                                         refresh_set = 1;
 824                                 }
 825                         }
 826                         vm = end;
 827                 }
 828                 switch (*vm) {
 829                 case '@':
 830                         bpp_set = 1;
 831                         /* fallthru */
 832                 case '-':
 833                         yres_set = 1;
 834                         /* fallthru */
 835                 case 'x':
 836                         xres_set = 1;
 837                         /* fallthru */
 838                 case 'M':
 839                 case 'R':
 840                         vm++;
 841                         break;
 842
 843                 default:
 844                         if (!pix_fmt) {
 845                                 char *tmp;
 846
 847                                 if (strncmp(vm, "LVDS", 4) == 0) {
 848                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 849                                         di_clk_parent = DI_PCLK_LDB;
 850                                 } else {
 851                                         pix_fmt = IPU_PIX_FMT_RGB24;
 852                                 }
 853                                 tmp = strchr(vm, ':');
 854                                 if (tmp)
 855                                         vm = tmp;
 856                         }
 857                         if (*vm != '\0')
 858                                 vm++;
 859                 }
 860         }
 861         if (p->xres == 0 || p->yres == 0) {
 862                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 863                 lcd_enabled = 0;
 864                 printf("Supported video modes are:");
 865                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
 866                         printf(" %s", p->name);
 867                 }
 868                 printf("\n");
 869                 return;
 870         }
 871
 872         p->pixclock = KHZ2PICOS(refresh *
 873                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 874                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 875                 / 1000);
 876         debug("Pixel clock set to %lu.%03lu MHz\n",
 877                 PICOS2KHZ(p->pixclock) / 1000,
 878                 PICOS2KHZ(p->pixclock) % 1000);
 879
 880         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 881         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 882                                         ARRAY_SIZE(stk5_lcd_pads));
 883
 884         debug("Initializing FB driver\n");
 885         if (!pix_fmt)
 886                 pix_fmt = IPU_PIX_FMT_RGB24;
 887         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 888                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 889         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 890                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 891         }
 892         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 893                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 894                 /* enable LDB & DI0 clock */
 895                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
 896                         &ccm_regs->CCGR6);
 897         }
 898
 899         if (karo_load_splashimage(0) == 0) {
 900                 debug("Initializing LCD controller\n");
 901                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 902         } else {
 903                 debug("Skipping initialization of LCD controller\n");
 904         }
 905 }
 906 #else
 907 #define lcd_enabled 0
 908 #endif /* CONFIG_LCD */
 909
 910 static void stk5_board_init(void)
 911 {
 912         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 913         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 914 }
 915
 916 static void stk5v3_board_init(void)
 917 {
 918         stk5_board_init();
 919 }
 920
 921 static void stk5v5_board_init(void)
 922 {
 923         stk5_board_init();
 924
 925         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
 926                         "Flexcan Transceiver");
 927         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
 928 }
 929
 930 static void tx53_set_cpu_clock(void)
 931 {
 932         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 933         int ret;
 934
 935         if (tstc() || (wrsr & WRSR_TOUT))
 936                 return;
 937
 938         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 939                 return;
 940
 941         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
 942         if (ret != 0) {
 943                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 944                 return;
 945         }
 946         printf("CPU clock set to %u.%03u MHz\n",
 947                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
 948                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
 949 }
 950
 951 int board_late_init(void)
 952 {
 953         int ret = 0;
 954         const char *baseboard;
 955
 956         tx53_set_cpu_clock();
 957         karo_fdt_move_fdt();
 958
 959         baseboard = getenv("baseboard");
 960         if (!baseboard)
 961                 goto exit;
 962
 963         if (strncmp(baseboard, "stk5", 4) == 0) {
 964                 printf("Baseboard: %s\n", baseboard);
 965                 if ((strlen(baseboard) == 4) ||
 966                         strcmp(baseboard, "stk5-v3") == 0) {
 967                         stk5v3_board_init();
 968                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 969                         stk5v5_board_init();
 970                 } else {
 971                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 972                                 baseboard + 4);
 973                 }
 974         } else {
 975                 printf("WARNING: Unsupported baseboard: '%s'\n",
 976                         baseboard);
 977                 ret = -EINVAL;
 978         }
 979
 980 exit:
 981         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
 982         return ret;
 983 }
 984
 985 int checkboard(void)
 986 {
 987         tx53_print_cpuinfo();
 988
 989         printf("Board: Ka-Ro TX53-xx3%s\n",
 990                 TX53_MOD_SUFFIX);
 991
 992         return 0;
 993 }
 994
 995 #if defined(CONFIG_OF_BOARD_SETUP)
 996 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 997 #include <jffs2/jffs2.h>
 998 #include <mtd_node.h>
 999 struct node_info nodes[] = {
1000         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1001 };
1002
1003 #else
1004 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1005 #endif
1006
1007 static void tx53_fixup_flexcan(void *blob)
1008 {
1009         const char *baseboard = getenv("baseboard");
1010
1011         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1012                 return;
1013
1014         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch");
1015         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch");
1016 }
1017
1018 #ifdef CONFIG_SYS_TX53_HWREV_2
1019 void tx53_fixup_rtc(void *blob)
1020 {
1021         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1022         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1023 }
1024 #else
1025 static inline void tx53_fixup_rtc(void *blob)
1026 {
1027 }
1028 #endif
1029
1030 void ft_board_setup(void *blob, bd_t *bd)
1031 {
1032         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1033         fdt_fixup_ethernet(blob);
1034
1035         karo_fdt_enable_node(blob, "ipu", getenv("video_mode") != NULL);
1036         karo_fdt_fixup_touchpanel(blob);
1037         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1038         tx53_fixup_flexcan(blob);
1039         tx53_fixup_rtc(blob);
1040 }
1041 #endif