02afb607d811cae49b8cf8c21e55aed270043f01
[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S
1 #include <config.h>
2 #include <asm-offsets.h>
3 #include <configs/tx6.h>
4 #include <linux/linkage.h>
5 #include <asm/arch/imx-regs.h>
6 #include <generated/asm-offsets.h>
7
8 #ifndef CCM_CCR
9 #error asm-offsets not included
10 #endif
11
12 #define DEBUG_LED_BIT           20
13 #define LED_GPIO_BASE           GPIO2_BASE_ADDR
14 #define LED_MUX_OFFSET          0x0ec
15 #define LED_MUX_MODE            0x15
16
17 #define SDRAM_CLK               CONFIG_SYS_SDRAM_CLK
18
19 #ifdef PHYS_SDRAM_2_SIZE
20 #define SDRAM_SIZE              (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
21 #else
22 #define SDRAM_SIZE              PHYS_SDRAM_1_SIZE
23 #endif
24
25 #define CPU_2_BE_32(l)                  \
26         ((((l) << 24) & 0xFF000000) |   \
27         (((l) << 8) & 0x00FF0000) |     \
28         (((l) >> 8) & 0x0000FF00) |     \
29         (((l) >> 24) & 0x000000FF))
30
31 #define CHECK_DCD_ADDR(a)       (                       \
32         ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
33         ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||   \
34         ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
35         ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||  \
36         ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
37         ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
38         ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
39
40         .macro  mxc_dcd_item    addr, val
41         .ifne   CHECK_DCD_ADDR(\addr)
42         .word   CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
43         .else
44         .error  "Address \addr not accessible from DCD"
45         .endif
46         .endm
47
48 #define MXC_DCD_ITEM(addr, val)         mxc_dcd_item    (addr), (val)
49 #if PHYS_SDRAM_1_WIDTH == 16
50 #define MXC_DCD_ITEM_16(addr, val)              mxc_dcd_item    (addr), (val)
51 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
52 #else
53 #define MXC_DCD_ITEM_16(addr, val)
54 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
55 #endif
56 #if PHYS_SDRAM_1_WIDTH > 16
57 #define MXC_DCD_ITEM_32(addr, val)              mxc_dcd_item    (addr), (val)
58 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
59 #else
60 #define MXC_DCD_ITEM_32(addr, val)
61 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
62 #endif
63 #if PHYS_SDRAM_1_WIDTH == 64
64 #define MXC_DCD_ITEM_64(addr, val)              mxc_dcd_item    (addr), (val)
65 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
66 #else
67 #define MXC_DCD_ITEM_64(addr, val)
68 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask)
69 #endif
70
71 #define MXC_DCD_CMD_SZ_BYTE             1
72 #define MXC_DCD_CMD_SZ_SHORT            2
73 #define MXC_DCD_CMD_SZ_WORD             4
74 #define MXC_DCD_CMD_FLAG_WRITE          0x0
75 #define MXC_DCD_CMD_FLAG_CLR            0x1
76 #define MXC_DCD_CMD_FLAG_SET            0x3
77 #define MXC_DCD_CMD_FLAG_CHK_CLR        ((0 << 0) | (0 << 1))
78 #define MXC_DCD_CMD_FLAG_CHK_SET        ((0 << 0) | (1 << 1))
79 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR    ((1 << 0) | (0 << 1))
80 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET    ((1 << 0) | (1 << 1))
81
82 #define MXC_DCD_START                                                   \
83         .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
84 dcd_start:
85
86         .macro  MXC_DCD_END
87 1:
88         .ifgt   . - dcd_start - 1768
89         .error  "DCD too large!"
90         .endif
91 dcd_end:
92         .section ".pad"
93         .section ".text"
94         .endm
95
96 #define MXC_DCD_CMD_WRT(type, flags)                                    \
97 1:      .word   CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
98
99 #define MXC_DCD_CMD_CHK(type, flags, addr, mask)                        \
100 1:      .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
101                 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
102
103 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)             \
104 1:      .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
105                 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
106
107 #define MXC_DCD_CMD_NOP()                               \
108 1:      .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
109
110
111 #define CK_TO_NS(ck)    (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
112 #define NS_TO_CK(ns)    (((ns) * SDRAM_CLK + 999) / 1000)
113 #define NS_TO_CK10(ns)  DIV_ROUND_UP(NS_TO_CK(ns), 10)
114 #define PS_TO_CK(ps)    DIV_ROUND_UP(NS_TO_CK(ps), 1000)
115
116         .macro          CK_VAL, name, clks, offs, max
117         .iflt           \clks - \offs
118         .set            \name, 0
119         .else
120         .ifle           \clks - \offs - \max
121         .set            \name, \clks - \offs
122         .else
123         .error          "Value \clks out of range for parameter \name"
124         .endif
125         .endif
126         .endm
127
128         .macro          NS_VAL, name, ns, offs, max
129         .iflt           \ns - \offs
130         .set            \name, 0
131         .else
132         CK_VAL          \name, NS_TO_CK(\ns), \offs, \max
133         .endif
134         .endm
135
136         .macro          CK_MAX, name, ck1, ck2, offs, max
137         .ifgt           \ck1 - \ck2
138         CK_VAL          \name, \ck1, \offs, \max
139         .else
140         CK_VAL          \name, \ck2, \offs, \max
141         .endif
142         .endm
143
144 #define MDMISC_DDR_TYPE_DDR3            0
145 #define MDMISC_DDR_TYPE_LPDDR2          1
146 #define MDMISC_DDR_TYPE_DDR2            2
147
148 #define DIV_ROUND_UP(m,d)               (((m) + (d) - 1) / (d))
149
150 #define MDOR_CLK_PERIOD_ns              15258   /* base clock for MDOR values */
151
152 /* DDR3 SDRAM */
153 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
154 #define BANK_ADDR_BITS                  2
155 #else
156 #define BANK_ADDR_BITS                  1
157 #endif
158 #define SDRAM_BURST_LENGTH              8
159 #define RALAT                           5
160 #define WALAT                           0
161 #define BI_ON                           0
162 #define ADDR_MIRROR                     0
163 #define DDR_TYPE                        MDMISC_DDR_TYPE_DDR3
164
165 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII or MT41K128M16JT-125 */
166 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
167 #define CL_VAL  11
168 #define CWL_VAL 8
169 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
170 #define CL_VAL  9 // or 10
171 #define CWL_VAL 7
172 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
173 #define CL_VAL  7 // or 8
174 #define CWL_VAL 6
175 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
176 #define CL_VAL  6
177 #define CWL_VAL 5
178 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
179 #define CL_VAL  5
180 #define CWL_VAL 5
181 #else
182 #error SDRAM clock out of range: 303 .. 800
183 #endif
184
185 /* MDCFG0 0x0c */
186 NS_VAL  tRFC,   160, 1, 255             /* clks - 1 (0..255) */
187 CK_MAX  tXS,    NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
188 CK_MAX  tXP,    NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) (MT41K128M16JT: 6ns) */
189 CK_MAX  tXPDLL, NS_TO_CK(24), 10, 1, 15 /* clks - 1 (0..15) */
190 NS_VAL  tFAW,   50, 1, 31               /* clks - 1 (0..31) (MT41K128M16JT: 30ns) */
191 CK_VAL  tCL,    CL_VAL, 3, 8            /* clks - 3 (0..8) CAS Latency */
192
193 /* MDCFG1 0x10 */
194 CK_VAL  tRCD,   PS_TO_CK(13750), 1, 7   /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
195 CK_VAL  tRP,    PS_TO_CK(13750), 1, 7   /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
196 NS_VAL  tRC,    50, 1, 31               /* clks - 1 (0..31) (MT41K128M16JT: 49ns) */
197 CK_VAL  tRAS,   NS_TO_CK10(375), 1, 31  /* clks - 1 (0..31) (MT41K128M16JT: 3.5ns) */
198 CK_VAL  tRPA,   1, 0, 1                 /* clks     (0..1) */
199 NS_VAL  tWR,    15, 1, 15               /* clks - 1 (0..15) */
200 CK_VAL  tMRD,   4, 1, 15                /* clks - 1 (0..15) */
201 CK_VAL  tCWL,   CWL_VAL, 2, 6           /* clks - 2 (0..6) */
202
203 /* MDCFG2 0x14 */
204 CK_VAL  tDLLK,  512, 1, 511             /* clks - 1 (0..511) */ /* (Jedec Standard) */
205 CK_MAX  tRTP,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
206 CK_MAX  tWTR,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
207 CK_MAX  tRRD,   NS_TO_CK(10), 4, 1, 7   /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */
208
209 /* MDOR 0x30 */
210 CK_MAX  tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
211 #define tSDE_RST        (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
212 #define tRST_CKE        (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
213
214 /* MDOTC 0x08 */
215 CK_VAL  tAOFPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
216 CK_VAL  tAONPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
217 CK_VAL  tANPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
218 CK_VAL  tAXPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
219 CK_VAL  tODTLon tCWL, 0, 7              /* clks - 1 (0..7) */ /* CWL+AL-2 */
220 CK_VAL  tODTLoff tCWL, 0, 31            /* clks - 1 (0..31) */ /* CWL+AL-2 */
221
222 /* MDPDC 0x04 */
223 CK_MAX  tCKE,   NS_TO_CK(5), 3, 1, 7
224 CK_MAX  tCKSRX, NS_TO_CK(10), 5, 0, 7
225 CK_MAX  tCKSRE, NS_TO_CK(10), 5, 0, 7
226
227 #define PRCT            0
228 #define PWDT            5
229 #define SLOW_PD         0
230 #define BOTH_CS_PD      1
231
232 #define MDPDC_VAL_0     (       \
233         (PRCT << 28) |          \
234         (PRCT << 24) |          \
235         (tCKE << 16) |          \
236         (SLOW_PD << 7) |        \
237         (BOTH_CS_PD << 6) |     \
238         (tCKSRX << 3) |         \
239         (tCKSRE << 0)           \
240         )
241
242 #define MDPDC_VAL_1     (MDPDC_VAL_0 |          \
243         (PWDT << 12) |                          \
244         (PWDT << 8)                             \
245         )
246
247 #define ROW_ADDR_BITS                   14
248 #define COL_ADDR_BITS                   10
249
250 #define Rtt_Nom                         1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
251 #define Rtt_WR                          0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
252 #define DLL_DISABLE                     0
253
254         .iflt   tWR - 7
255         .set    mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ |    \
256                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
257                         ((tWR + 1 - 4) << 9) |                          \
258                         ((((tCL + 3) - 4) & 0x7) << 4) |                \
259                         ((((tCL + 3) - 4) & 0x8) >> 1))
260         .else
261         .set    mr0_val, ((1 << 8) /* DLL Reset */ |                    \
262                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
263                         (((tWR + 1) / 2) << 9) |        \
264                         ((((tCL + 3) - 4) & 0x7) << 4) | \
265                         ((((tCL + 3) - 4) & 0x8) >> 1))
266         .endif
267
268 #define mr1_val                         (                                       \
269                                          ((Rtt_Nom & 1) << 2) |                 \
270                                          (((Rtt_Nom >> 1) & 1) << 6) |          \
271                                          (((Rtt_Nom >> 2) & 1) << 9) |          \
272                                          (DLL_DISABLE << 0) |                   \
273                                         0)
274 #define mr2_val                         (                                       \
275                                          (Rtt_WR << 9) /* dynamic ODT */ |      \
276                                          (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
277                                          (1 << 6) | /* ASR: Automatic Self Refresh */ \
278                                          (((tCWL + 2) - 5) << 3) |              \
279                                         0)
280 #define mr3_val                         0
281
282 #define MDSCR_MRS_VAL(cs, mr, val)      (((val) << 16) |                \
283                                         (1 << 15) /* CON_REQ */ |       \
284                                         (3 << 4) /* MRS command */ |    \
285                                         ((cs) << 3) |                   \
286                                         ((mr) << 0) |                   \
287                                         0)
288
289 #define MDCFG0_VAL      (       \
290         (tRFC << 24) |          \
291         (tXS << 16) |           \
292         (tXP << 13) |           \
293         (tXPDLL << 9) |         \
294         (tFAW << 4) |           \
295         (tCL << 0))             \
296
297 #define MDCFG1_VAL      (       \
298         (tRCD << 29) |          \
299         (tRP << 26) |           \
300         (tRC << 21) |           \
301         (tRAS << 16) |          \
302         (tRPA << 15) |          \
303         (tWR << 9) |            \
304         (tMRD << 5) |           \
305         (tCWL << 0))            \
306
307 #define MDCFG2_VAL      (       \
308         (tDLLK << 16) |         \
309         (tRTP << 6) |           \
310         (tWTR << 3) |           \
311         (tRRD << 0))
312
313 #define BURST_LEN               (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
314
315 #define MDCTL_VAL               (((ROW_ADDR_BITS - 11) << 24) |         \
316                                 ((COL_ADDR_BITS - 9) << 20) |           \
317                                 (BURST_LEN << 19) |                     \
318                                 ((PHYS_SDRAM_1_WIDTH / 32) << 16) |     \
319                                 ((-1) << (32 - BANK_ADDR_BITS)))
320
321 #define MDMISC_WALAT(n)         (((n) & 3) << 16)
322 #define MDMISC_RALAT(n)         (((n) & 7) << 6)
323
324 #define MDMISC_VAL              ((ADDR_MIRROR << 19) |  \
325                                 MDMISC_WALAT(WALAT) |   \
326                                 (BI_ON << 12) |         \
327                                 (0x3 << 9) |            \
328                                 MDMISC_RALAT(RALAT) |   \
329                                 (DDR_TYPE << 3))
330
331 #define MDOR_VAL                ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
332
333 #define MDOTC_VAL               ((tAOFPD << 27) |       \
334                                 (tAONPD << 24) |        \
335                                 (tANPD << 20) |         \
336                                 (tAXPD << 16) |         \
337                                 (tODTLon << 12) |       \
338                                 (tODTLoff << 4))
339
340         .section ".ivt"
341 ivt_header:
342         .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
343 app_start_addr:
344         .long   _start
345         .long   0x0
346 dcd_ptr:
347         .long   dcd_hdr
348 boot_data_ptr:
349         .word   boot_data
350 self_ptr:
351         .word   ivt_header
352 app_code_csf:
353 #ifdef CONFIG_SECURE_BOOT
354         .word   __csf_data
355 #else
356         .word   0x0
357 #endif
358         .word   0x0
359 boot_data:
360         .long   CONFIG_SYS_TEXT_BASE
361 image_len:
362         .long   __uboot_img_len
363 plugin:
364         .word   0
365 ivt_end:
366 #define DCD_VERSION     0x40
367
368 #define DDR_SEL_VAL     3 /* DDR3 */
369 #if PHYS_SDRAM_1_WIDTH == 16
370 #define DSE1_VAL        6 /* Drive Strength for DATA lines */
371 #define DSE2_VAL        6 /* Drive Strength for ADDR/CMD lines */
372 #else
373 #define DSE1_VAL        6 /* Drive Strength for DATA lines */
374 #define DSE2_VAL        6 /* Drive Strength for ADDR/CMD lines */
375 #endif
376 #define ODT_VAL         2
377 #define DDR_PKE_VAL     0
378
379 #define DDR_SEL_SHIFT   18
380 #define DDR_MODE_SHIFT  17
381 #define ODT_SHIFT       8
382 #define DSE_SHIFT       3
383 #define HYS_SHIFT       16
384 #define PKE_SHIFT       12
385 #define PUE_SHIFT       13
386 #define PUS_SHIFT       14
387
388 #define DDR_SEL_MASK    (DDR_SEL_VAL << DDR_SEL_SHIFT)
389 #define DDR_MODE_MASK   (1 << DDR_MODE_SHIFT) /* differential input mode */
390 #define DSE1_MASK       (DSE1_VAL << DSE_SHIFT)
391 #define DSE2_MASK       (DSE2_VAL << DSE_SHIFT)
392 #define ODT_MASK        (ODT_VAL << ODT_SHIFT)
393 #define DDR_PKE_MASK    (DDR_PKE_VAL << PKE_SHIFT)
394
395 #define DQM_MASK        (DDR_MODE_MASK | DSE2_MASK)
396 #define SDQS_MASK       DSE2_MASK
397 #define SDODT_MASK      (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
398 #define SDCLK_MASK      (DDR_MODE_MASK | DSE2_MASK)
399 #define SDCKE_MASK      ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
400 #define DDR_ADDR_MASK   (ODT_MASK | DDR_MODE_MASK)
401 #define DDR_CTRL_MASK   (DDR_MODE_MASK | DSE2_MASK)
402
403 #define MMDC1_MDCTL                             0x021b0000
404 #define MMDC1_MDPDC                             0x021b0004
405 #define MMDC1_MDOTC                             0x021b0008
406 #define MMDC1_MDCFG0                            0x021b000c
407 #define MMDC1_MDCFG1                            0x021b0010
408 #define MMDC1_MDCFG2                            0x021b0014
409 #define MMDC1_MDMISC                            0x021b0018
410 #define MMDC1_MDSCR                             0x021b001c
411 #define MMDC1_MDREF                             0x021b0020
412 #define MMDC1_MDRWD                             0x021b002c
413 #define MMDC1_MDOR                              0x021b0030
414 #define MMDC1_MDASP                             0x021b0040
415
416 #define MMDC1_MAPSR                             0x021b0404
417
418 #define MMDC1_MPZQHWCTRL                        0x021b0800
419 #define MMDC1_MPWLGCR                           0x021b0808
420 #define MMDC1_MPWLDECTRL0                       0x021b080c
421 #define MMDC1_MPWLDECTRL1                       0x021b0810
422 #define MMDC1_MPWLDLST                          0x021b0814
423 #define MMDC1_MPODTCTRL                         0x021b0818
424 #define MMDC1_MPRDDQBY0DL                       0x021b081c
425 #define MMDC1_MPRDDQBY1DL                       0x021b0820
426 #define MMDC1_MPRDDQBY2DL                       0x021b0824
427 #define MMDC1_MPRDDQBY3DL                       0x021b0828
428 #define MMDC1_MPDGCTRL0                         0x021b083c
429 #define MMDC1_MPDGCTRL1                         0x021b0840
430 #define MMDC1_MPDGDLST0                         0x021b0844
431 #define MMDC1_MPRDDLCTL                         0x021b0848
432 #define MMDC1_MPRDDLST                          0x021b084c
433 #define MMDC1_MPWRDLCTL                         0x021b0850
434 #define MMDC1_MPWRDLST                          0x021b0854
435 #define MMDC1_MPRDDLHWCTL                       0x021b0860
436 #define MMDC1_MPWRDLHWCTL                       0x021b0864
437 #define MMDC1_MPPDCMPR2                         0x021b0890
438 #define MMDC1_MPSWDRDR0                         0x021b0898
439 #define MMDC1_MPSWDRDR1                         0x021b089c
440 #define MMDC1_MPSWDRDR2                         0x021b08a0
441 #define MMDC1_MPSWDRDR3                         0x021b08a4
442 #define MMDC1_MPSWDRDR4                         0x021b08a8
443 #define MMDC1_MPSWDRDR5                         0x021b08ac
444 #define MMDC1_MPSWDRDR6                         0x021b08b0
445 #define MMDC1_MPSWDRDR7                         0x021b08b4
446 #define MMDC1_MPMUR0                            0x021b08b8
447
448 #if PHYS_SDRAM_1_WIDTH == 64
449 #define MMDC2_MPWLGCR                           0x021b4808
450 #define MMDC2_MPWLDECTRL0                       0x021b480c
451 #define MMDC2_MPWLDECTRL1                       0x021b4810
452 #define MMDC2_MPWLDLST                          0x021b4814
453 #define MMDC2_MPODTCTRL                         0x021b4818
454 #define MMDC2_MPRDDQBY0DL                       0x021b481c
455 #define MMDC2_MPRDDQBY1DL                       0x021b4820
456 #define MMDC2_MPRDDQBY2DL                       0x021b4824
457 #define MMDC2_MPRDDQBY3DL                       0x021b4828
458 #define MMDC2_MPDGCTRL0                         0x021b483c
459 #define MMDC2_MPDGCTRL1                         0x021b4840
460 #define MMDC2_MPDGDLST0                         0x021b4844
461 #define MMDC2_MPRDDLCTL                         0x021b4848
462 #define MMDC2_MPRDDLST                          0x021b484c
463 #define MMDC2_MPWRDLCTL                         0x021b4850
464 #define MMDC2_MPWRDLST                          0x021b4854
465 #define MMDC2_MPRDDLHWCTL                       0x021b4860
466 #define MMDC2_MPWRDLHWCTL                       0x021b4864
467 #define MMDC2_MPRDDLHWST0                       0x021b4868
468 #define MMDC2_MPRDDLHWST1                       0x021b486c
469 #define MMDC2_MPWRDLHWST0                       0x021b4870
470 #define MMDC2_MPWRDLHWST1                       0x021b4874
471 #define MMDC2_MPWLHWERR                         0x021b4878
472 #define MMDC2_MPDGHWST0                         0x021b487c
473 #define MMDC2_MPDGHWST1                         0x021b4880
474 #define MMDC2_MPDGHWST2                         0x021b4884
475 #define MMDC2_MPDGHWST3                         0x021b4888
476 #define MMDC2_MPSWDAR0                          0x021b4894
477 #define MMDC2_MPSWDRDR0                         0x021b4898
478 #define MMDC2_MPSWDRDR1                         0x021b489c
479 #define MMDC2_MPSWDRDR2                         0x021b48a0
480 #define MMDC2_MPSWDRDR3                         0x021b48a4
481 #define MMDC2_MPSWDRDR4                         0x021b48a8
482 #define MMDC2_MPSWDRDR5                         0x021b48ac
483 #define MMDC2_MPSWDRDR6                         0x021b48b0
484 #define MMDC2_MPSWDRDR7                         0x021b48b4
485 #define MMDC2_MPMUR0                            0x021b48b8
486 #endif
487
488 #ifdef CONFIG_SOC_MX6Q
489 #define IOMUXC_GPR1                             0x020e0004
490 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20        0x020e00a0
491 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
492 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
493 #define IOMUXC_SW_MUX_CTL_PAD_GPIO16            0x020e0248
494 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e024c
495 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e02a8
496 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e02ac
497 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e02c0
498 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e02c4
499 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2         0x020e02c8
500 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e02d4
501 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e02d8
502 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02dc
503 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02e0
504 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e02e4
505 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e02ec
506 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e02f4
507 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e02f8
508 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e02fc
509 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0300
510 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e0304
511 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0308
512 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e030c
513 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0310
514 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e0314
515 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e0318
516
517 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20        0x020e03b4
518 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
519 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
520 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e050c
521 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0510
522 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0514
523 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e0518
524 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e051c
525 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e0520
526 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e0524
527 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0528
528 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e052c
529 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0530
530 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0534
531 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0538
532 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e053c
533 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0540
534 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0544
535 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0548
536 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e054c
537 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0550
538 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e0554
539 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0558
540 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e055c
541 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0560
542 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e0564
543 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0568
544 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e056c
545 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0578
546 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e057c
547 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0580
548 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e0584
549 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e0588
550 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e058c
551 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e0590
552 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e0594
553 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e0598
554 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e059c
555 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e05a0
556 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e05a8
557 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e05ac
558 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e05b0
559 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e05b4
560 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e05b8
561 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e05bc
562 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e05c0
563 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e05c4
564 #define IOMUXC_SW_PAD_CTL_PAD_GPIO16            0x020e0618
565 #define IOMUXC_SW_PAD_CTL_PAD_GPIO17            0x020e061c
566 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2         0x020e06b0
567 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
568 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
569 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
570 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0         0x020e0754
571 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0758
572 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1         0x020e075c
573 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2         0x020e0760
574 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3         0x020e0764
575 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0768
576 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4         0x020e076c
577 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e0770
578 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0774
579 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5         0x020e0778
580 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6         0x020e077c
581 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7         0x020e0780
582 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
583 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
584 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
585 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
586 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
587 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
588 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
589 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
590 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
591
592 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
593 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
594
595 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
596 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
597 #define TX6_I2C1_SEL_INP_VAL                    0
598 #endif
599
600 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
601 #define IOMUXC_GPR1                             0x020e0004
602 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20        0x020e0154
603 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
604 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
605 #define IOMUXC_SW_MUX_CTL_PAD_GPIO16            0x020e0214
606 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e0218
607 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e0330
608 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e032c
609 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e0314
610 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e0318
611 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2         0x020e031c
612 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e0270
613 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e026c
614 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02a8
615 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02a4
616 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e0274
617 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e027c
618 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e033c
619 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e0338
620 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e0284
621 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0288
622 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e028c
623 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0290
624 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e0294
625 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0298
626 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e029c
627 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e02a0
628
629 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20        0x020e0524
630 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
631 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
632 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e04d0
633 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0484
634 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0480
635 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e04cc
636 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e04c8
637 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e047c
638 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e04c4
639 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0478
640 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e0424
641 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0428
642 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0444
643 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0448
644 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e044c
645 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0450
646 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0454
647 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0458
648 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e045c
649 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0460
650 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e042c
651 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0430
652 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e0434
653 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0438
654 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e043c
655 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0440
656 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e0464
657 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0490
658 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e0494
659 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0498
660 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e049c
661 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e04ac
662 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e04a0
663 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e04a4
664 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e04b0
665 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e04a8
666 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e04b4
667 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e04b8
668 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e04bc
669 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e0470
670 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e04c0
671 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e0474
672 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e04d4
673 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e0488
674 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e04d8
675 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e048c
676 #define IOMUXC_SW_PAD_CTL_PAD_GPIO16            0x020e05e4
677 #define IOMUXC_SW_PAD_CTL_PAD_GPIO17            0x020e05e8
678 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2         0x020e0704
679 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
680 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
681 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
682 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0754
683 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0758
684 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e075c
685 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0760
686 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
687 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
688 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
689 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
690 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
691 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
692 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
693 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
694 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
695
696 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e08f8
697 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e08fc
698
699 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
700 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
701 #define TX6_I2C1_SEL_INP_VAL                    1
702 #endif
703
704 dcd_hdr:
705         MXC_DCD_START
706         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
707         /* setup I2C pads for PMIC */
708         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, 0x00000016)
709         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, 0x00000011)
710         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, 0x0000f079)
711         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, 0x0000f079)
712         MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL)
713         MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL)
714
715         /* ENET_REF_CLK */
716         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO16, 0x00000012)
717         /* ETN PHY nRST */
718         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, 0x00000015)
719         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, 0x000030b0)
720         /* ETN PHY Power */
721         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, 0x00000015)
722         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, 0x000030b0)
723         /* RESET_OUT GPIO_7_12 */
724         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
725         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0)
726
727         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
728         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */
729         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
730
731         MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
732
733         /* enable all relevant clocks... */
734         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
735         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
736         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
737         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
738         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
739         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
740         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
741         MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
742         MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
743         MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
744
745         /* IOMUX: */
746         MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
747         /* UART1 pad config */
748         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
749         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
750 #ifdef CONFIG_SOC_MX6Q
751         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
752 #else
753         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */
754 #endif
755         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
756         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
757         MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
758
759 #ifdef CONFIG_NAND_MXS
760         /* NAND */
761         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,    0x00000000)     /* NANDF_CLE: NANDF_CLE */
762         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,    0x00000000)     /* NANDF_ALE: NANDF_ALE */
763         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B,   0x00000000)     /* NANDF_WP_B: NANDF_WPn */
764         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY,  0x00000000)     /* NANDF_RB0: NANDF_READY0 */
765         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B,  0x00000000)     /* NANDF_CS0: NANDF_CS0 */
766         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD,     0x00000001)     /* SD4_CMD: NANDF_RDn */
767         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK,     0x00000001)     /* SD4_CLK: NANDF_WRn */
768         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000)     /* NANDF_D0: NANDF_D0 */
769         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000)     /* NANDF_D1: NANDF_D1 */
770         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000)     /* NANDF_D2: NANDF_D2 */
771         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000)     /* NANDF_D3: NANDF_D3 */
772         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000)     /* NANDF_D4: NANDF_D4 */
773         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000)     /* NANDF_D5: NANDF_D5 */
774         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000)     /* NANDF_D6: NANDF_D6 */
775         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000)     /* NANDF_D7: NANDF_D7 */
776 #endif
777         /* ext. mem CS */
778         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
779         /* DRAM_DQM[0..7] */
780         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
781         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
782         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
783         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
784         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
785         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
786         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
787         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
788
789         /* DRAM_A[0..15] */
790         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
791         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
792         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
793         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
794         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
795         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
796         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
797         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
798         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
799         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
800         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
801         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
802         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
803         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
804         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
805         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
806         /* DRAM_CAS */
807         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
808         /* DRAM_RAS */
809         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
810         /* DRAM_SDCLK[0..1] */
811         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
812         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
813         /* DRAM_RESET */
814         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
815         /* DRAM_SDCKE[0..1] */
816         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
817         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
818         /* DRAM_SDBA[0..2] */
819         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
820         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
821         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
822         /* DRAM_SDODT[0..1] */
823         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
824         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
825         /* DRAM_B[0..7]DS */
826         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
827         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
828         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE1_MASK)
829         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE1_MASK)
830         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE1_MASK)
831         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE1_MASK)
832         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE1_MASK)
833         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE1_MASK)
834         /* ADDDS */
835         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
836         /* DDRMODE_CTL */
837         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
838         /* DDRPKE */
839         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
840         /* DDRMODE */
841         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
842         /* CTLDS */
843         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
844         /* DDR_TYPE */
845         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
846         /* DDRPK */
847         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
848         /* DDRHYS */
849         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
850
851 #ifdef CONFIG_SOC_MX6Q
852         /* TERM_CTL[0..7] */
853         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
854         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
855         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
856         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
857         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
858         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
859         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
860         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
861 #endif
862 #if PHYS_SDRAM_1_WIDTH > 16
863 #define DO_DDR_CALIB
864 #endif
865         /* SDRAM initialization */
866 #define WL_DLY_DQS_VAL  30
867 #define WL_DLY_DQS0     (WL_DLY_DQS_VAL + 0)
868 #define WL_DLY_DQS1     (WL_DLY_DQS_VAL + 0)
869 #define WL_DLY_DQS2     (WL_DLY_DQS_VAL + 0)
870 #define WL_DLY_DQS3     (WL_DLY_DQS_VAL + 0)
871 #define WL_DLY_DQS4     (WL_DLY_DQS_VAL + 0)
872 #define WL_DLY_DQS5     (WL_DLY_DQS_VAL + 0)
873 #define WL_DLY_DQS6     (WL_DLY_DQS_VAL + 0)
874 #define WL_DLY_DQS7     (WL_DLY_DQS_VAL + 0)
875
876         /* ZQ calibration */
877         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
878         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
879         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
880
881         MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
882         MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
883         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
884         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
885
886         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43240334)
887         MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x0324031a)
888         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x43340344)
889         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x03280276)
890
891         MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
892         MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
893         MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
894         MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
895
896         /* MPRDDQBY[0..7]DL */
897         MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
898         MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
899         MXC_DCD_ITEM_32(MMDC1_MPRDDQBY2DL, 0x33333333)
900         MXC_DCD_ITEM_32(MMDC1_MPRDDQBY3DL, 0x33333333)
901         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
902         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
903         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
904         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
905 #define MPMUR_FRC_MSR   (1 << 11)
906         MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
907         MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
908         /* MDMISC */
909         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
910         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
911         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
912
913         /* MSDSCR Conf Req */
914         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
915         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
916         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
917
918         /* MDCTL */
919         MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
920 #if BANK_ADDR_BITS > 1
921         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (3 << 30))
922 #else
923         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (1 << 30))
924 #endif
925         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
926
927         MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
928         MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
929         MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
930         MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2)
931         MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
932         MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
933         MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
934         MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
935
936         /* CS0 MRS: */
937         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
938         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
939         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
940         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
941 #if BANK_ADDR_BITS > 1
942         /* CS1 MRS: */
943         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
944         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
945         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
946         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
947 #endif
948         MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
949         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
950
951         MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222)
952         MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
953
954         /* DDR3 calibration */
955         MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
956         MXC_DCD_ITEM(MMDC1_MAPSR, 1)
957
958 #ifdef DO_DDR_CALIB
959         /* ZQ calibration */
960         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
961         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
962         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
963
964         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
965         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
966         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
967 #endif
968         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
969 #if BANK_ADDR_BITS > 1
970         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
971 #endif
972
973         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
974         /* DRAM_SDQS[0..7] pad config */
975         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
976         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
977         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
978         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
979         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
980         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
981         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
982         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
983 #ifdef DO_DDR_CALIB
984         /* Read delay calibration */
985         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
986         MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
987         MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
988         MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000013)
989         MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
990         MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
991         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
992
993         /* Write delay calibration */
994         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
995         MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
996         MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
997         MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
998 #if PHYS_SDRAM_1_WIDTH == 64
999         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1000
1001         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
1002         MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
1003         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
1004 #endif
1005         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1006 #endif /* DO_DDR_CALIB */
1007         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
1008 #if BANK_ADDR_BITS > 1
1009         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
1010 #endif
1011         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
1012         MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
1013         MXC_DCD_ITEM(MMDC1_MAPSR, (16 << 8))
1014         MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
1015
1016         /* MDSCR: Normal operation */
1017         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
1018         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
1019         MXC_DCD_END