karo: tx6: disable gpmi clk before changing podf and clk_sel
[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S
1 #include <config.h>
2 #include <asm-offsets.h>
3 #include <configs/tx6.h>
4 #include <linux/linkage.h>
5 #include <asm/arch/imx-regs.h>
6 #include <generated/asm-offsets.h>
7
8 #ifndef CCM_CCR
9 #error asm-offsets not included
10 #endif
11
12 #define DEBUG_LED_BIT           20
13 #define LED_GPIO_BASE           GPIO2_BASE_ADDR
14 #define LED_MUX_OFFSET          0x0ec
15 #define LED_MUX_MODE            0x15
16
17 #define SDRAM_CLK               CONFIG_SYS_SDRAM_CLK
18
19 #ifdef PHYS_SDRAM_2_SIZE
20 #define SDRAM_SIZE              (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
21 #else
22 #define SDRAM_SIZE              PHYS_SDRAM_1_SIZE
23 #endif
24
25 #define CCGR(m)                 (3 << ((m) * 2))
26
27 #define CPU_2_BE_32(l)                  \
28         ((((l) << 24) & 0xFF000000) |   \
29         (((l) << 8) & 0x00FF0000) |     \
30         (((l) >> 8) & 0x0000FF00) |     \
31         (((l) >> 24) & 0x000000FF))
32
33 #define CHECK_DCD_ADDR(a)       (                                       \
34         ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
35         ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||           \
36         ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
37         ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||          \
38         ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ ||         \
39         ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
40         ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
41         ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
42
43         .macro  mxc_dcd_item    addr, val
44         .ifne   CHECK_DCD_ADDR(\addr)
45         .word   CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
46         .else
47         .error  "Address \addr not accessible from DCD"
48         .endif
49         .endm
50
51 #define MXC_DCD_ITEM(addr, val)         mxc_dcd_item    (addr), (val)
52 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
53 #define MXC_DCD_ITEM_16(addr, val)      mxc_dcd_item    (addr), (val)
54 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
55 #else
56 #define MXC_DCD_ITEM_16(addr, val)
57 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
58 #endif
59 #if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
60 #define MXC_DCD_ITEM_32(addr, val)      mxc_dcd_item    (addr), (val)
61 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
62 #else
63 #define MXC_DCD_ITEM_32(addr, val)
64 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
65 #endif
66 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
67 #define MXC_DCD_ITEM_64(addr, val)      mxc_dcd_item    (addr), (val)
68 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
69 #else
70 #define MXC_DCD_ITEM_64(addr, val)
71 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask)
72 #endif
73
74 #define MXC_DCD_CMD_SZ_BYTE             1
75 #define MXC_DCD_CMD_SZ_SHORT            2
76 #define MXC_DCD_CMD_SZ_WORD             4
77 #define MXC_DCD_CMD_FLAG_WRITE          0x0
78 #define MXC_DCD_CMD_FLAG_CLR            0x1
79 #define MXC_DCD_CMD_FLAG_SET            0x3
80 #define MXC_DCD_CMD_FLAG_CHK_CLR        ((0 << 0) | (0 << 1))
81 #define MXC_DCD_CMD_FLAG_CHK_SET        ((0 << 0) | (1 << 1))
82 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR    ((1 << 0) | (0 << 1))
83 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET    ((1 << 0) | (1 << 1))
84
85 #define MXC_DCD_START                                                   \
86         .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
87 dcd_start:
88
89         .macro  MXC_DCD_END
90 1:
91         .ifgt   . - dcd_start - 1768
92         .error  "DCD too large!"
93         .endif
94 dcd_end:
95         .section ".pad"
96         .section ".text"
97         .endm
98
99 #define MXC_DCD_CMD_WRT(type, flags)                                    \
100 1:      .word   CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
101
102 #define MXC_DCD_CMD_CHK(type, flags, addr, mask)                        \
103 1:      .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
104                 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
105
106 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)             \
107 1:      .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
108                 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
109
110 #define MXC_DCD_CMD_NOP()                               \
111 1:      .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
112
113
114 #define CK_TO_NS(ck)    (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
115 #define NS_TO_CK(ns)    (((ns) * SDRAM_CLK + 999) / 1000)
116 #define NS_TO_CK10(ns)  DIV_ROUND_UP(NS_TO_CK(ns), 10)
117 #define PS_TO_CK(ps)    DIV_ROUND_UP(NS_TO_CK(ps), 1000)
118
119         .macro          CK_VAL, name, clks, offs, max
120         .iflt           \clks - \offs
121         .set            \name, 0
122         .else
123         .ifle           \clks - \offs - \max
124         .set            \name, \clks - \offs
125         .else
126         .error          "Value \clks out of range for parameter \name"
127         .endif
128         .endif
129         .endm
130
131         .macro          NS_VAL, name, ns, offs, max
132         .iflt           \ns - \offs
133         .set            \name, 0
134         .else
135         CK_VAL          \name, NS_TO_CK(\ns), \offs, \max
136         .endif
137         .endm
138
139         .macro          CK_MAX, name, ck1, ck2, offs, max
140         .ifgt           \ck1 - \ck2
141         CK_VAL          \name, \ck1, \offs, \max
142         .else
143         CK_VAL          \name, \ck2, \offs, \max
144         .endif
145         .endm
146
147 #define MDMISC_DDR_TYPE_DDR3            0
148 #define MDMISC_DDR_TYPE_LPDDR2          1
149 #define MDMISC_DDR_TYPE_DDR2            2
150
151 #define DIV_ROUND_UP(m,d)               (((m) + (d) - 1) / (d))
152
153 #define MDOR_CLK_PERIOD_ns              15258   /* base clock for MDOR values */
154
155 /* DDR3 SDRAM */
156 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
157 #define BANK_ADDR_BITS                  2
158 #else
159 #define BANK_ADDR_BITS                  1
160 #endif
161 #define SDRAM_BURST_LENGTH              8
162 #define RALAT                           5
163 #define WALAT                           0
164 #define BI_ON                           0
165 #define ADDR_MIRROR                     0
166 #define DDR_TYPE                        MDMISC_DDR_TYPE_DDR3
167
168 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII or MT41K128M16JT-125 */
169 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
170 #define CL_VAL  11
171 #define CWL_VAL 8
172 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
173 #define CL_VAL  9 // or 10
174 #define CWL_VAL 7
175 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
176 #define CL_VAL  7 // or 8
177 #define CWL_VAL 6
178 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
179 #define CL_VAL  6
180 #define CWL_VAL 5
181 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
182 #define CL_VAL  5
183 #define CWL_VAL 5
184 #else
185 #error SDRAM clock out of range: 303 .. 800
186 #endif
187
188 /* MDCFG0 0x0c */
189 NS_VAL  tRFC,   160, 1, 255             /* clks - 1 (0..255) */
190 CK_MAX  tXS,    NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
191 CK_MAX  tXP,    NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) (MT41K128M16JT: 6ns) */
192 CK_MAX  tXPDLL, NS_TO_CK(24), 10, 1, 15 /* clks - 1 (0..15) */
193 NS_VAL  tFAW,   50, 1, 31               /* clks - 1 (0..31) (MT41K128M16JT: 30ns) */
194 CK_VAL  tCL,    CL_VAL, 3, 8            /* clks - 3 (0..8) CAS Latency */
195
196 /* MDCFG1 0x10 */
197 CK_VAL  tRCD,   PS_TO_CK(13750), 1, 7   /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
198 CK_VAL  tRP,    PS_TO_CK(13750), 1, 7   /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
199 NS_VAL  tRC,    50, 1, 31               /* clks - 1 (0..31) (MT41K128M16JT: 49ns) */
200 CK_VAL  tRAS,   NS_TO_CK10(375), 1, 31  /* clks - 1 (0..31) (MT41K128M16JT: 3.5ns) */
201 CK_VAL  tRPA,   1, 0, 1                 /* clks     (0..1) */
202 NS_VAL  tWR,    15, 1, 15               /* clks - 1 (0..15) */
203 CK_VAL  tMRD,   4, 1, 15                /* clks - 1 (0..15) */
204 CK_VAL  tCWL,   CWL_VAL, 2, 6           /* clks - 2 (0..6) */
205
206 /* MDCFG2 0x14 */
207 CK_VAL  tDLLK,  512, 1, 511             /* clks - 1 (0..511) */ /* (Jedec Standard) */
208 CK_MAX  tRTP,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
209 CK_MAX  tWTR,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
210 CK_MAX  tRRD,   NS_TO_CK(10), 4, 1, 7   /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */
211
212 /* MDOR 0x30 */
213 CK_MAX  tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
214 #define tSDE_RST        (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
215 #define tRST_CKE        (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
216
217 /* MDOTC 0x08 */
218 CK_VAL  tAOFPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
219 CK_VAL  tAONPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
220 CK_VAL  tANPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
221 CK_VAL  tAXPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
222 CK_VAL  tODTLon tCWL, 0, 7              /* clks - 1 (0..7) */ /* CWL+AL-2 */
223 CK_VAL  tODTLoff tCWL, 0, 31            /* clks - 1 (0..31) */ /* CWL+AL-2 */
224
225 /* MDPDC 0x04 */
226 CK_MAX  tCKE,   NS_TO_CK(5), 3, 1, 7
227 CK_MAX  tCKSRX, NS_TO_CK(10), 5, 0, 7
228 CK_MAX  tCKSRE, NS_TO_CK(10), 5, 0, 7
229
230 #define PRCT            0
231 #define PWDT            5
232 #define SLOW_PD         0
233 #define BOTH_CS_PD      1
234
235 #define MDPDC_VAL_0     (       \
236         (PRCT << 28) |          \
237         (PRCT << 24) |          \
238         (tCKE << 16) |          \
239         (SLOW_PD << 7) |        \
240         (BOTH_CS_PD << 6) |     \
241         (tCKSRX << 3) |         \
242         (tCKSRE << 0)           \
243         )
244
245 #define MDPDC_VAL_1     (MDPDC_VAL_0 |          \
246         (PWDT << 12) |                          \
247         (PWDT << 8)                             \
248         )
249
250 #define ROW_ADDR_BITS                   14
251 #define COL_ADDR_BITS                   10
252
253 #define Rtt_Nom                         1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
254 #define Rtt_WR                          0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
255 #define DLL_DISABLE                     0
256
257         .iflt   tWR - 7
258         .set    mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ |    \
259                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
260                         ((tWR + 1 - 4) << 9) |                          \
261                         ((((tCL + 3) - 4) & 0x7) << 4) |                \
262                         ((((tCL + 3) - 4) & 0x8) >> 1))
263         .else
264         .set    mr0_val, ((1 << 8) /* DLL Reset */ |                    \
265                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
266                         (((tWR + 1) / 2) << 9) |        \
267                         ((((tCL + 3) - 4) & 0x7) << 4) | \
268                         ((((tCL + 3) - 4) & 0x8) >> 1))
269         .endif
270
271 #define mr1_val                         (                                       \
272                                          ((Rtt_Nom & 1) << 2) |                 \
273                                          (((Rtt_Nom >> 1) & 1) << 6) |          \
274                                          (((Rtt_Nom >> 2) & 1) << 9) |          \
275                                          (DLL_DISABLE << 0) |                   \
276                                         0)
277 #define mr2_val                         (                                       \
278                                          (Rtt_WR << 9) /* dynamic ODT */ |      \
279                                          (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
280                                          (1 << 6) | /* ASR: Automatic Self Refresh */ \
281                                          (((tCWL + 2) - 5) << 3) |              \
282                                         0)
283 #define mr3_val                         0
284
285 #define MDSCR_MRS_VAL(cs, mr, val)      (((val) << 16) |                \
286                                         (1 << 15) /* CON_REQ */ |       \
287                                         (3 << 4) /* MRS command */ |    \
288                                         ((cs) << 3) |                   \
289                                         ((mr) << 0) |                   \
290                                         0)
291
292 #define MDCFG0_VAL      (       \
293         (tRFC << 24) |          \
294         (tXS << 16) |           \
295         (tXP << 13) |           \
296         (tXPDLL << 9) |         \
297         (tFAW << 4) |           \
298         (tCL << 0))             \
299
300 #define MDCFG1_VAL      (       \
301         (tRCD << 29) |          \
302         (tRP << 26) |           \
303         (tRC << 21) |           \
304         (tRAS << 16) |          \
305         (tRPA << 15) |          \
306         (tWR << 9) |            \
307         (tMRD << 5) |           \
308         (tCWL << 0))            \
309
310 #define MDCFG2_VAL      (       \
311         (tDLLK << 16) |         \
312         (tRTP << 6) |           \
313         (tWTR << 3) |           \
314         (tRRD << 0))
315
316 #define BURST_LEN               (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
317
318 #define MDCTL_VAL               (((ROW_ADDR_BITS - 11) << 24) |         \
319                                 ((COL_ADDR_BITS - 9) << 20) |           \
320                                 (BURST_LEN << 19) |                     \
321                                 ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \
322                                 ((-1) << (32 - BANK_ADDR_BITS)))
323
324 #define MDMISC_WALAT(n)         (((n) & 3) << 16)
325 #define MDMISC_RALAT(n)         (((n) & 7) << 6)
326
327 #define MDMISC_VAL              ((ADDR_MIRROR << 19) |  \
328                                 MDMISC_WALAT(WALAT) |   \
329                                 (BI_ON << 12) |         \
330                                 (0x3 << 9) |            \
331                                 MDMISC_RALAT(RALAT) |   \
332                                 (DDR_TYPE << 3))
333
334 #define MDOR_VAL                ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
335
336 #define MDOTC_VAL               ((tAOFPD << 27) |       \
337                                 (tAONPD << 24) |        \
338                                 (tANPD << 20) |         \
339                                 (tAXPD << 16) |         \
340                                 (tODTLon << 12) |       \
341                                 (tODTLoff << 4))
342
343         .section ".ivt"
344 ivt_header:
345         .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
346 app_start_addr:
347         .long   _start
348         .long   0x0
349 dcd_ptr:
350         .long   dcd_hdr
351 boot_data_ptr:
352         .word   boot_data
353 self_ptr:
354         .word   ivt_header
355 app_code_csf:
356 #ifdef CONFIG_SECURE_BOOT
357         .word   __csf_data
358 #else
359         .word   0x0
360 #endif
361         .word   0x0
362 boot_data:
363         .long   CONFIG_SYS_TEXT_BASE
364 image_len:
365         .long   __uboot_img_len
366 plugin:
367         .word   0
368 ivt_end:
369 #define DCD_VERSION     0x40
370
371 #define DDR_SEL_VAL     3 /* DDR3 */
372 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
373 #define DSE1_VAL        6 /* Drive Strength for DATA lines */
374 #define DSE2_VAL        6 /* Drive Strength for ADDR/CMD lines */
375 #else
376 #define DSE1_VAL        6 /* Drive Strength for DATA lines */
377 #define DSE2_VAL        6 /* Drive Strength for ADDR/CMD lines */
378 #endif
379 #define ODT_VAL         2
380 #define DDR_PKE_VAL     0
381
382 #define DDR_SEL_SHIFT   18
383 #define DDR_MODE_SHIFT  17
384 #define ODT_SHIFT       8
385 #define DSE_SHIFT       3
386 #define HYS_SHIFT       16
387 #define PKE_SHIFT       12
388 #define PUE_SHIFT       13
389 #define PUS_SHIFT       14
390
391 #define DDR_SEL_MASK    (DDR_SEL_VAL << DDR_SEL_SHIFT)
392 #define DDR_MODE_MASK   (1 << DDR_MODE_SHIFT) /* differential input mode */
393 #define DSE1_MASK       (DSE1_VAL << DSE_SHIFT)
394 #define DSE2_MASK       (DSE2_VAL << DSE_SHIFT)
395 #define ODT_MASK        (ODT_VAL << ODT_SHIFT)
396 #define DDR_PKE_MASK    (DDR_PKE_VAL << PKE_SHIFT)
397
398 #define DQM_MASK        (DDR_MODE_MASK | DSE2_MASK)
399 #define SDQS_MASK       DSE2_MASK
400 #define SDODT_MASK      (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
401 #define SDCLK_MASK      (DDR_MODE_MASK | DSE2_MASK)
402 #define SDCKE_MASK      ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
403 #define DDR_ADDR_MASK   (ODT_MASK | DDR_MODE_MASK)
404 #define DDR_CTRL_MASK   (DDR_MODE_MASK | DSE2_MASK)
405
406 #define MMDC1_MDCTL                             0x021b0000
407 #define MMDC1_MDPDC                             0x021b0004
408 #define MMDC1_MDOTC                             0x021b0008
409 #define MMDC1_MDCFG0                            0x021b000c
410 #define MMDC1_MDCFG1                            0x021b0010
411 #define MMDC1_MDCFG2                            0x021b0014
412 #define MMDC1_MDMISC                            0x021b0018
413 #define MMDC1_MDSCR                             0x021b001c
414 #define MMDC1_MDREF                             0x021b0020
415 #define MMDC1_MDRWD                             0x021b002c
416 #define MMDC1_MDOR                              0x021b0030
417 #define MMDC1_MDASP                             0x021b0040
418
419 #define MMDC1_MAPSR                             0x021b0404
420
421 #define MMDC1_MPZQHWCTRL                        0x021b0800
422 #define MMDC1_MPWLGCR                           0x021b0808
423 #define MMDC1_MPWLDECTRL0                       0x021b080c
424 #define MMDC1_MPWLDECTRL1                       0x021b0810
425 #define MMDC1_MPWLDLST                          0x021b0814
426 #define MMDC1_MPODTCTRL                         0x021b0818
427 #define MMDC1_MPRDDQBY0DL                       0x021b081c
428 #define MMDC1_MPRDDQBY1DL                       0x021b0820
429 #define MMDC1_MPRDDQBY2DL                       0x021b0824
430 #define MMDC1_MPRDDQBY3DL                       0x021b0828
431 #define MMDC1_MPDGCTRL0                         0x021b083c
432 #define MMDC1_MPDGCTRL1                         0x021b0840
433 #define MMDC1_MPDGDLST0                         0x021b0844
434 #define MMDC1_MPRDDLCTL                         0x021b0848
435 #define MMDC1_MPRDDLST                          0x021b084c
436 #define MMDC1_MPWRDLCTL                         0x021b0850
437 #define MMDC1_MPWRDLST                          0x021b0854
438 #define MMDC1_MPRDDLHWCTL                       0x021b0860
439 #define MMDC1_MPWRDLHWCTL                       0x021b0864
440 #define MMDC1_MPDGHWST0                         0x021b087c
441 #define MMDC1_MPDGHWST1                         0x021b0880
442 #define MMDC1_MPPDCMPR2                         0x021b0890
443 #define MMDC1_MPDGHWST2                         0x021b0884
444 #define MMDC1_MPDGHWST3                         0x021b0888
445 #define MMDC1_MPSWDRDR0                         0x021b0898
446 #define MMDC1_MPSWDRDR1                         0x021b089c
447 #define MMDC1_MPSWDRDR2                         0x021b08a0
448 #define MMDC1_MPSWDRDR3                         0x021b08a4
449 #define MMDC1_MPSWDRDR4                         0x021b08a8
450 #define MMDC1_MPSWDRDR5                         0x021b08ac
451 #define MMDC1_MPSWDRDR6                         0x021b08b0
452 #define MMDC1_MPSWDRDR7                         0x021b08b4
453 #define MMDC1_MPMUR0                            0x021b08b8
454
455 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
456 #define MMDC2_MPWLGCR                           0x021b4808
457 #define MMDC2_MPWLDECTRL0                       0x021b480c
458 #define MMDC2_MPWLDECTRL1                       0x021b4810
459 #define MMDC2_MPWLDLST                          0x021b4814
460 #define MMDC2_MPODTCTRL                         0x021b4818
461 #define MMDC2_MPRDDQBY0DL                       0x021b481c
462 #define MMDC2_MPRDDQBY1DL                       0x021b4820
463 #define MMDC2_MPRDDQBY2DL                       0x021b4824
464 #define MMDC2_MPRDDQBY3DL                       0x021b4828
465 #define MMDC2_MPDGCTRL0                         0x021b483c
466 #define MMDC2_MPDGCTRL1                         0x021b4840
467 #define MMDC2_MPDGDLST0                         0x021b4844
468 #define MMDC2_MPRDDLCTL                         0x021b4848
469 #define MMDC2_MPRDDLST                          0x021b484c
470 #define MMDC2_MPWRDLCTL                         0x021b4850
471 #define MMDC2_MPWRDLST                          0x021b4854
472 #define MMDC2_MPRDDLHWCTL                       0x021b4860
473 #define MMDC2_MPWRDLHWCTL                       0x021b4864
474 #define MMDC2_MPRDDLHWST0                       0x021b4868
475 #define MMDC2_MPRDDLHWST1                       0x021b486c
476 #define MMDC2_MPWRDLHWST0                       0x021b4870
477 #define MMDC2_MPWRDLHWST1                       0x021b4874
478 #define MMDC2_MPWLHWERR                         0x021b4878
479 #define MMDC2_MPDGHWST0                         0x021b487c
480 #define MMDC2_MPDGHWST1                         0x021b4880
481 #define MMDC2_MPDGHWST2                         0x021b4884
482 #define MMDC2_MPDGHWST3                         0x021b4888
483 #define MMDC2_MPSWDAR0                          0x021b4894
484 #define MMDC2_MPSWDRDR0                         0x021b4898
485 #define MMDC2_MPSWDRDR1                         0x021b489c
486 #define MMDC2_MPSWDRDR2                         0x021b48a0
487 #define MMDC2_MPSWDRDR3                         0x021b48a4
488 #define MMDC2_MPSWDRDR4                         0x021b48a8
489 #define MMDC2_MPSWDRDR5                         0x021b48ac
490 #define MMDC2_MPSWDRDR6                         0x021b48b0
491 #define MMDC2_MPSWDRDR7                         0x021b48b4
492 #define MMDC2_MPMUR0                            0x021b48b8
493 #endif
494
495 #ifdef CONFIG_SOC_MX6Q
496 #define IOMUXC_GPR1                             0x020e0004
497 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20        0x020e00a0
498 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
499 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
500 #define IOMUXC_SW_MUX_CTL_PAD_GPIO16            0x020e0248
501 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e024c
502 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e02a8
503 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e02ac
504 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e02c0
505 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e02c4
506 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2         0x020e02c8
507 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e02d4
508 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e02d8
509 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02dc
510 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02e0
511 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e02e4
512 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e02ec
513 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e02f4
514 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e02f8
515 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e02fc
516 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0300
517 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e0304
518 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0308
519 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e030c
520 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0310
521 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e0314
522 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e0318
523
524 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20        0x020e03b4
525 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
526 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
527 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e050c
528 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0510
529 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0514
530 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e0518
531 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e051c
532 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e0520
533 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e0524
534 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0528
535 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e052c
536 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0530
537 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0534
538 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0538
539 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e053c
540 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0540
541 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0544
542 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0548
543 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e054c
544 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0550
545 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e0554
546 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0558
547 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e055c
548 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0560
549 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e0564
550 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0568
551 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e056c
552 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0578
553 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e057c
554 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0580
555 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e0584
556 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e0588
557 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e058c
558 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e0590
559 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e0594
560 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e0598
561 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e059c
562 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e05a0
563 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e05a8
564 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e05ac
565 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e05b0
566 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e05b4
567 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e05b8
568 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e05bc
569 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e05c0
570 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e05c4
571 #define IOMUXC_SW_PAD_CTL_PAD_GPIO16            0x020e0618
572 #define IOMUXC_SW_PAD_CTL_PAD_GPIO17            0x020e061c
573 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2         0x020e06b0
574 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
575 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
576 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
577 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0         0x020e0754
578 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0758
579 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1         0x020e075c
580 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2         0x020e0760
581 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3         0x020e0764
582 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0768
583 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4         0x020e076c
584 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e0770
585 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0774
586 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5         0x020e0778
587 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6         0x020e077c
588 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7         0x020e0780
589 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
590 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
591 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
592 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
593 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
594 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
595 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
596 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
597 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
598
599 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
600 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
601
602 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
603 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
604 #define TX6_I2C1_SEL_INP_VAL                    0
605 #elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
606 #define IOMUXC_GPR1                             0x020e0004
607 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20        0x020e0154
608 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
609 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
610 #define IOMUXC_SW_MUX_CTL_PAD_GPIO16            0x020e0214
611 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e0218
612 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e0330
613 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e032c
614 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e0314
615 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e0318
616 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2         0x020e031c
617 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e0270
618 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e026c
619 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02a8
620 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02a4
621 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e0274
622 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e027c
623 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e033c
624 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e0338
625 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e0284
626 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0288
627 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e028c
628 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0290
629 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e0294
630 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0298
631 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e029c
632 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e02a0
633
634 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20        0x020e0524
635 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
636 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
637 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e04d0
638 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0484
639 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0480
640 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e04cc
641 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e04c8
642 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e047c
643 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e04c4
644 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0478
645 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e0424
646 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0428
647 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0444
648 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0448
649 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e044c
650 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0450
651 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0454
652 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0458
653 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e045c
654 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0460
655 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e042c
656 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0430
657 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e0434
658 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0438
659 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e043c
660 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0440
661 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e0464
662 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0490
663 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e0494
664 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0498
665 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e049c
666 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e04ac
667 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e04a0
668 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e04a4
669 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e04b0
670 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e04a8
671 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e04b4
672 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e04b8
673 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e04bc
674 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e0470
675 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e04c0
676 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e0474
677 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e04d4
678 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e0488
679 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e04d8
680 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e048c
681 #define IOMUXC_SW_PAD_CTL_PAD_GPIO16            0x020e05e4
682 #define IOMUXC_SW_PAD_CTL_PAD_GPIO17            0x020e05e8
683 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2         0x020e0704
684 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
685 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
686 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
687 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0754
688 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0758
689 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e075c
690 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0760
691 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
692 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
693 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
694 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
695 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
696 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
697 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
698 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
699 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
700
701 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e08f8
702 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e08fc
703
704 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
705 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
706 #define TX6_I2C1_SEL_INP_VAL                    1
707 #endif
708
709 dcd_hdr:
710         MXC_DCD_START
711         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
712         /* setup I2C pads for PMIC */
713         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, 0x00000016)
714         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, 0x00000011)
715         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, 0x0000f079)
716         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, 0x0000f079)
717         MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL)
718         MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL)
719
720         /* ENET_REF_CLK */
721         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO16, 0x00000012)
722         /* ETN PHY nRST */
723         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, 0x00000015)
724         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, 0x000030b0)
725         /* ETN PHY Power */
726         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, 0x00000015)
727         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, 0x000030b0)
728         /* RESET_OUT GPIO_7_12 */
729         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
730         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0)
731 #ifndef CONFIG_TX6_EMMC
732         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR)
733         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
734         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
735         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
736         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
737         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
738         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
739         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
740         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
741 #endif
742         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 (0x00029148) */
743         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 (0x00029148) */
744         MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
745
746         /* enable all relevant clocks... */
747         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
748         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */
749         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */
750         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */
751 //      MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR()) /* 0x3ff00000 default: 0x3ff0000f */
752         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* 0xff00ff00 default: 0x0000ff00 GPMI BCH */
753         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */
754         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */
755         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
756         MXC_DCD_ITEM(0x020c80a0, 0x00082029) /* set video PLL to 498MHz */
757         MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
758         MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
759
760         /* IOMUX: */
761         MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
762         /* UART1 pad config */
763         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
764         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
765 #ifdef CONFIG_SOC_MX6Q
766         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
767 #else
768         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */
769 #endif
770         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
771         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
772         MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
773
774 #ifdef CONFIG_NAND_MXS
775         /* NAND */
776         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,    0x00000000)     /* NANDF_CLE: NANDF_CLE */
777         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,    0x00000000)     /* NANDF_ALE: NANDF_ALE */
778         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B,   0x00000000)     /* NANDF_WP_B: NANDF_WPn */
779         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY,  0x00000000)     /* NANDF_RB0: NANDF_READY0 */
780         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B,  0x00000000)     /* NANDF_CS0: NANDF_CS0 */
781         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD,     0x00000001)     /* SD4_CMD: NANDF_RDn */
782         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK,     0x00000001)     /* SD4_CLK: NANDF_WRn */
783         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000)     /* NANDF_D0: NANDF_D0 */
784         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000)     /* NANDF_D1: NANDF_D1 */
785         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000)     /* NANDF_D2: NANDF_D2 */
786         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000)     /* NANDF_D3: NANDF_D3 */
787         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000)     /* NANDF_D4: NANDF_D4 */
788         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000)     /* NANDF_D5: NANDF_D5 */
789         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000)     /* NANDF_D6: NANDF_D6 */
790         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000)     /* NANDF_D7: NANDF_D7 */
791 #endif
792         /* ext. mem CS */
793         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
794         /* DRAM_DQM[0..7] */
795         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
796         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
797         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
798         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
799         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
800         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
801         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
802         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
803
804         /* DRAM_A[0..15] */
805         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
806         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
807         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
808         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
809         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
810         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
811         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
812         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
813         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
814         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
815         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
816         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
817         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
818         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
819         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
820         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
821         /* DRAM_CAS */
822         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
823         /* DRAM_RAS */
824         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
825         /* DRAM_SDCLK[0..1] */
826         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
827         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
828         /* DRAM_RESET */
829         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
830         /* DRAM_SDCKE[0..1] */
831         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
832         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
833         /* DRAM_SDBA[0..2] */
834         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
835         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
836         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
837         /* DRAM_SDODT[0..1] */
838         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
839         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
840         /* DRAM_B[0..7]DS */
841         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
842         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
843         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE1_MASK)
844         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE1_MASK)
845         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE1_MASK)
846         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE1_MASK)
847         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE1_MASK)
848         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE1_MASK)
849         /* ADDDS */
850         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
851         /* DDRMODE_CTL */
852         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
853         /* DDRPKE */
854         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
855         /* DDRMODE */
856         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
857         /* CTLDS */
858         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
859         /* DDR_TYPE */
860         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
861         /* DDRPK */
862         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
863         /* DDRHYS */
864         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
865
866 #ifdef CONFIG_SOC_MX6Q
867         /* TERM_CTL[0..7] */
868         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
869         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
870         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
871         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
872         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
873         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
874         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
875         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
876 #endif
877 #if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
878 #define DO_DDR_CALIB
879 #endif
880         /* SDRAM initialization */
881 #define WL_DLY_DQS_VAL  30
882 #define WL_DLY_DQS0     (WL_DLY_DQS_VAL + 0)
883 #define WL_DLY_DQS1     (WL_DLY_DQS_VAL + 0)
884 #define WL_DLY_DQS2     (WL_DLY_DQS_VAL + 0)
885 #define WL_DLY_DQS3     (WL_DLY_DQS_VAL + 0)
886 #define WL_DLY_DQS4     (WL_DLY_DQS_VAL + 0)
887 #define WL_DLY_DQS5     (WL_DLY_DQS_VAL + 0)
888 #define WL_DLY_DQS6     (WL_DLY_DQS_VAL + 0)
889 #define WL_DLY_DQS7     (WL_DLY_DQS_VAL + 0)
890
891         /* ZQ calibration */
892         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
893         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
894         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
895
896         MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
897         MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
898         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
899         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
900 #if defined(CONFIG_SOC_MX6Q)
901         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43430349)
902         MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x03330334)
903         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x434b0351)
904         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x033d030e)
905 #elif defined(CONFIG_SOC_MX6DL)
906         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x423a0236)
907         MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x02210227)
908         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42240226)
909         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02120223)
910 #elif defined(CONFIG_SOC_MX6S)
911         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42490244)
912         MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x022f0238)
913 #else
914 #error No DGCTRL settings for selected SoC
915 #endif
916         MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
917         MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
918         MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
919         MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
920
921         /* MPRDDQBY[0..7]DL */
922         MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
923         MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
924         MXC_DCD_ITEM_32(MMDC1_MPRDDQBY2DL, 0x33333333)
925         MXC_DCD_ITEM_32(MMDC1_MPRDDQBY3DL, 0x33333333)
926         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
927         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
928         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
929         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
930 #define MPMUR_FRC_MSR   (1 << 11)
931         MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
932         MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
933         /* MDMISC */
934         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
935         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
936         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
937
938         /* MSDSCR Conf Req */
939         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
940         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
941         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
942
943         /* MDCTL */
944         MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
945 #if BANK_ADDR_BITS > 1
946         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (3 << 30))
947 #else
948         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (1 << 30))
949 #endif
950         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
951
952         MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
953         MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
954         MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
955         MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2)
956         MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
957         MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
958         MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
959         MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
960
961         /* CS0 MRS: */
962         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
963         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
964         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
965         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
966 #if BANK_ADDR_BITS > 1
967         /* CS1 MRS: */
968         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
969         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
970         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
971         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
972 #endif
973         MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
974         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
975
976         MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222)
977         MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
978
979         /* DDR3 calibration */
980         MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
981         MXC_DCD_ITEM(MMDC1_MAPSR, 1)
982
983 #ifdef DO_DDR_CALIB
984         /* ZQ calibration */
985         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
986         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
987         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
988
989         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
990         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
991         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
992 #endif
993         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
994 #if BANK_ADDR_BITS > 1
995         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
996 #endif
997         /* DRAM_SDQS[0..7] pad config */
998         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
999         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
1000         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
1001         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
1002         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
1003         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
1004         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
1005         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
1006 #ifdef DO_DDR_CALIB
1007         /* Read delay calibration */
1008         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
1009         MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
1010         MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
1011         MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000013)
1012         MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
1013         MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
1014         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1015
1016         /* Write delay calibration */
1017         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
1018         MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
1019         MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
1020         MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
1021 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
1022         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1023
1024         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
1025         MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
1026         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
1027 #endif
1028         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1029 #endif /* DO_DDR_CALIB */
1030         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
1031 #if BANK_ADDR_BITS > 1
1032         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
1033 #endif
1034         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
1035         MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
1036         MXC_DCD_ITEM(MMDC1_MAPSR, (16 << 8))
1037         MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
1038
1039         /* MDSCR: Normal operation */
1040         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
1041         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
1042         MXC_DCD_END