karo: tx6: remove bogus definition of MMDC1_MPWRDLST
[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S
1 #include <config.h>
2 #include <configs/tx6.h>
3 #include <asm/arch/imx-regs.h>
4 #include <generated/asm-offsets.h>
5
6 #ifndef CCM_CCR
7 #error asm-offsets not included
8 #endif
9
10 #define DEBUG_LED_BIT           20
11 #define LED_GPIO_BASE           GPIO2_BASE_ADDR
12 #define LED_MUX_OFFSET          0x0ec
13 #define LED_MUX_MODE            0x15
14
15 #define SDRAM_CLK               CONFIG_SYS_SDRAM_CLK
16
17 #ifdef PHYS_SDRAM_2_SIZE
18 #define SDRAM_SIZE              (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
19 #else
20 #define SDRAM_SIZE              PHYS_SDRAM_1_SIZE
21 #endif
22
23 #define CPU_2_BE_32(l)                  \
24         ((((l) << 24) & 0xFF000000) |   \
25         (((l) << 8) & 0x00FF0000) |     \
26         (((l) >> 8) & 0x0000FF00) |     \
27         (((l) >> 24) & 0x000000FF))
28
29 #define CHECK_DCD_ADDR(a)       (                       \
30         ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
31         ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||   \
32         ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
33         ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||  \
34         ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
35         ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
36         ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
37
38         .macro  mxc_dcd_item    addr, val
39         .ifne   CHECK_DCD_ADDR(\addr)
40         .word   CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
41         .else
42         .error  "Address \addr not accessible from DCD"
43         .endif
44         .endm
45
46 #define MXC_DCD_ITEM(addr, val)         mxc_dcd_item    (addr), (val)
47 #if PHYS_SDRAM_1_WIDTH == 64
48 #define MXC_DCD_ITEM_64(addr, val)              mxc_dcd_item    (addr), (val)
49 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
50 #else
51 #define MXC_DCD_ITEM_64(addr, val)
52 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask)
53 #endif
54
55 #define MXC_DCD_CMD_SZ_BYTE             1
56 #define MXC_DCD_CMD_SZ_SHORT            2
57 #define MXC_DCD_CMD_SZ_WORD             4
58 #define MXC_DCD_CMD_FLAG_WRITE          0x0
59 #define MXC_DCD_CMD_FLAG_CLR            0x1
60 #define MXC_DCD_CMD_FLAG_SET            0x3
61 #define MXC_DCD_CMD_FLAG_CHK_CLR        ((0 << 0) | (0 << 1))
62 #define MXC_DCD_CMD_FLAG_CHK_SET        ((0 << 0) | (1 << 1))
63 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR    ((1 << 0) | (0 << 1))
64 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET    ((1 << 0) | (1 << 1))
65
66 #define MXC_DCD_START                                                   \
67         .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
68 dcd_start:
69
70         .macro  MXC_DCD_END
71 1:
72         .ifgt   . - dcd_start - 1768
73         .error  "DCD too large!"
74         .endif
75 dcd_end:
76         .endm
77
78 #define MXC_DCD_CMD_WRT(type, flags)                                    \
79 1:      .word   CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
80
81 #define MXC_DCD_CMD_CHK(type, flags, addr, mask)                        \
82 1:      .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
83                 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
84
85 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)             \
86 1:      .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
87                 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
88
89 #define MXC_DCD_CMD_NOP()                               \
90 1:      .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
91
92
93 #define CK_TO_NS(ck)    (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
94 #define NS_TO_CK(ns)    (((ns) * SDRAM_CLK + 999) / 1000)
95 #define NS_TO_CK10(ns)  DIV_ROUND_UP(NS_TO_CK(ns), 10)
96
97         .macro          CK_VAL, name, clks, offs, max
98         .iflt           \clks - \offs
99         .set            \name, 0
100         .else
101         .ifle           \clks - \offs - \max
102         .set            \name, \clks - \offs
103         .else
104         .error          "Value \clks out of range for parameter \name"
105         .endif
106         .endif
107         .endm
108
109         .macro          NS_VAL, name, ns, offs, max
110         .iflt           \ns - \offs
111         .set            \name, 0
112         .else
113         CK_VAL          \name, NS_TO_CK(\ns), \offs, \max
114         .endif
115         .endm
116
117         .macro          CK_MAX, name, ck1, ck2, offs, max
118         .ifgt           \ck1 - \ck2
119         CK_VAL          \name, \ck1, \offs, \max
120         .else
121         CK_VAL          \name, \ck2, \offs, \max
122         .endif
123         .endm
124
125 #define MDMISC_DDR_TYPE_DDR3            0
126 #define MDMISC_DDR_TYPE_LPDDR2          1
127 #define MDMISC_DDR_TYPE_DDR2            2
128
129 #define DIV_ROUND_UP(m,d)               (((m) + (d) - 1) / (d))
130
131 #define MDOR_CLK_PERIOD_ns              15258   /* base clock for MDOR values */
132
133 /* DDR3 SDRAM */
134 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
135 #define BANK_ADDR_BITS                  2
136 #else
137 #define BANK_ADDR_BITS                  1
138 #endif
139 #define SDRAM_BURST_LENGTH              8
140 #define RALAT                           5
141 #define WALAT                           0
142 #define BI_ON                           0
143 #define ADDR_MIRROR                     0
144 #define DDR_TYPE                        MDMISC_DDR_TYPE_DDR3
145
146 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
147 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
148 #define CL_VAL  11
149 #define CWL_VAL 8
150 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
151 #define CL_VAL  9 // or 10
152 #define CWL_VAL 7
153 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
154 #define CL_VAL  7 // or 8
155 #define CWL_VAL 6
156 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
157 #define CL_VAL  6
158 #define CWL_VAL 5
159 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
160 #define CL_VAL  5
161 #define CWL_VAL 5
162 #else
163 #error SDRAM clock out of range: 303 .. 800
164 #endif
165
166 /* MDCFG0 0x0c */
167 NS_VAL  tRFC,   160, 1, 255             /* clks - 1 (0..255) */
168 CK_MAX  tXS,    NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
169 CK_MAX  tXP,    NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
170 CK_MAX  tXPDLL, NS_TO_CK(24), 2, 1, 15  /* clks - 1 (0..15) */
171 NS_VAL  tFAW,   50, 1, 31               /* clks - 1 (0..31) */
172 CK_VAL  tCL,    CL_VAL, 3, 8            /* clks - 3 (0..8) CAS Latency */
173
174 /* MDCFG1 0x10 */
175 CK_VAL  tRCD,   NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */
176 CK_VAL  tRP,    NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */
177 NS_VAL  tRC,    50, 1, 31               /* clks - 1 (0..31) */
178 CK_VAL  tRAS,   NS_TO_CK10(375), 1, 31  /* clks - 1 (0..31) */ /* 37.5 */
179 CK_VAL  tRPA,   1, 0, 1                 /* clks     (0..1) */
180 NS_VAL  tWR,    15, 1, 15               /* clks - 1 (0..15) */
181 CK_VAL  tMRD,   4, 1, 15                /* clks - 1 (0..15) */
182 CK_VAL  tCWL,   CWL_VAL, 2, 6           /* clks - 2 (0..6) */
183
184 /* MDCFG2 0x14 */
185 CK_VAL  tDLLK,  512, 1, 511             /* clks - 1 (0..511) */
186 CK_MAX  tRTP,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
187 CK_MAX  tWTR,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
188 CK_MAX  tRRD,   NS_TO_CK(10), 4, 1, 7   /* clks - 1 (0..7) */
189
190 /* MDOR 0x30 */
191 CK_MAX  tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
192 #define tSDE_RST        (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
193 #define tRST_CKE        (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
194
195 /* MDOTC 0x08 */
196 CK_VAL  tAOFPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
197 CK_VAL  tAONPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
198 CK_VAL  tANPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
199 CK_VAL  tAXPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
200 CK_VAL  tODTLon tCWL, 0, 7              /* clks - 1 (0..7) */ /* CWL+AL-2 */
201 CK_VAL  tODTLoff tCWL, 0, 31            /* clks - 1 (0..31) */ /* CWL+AL-2 */
202
203 /* MDPDC 0x04 */
204 CK_MAX  tCKE,   NS_TO_CK(5), 3, 1, 7
205 CK_MAX  tCKSRX, NS_TO_CK(10), 5, 0, 7
206 CK_MAX  tCKSRE, NS_TO_CK(10), 5, 0, 7
207
208 #define PRCT            0
209 #define PWDT            5
210 #define SLOW_PD         0
211 #define BOTH_CS_PD      1
212
213 #define MDPDC_VAL_0     (       \
214         (PRCT << 28) |          \
215         (PRCT << 24) |          \
216         (tCKE << 16) |          \
217         (SLOW_PD << 7) |        \
218         (BOTH_CS_PD << 6) |     \
219         (tCKSRX << 3) |         \
220         (tCKSRE << 0)           \
221         )
222
223 #define MDPDC_VAL_1     (MDPDC_VAL_0 |          \
224         (PWDT << 12) |                          \
225         (PWDT << 8)                             \
226         )
227
228 #define ROW_ADDR_BITS                   14
229 #define COL_ADDR_BITS                   10
230
231 #define Rtt_Nom                         1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
232 #define Rtt_WR                          0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
233 #define DLL_DISABLE                     0
234
235         .iflt   tWR - 7
236         .set    mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ |    \
237                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
238                         ((tWR + 1 - 4) << 9) |                          \
239                         ((((tCL + 3) - 4) & 0x7) << 4) |                \
240                         ((((tCL + 3) - 4) & 0x8) >> 1))
241         .else
242         .set    mr0_val, ((1 << 8) /* DLL Reset */ |                    \
243                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
244                         (((tWR + 1) / 2) << 9) |        \
245                         ((((tCL + 3) - 4) & 0x7) << 4) | \
246                         ((((tCL + 3) - 4) & 0x8) >> 1))
247         .endif
248
249 #define mr1_val                         (                                       \
250                                          ((Rtt_Nom & 1) << 2) |                 \
251                                          (((Rtt_Nom >> 1) & 1) << 6) |          \
252                                          (((Rtt_Nom >> 2) & 1) << 9) |          \
253                                          (DLL_DISABLE << 0) |                   \
254                                         0)
255 #define mr2_val                         (                                       \
256                                          (Rtt_WR << 9) /* dynamic ODT */ |      \
257                                          (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
258                                          (1 << 6) | /* ASR: Automatic Self Refresh */ \
259                                          (((tCWL + 2) - 5) << 3) |              \
260                                         0)
261 #define mr3_val                         0
262
263 #define MDSCR_MRS_VAL(cs, mr, val)      (((val) << 16) |                \
264                                         (1 << 15) /* CON_REQ */ |       \
265                                         (3 << 4) /* MRS command */ |    \
266                                         ((cs) << 3) |                   \
267                                         ((mr) << 0) |                   \
268                                         0)
269
270 #define MDCFG0_VAL      (       \
271         (tRFC << 24) |          \
272         (tXS << 16) |           \
273         (tXP << 13) |           \
274         (tXPDLL << 9) |         \
275         (tFAW << 4) |           \
276         (tCL << 0))             \
277
278 #define MDCFG1_VAL      (       \
279         (tRCD << 29) |          \
280         (tRP << 26) |           \
281         (tRC << 21) |           \
282         (tRAS << 16) |          \
283         (tRPA << 15) |          \
284         (tWR << 9) |            \
285         (tMRD << 5) |           \
286         (tCWL << 0))            \
287
288 #define MDCFG2_VAL      (       \
289         (tDLLK << 16) |         \
290         (tRTP << 6) |           \
291         (tWTR << 3) |           \
292         (tRRD << 0))
293
294 #define BURST_LEN               (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
295
296 #define MDCTL_VAL               (((ROW_ADDR_BITS - 11) << 24) |         \
297                                 ((COL_ADDR_BITS - 9) << 20) |           \
298                                 (BURST_LEN << 19) |                     \
299                                 ((PHYS_SDRAM_1_WIDTH / 32) << 16) |     \
300                                 ((-1) << (32 - BANK_ADDR_BITS)))
301
302 #define MDMISC_VAL              ((ADDR_MIRROR << 19) |  \
303                                 (WALAT << 16) |         \
304                                 (BI_ON << 12) |         \
305                                 (0x3 << 9) |            \
306                                 (RALAT << 6) |          \
307                                 (DDR_TYPE << 3))
308
309 #define MDOR_VAL                ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
310
311 #define MDOTC_VAL               ((tAOFPD << 27) |       \
312                                 (tAONPD << 24) |        \
313                                 (tANPD << 20) |         \
314                                 (tAXPD << 16) |         \
315                                 (tODTLon << 12) |       \
316                                 (tODTLoff << 4))
317
318 ivt_header:
319         .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
320 app_start_addr:
321         .long   _start
322         .long   0x0
323 dcd_ptr:
324         .long   dcd_hdr
325 boot_data_ptr:
326         .word   boot_data
327 self_ptr:
328         .word   ivt_header
329 app_code_csf:
330         .word   0x0
331         .word   0x0
332 boot_data:
333         .long   _start
334 image_len:
335         .long   CONFIG_U_BOOT_IMG_SIZE
336 plugin:
337         .word   0
338 ivt_end:
339 #define DCD_VERSION     0x40
340
341 #define CLKCTL_CCGR0    0x68
342 #define CLKCTL_CCGR1    0x6c
343 #define CLKCTL_CCGR2    0x70
344 #define CLKCTL_CCGR3    0x74
345 #define CLKCTL_CCGR4    0x78
346 #define CLKCTL_CCGR5    0x7c
347 #define CLKCTL_CCGR6    0x80
348 #define CLKCTL_CCGR7    0x84
349 #define CLKCTL_CMEOR    0x88
350
351 #define DDR_SEL_VAL     3
352 #define DSE_VAL         6
353 #define ODT_VAL         2
354
355 #define DDR_SEL_SHIFT   18
356 #define DDR_MODE_SHIFT  17
357 #define ODT_SHIFT       8
358 #define DSE_SHIFT       3
359 #define HYS_SHIFT       16
360 #define PKE_SHIFT       12
361 #define PUE_SHIFT       13
362 #define PUS_SHIFT       14
363
364 #define DDR_SEL_MASK    (DDR_SEL_VAL << DDR_SEL_SHIFT)
365 #define DDR_MODE_MASK   (1 << DDR_MODE_SHIFT)
366 #define DSE_MASK        (DSE_VAL << DSE_SHIFT)
367 #define ODT_MASK        (ODT_VAL << ODT_SHIFT)
368
369 #define DQM_MASK        (DDR_MODE_MASK | DSE_MASK)
370 #define SDQS_MASK       DSE_MASK
371 #define SDODT_MASK      (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
372 #define SDCLK_MASK      (DDR_MODE_MASK | DSE_MASK)
373 #define SDCKE_MASK      ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
374 #define DDR_ADDR_MASK   0
375 #define DDR_CTRL_MASK   (DDR_MODE_MASK | DSE_MASK)
376
377 #define MMDC1_MDCTL                             0x021b0000
378 #define MMDC1_MDPDC                             0x021b0004
379 #define MMDC1_MDOTC                             0x021b0008
380 #define MMDC1_MDCFG0                            0x021b000c
381 #define MMDC1_MDCFG1                            0x021b0010
382 #define MMDC1_MDCFG2                            0x021b0014
383 #define MMDC1_MDMISC                            0x021b0018
384 #define MMDC1_MDSCR                             0x021b001c
385 #define MMDC1_MDREF                             0x021b0020
386 #define MMDC1_MDRWD                             0x021b002c
387 #define MMDC1_MDOR                              0x021b0030
388 #define MMDC1_MDASP                             0x021b0040
389 #define MMDC1_MAPSR                             0x021b0404
390 #define MMDC1_MPZQHWCTRL                        0x021b0800
391 #define MMDC1_MPWLGCR                           0x021b0808
392 #define MMDC1_MPWLDECTRL0                       0x021b080c
393 #define MMDC1_MPWLDECTRL1                       0x021b0810
394 #define MMDC1_MPWLDLST                          0x021b0814
395 #define MMDC1_MPODTCTRL                         0x021b0818
396 #define MMDC1_MPRDDQBY0DL                       0x021b081c
397 #define MMDC1_MPRDDQBY1DL                       0x021b0820
398 #define MMDC1_MPRDDQBY2DL                       0x021b0824
399 #define MMDC1_MPRDDQBY3DL                       0x021b0828
400 #define MMDC1_MPDGCTRL0                         0x021b083c
401 #define MMDC1_MPDGCTRL1                         0x021b0840
402 #define MMDC1_MPDGDLST0                         0x021b0844
403 #define MMDC1_MPRDDLCTL                         0x021b0848
404 #define MMDC1_MPRDDLST                          0x021b084c
405 #define MMDC1_MPWRDLCTL                         0x021b0850
406 #define MMDC1_MPWRDLST                          0x021b0854
407 #define MMDC1_MPRDDLHWCTL                       0x021b0860
408 #define MMDC1_MPWRDLHWCTL                       0x021b0864
409 #define MMDC1_MPPDCMPR2                         0x021b0890
410 #define MMDC1_MPSWDRDR0                         0x021b0898
411 #define MMDC1_MPSWDRDR1                         0x021b089c
412 #define MMDC1_MPSWDRDR2                         0x021b08a0
413 #define MMDC1_MPSWDRDR3                         0x021b08a4
414 #define MMDC1_MPSWDRDR4                         0x021b08a8
415 #define MMDC1_MPSWDRDR5                         0x021b08ac
416 #define MMDC1_MPSWDRDR6                         0x021b08b0
417 #define MMDC1_MPSWDRDR7                         0x021b08b4
418 #define MMDC1_MPMUR0                            0x021b08b8
419
420 #if PHYS_SDRAM_1_WIDTH == 64
421 #define MMDC2_MDPDC                             0x021b4004
422 #define MMDC2_MPWLGCR                           0x021b4808
423 #define MMDC2_MPWLDECTRL0                       0x021b480c
424 #define MMDC2_MPWLDECTRL1                       0x021b4810
425 #define MMDC2_MPWLDLST                          0x021b4814
426 #define MMDC2_MPODTCTRL                         0x021b4818
427 #define MMDC2_MPRDDQBY0DL                       0x021b481c
428 #define MMDC2_MPRDDQBY1DL                       0x021b4820
429 #define MMDC2_MPRDDQBY2DL                       0x021b4824
430 #define MMDC2_MPRDDQBY3DL                       0x021b4828
431 #define MMDC2_MPDGCTRL0                         0x021b483c
432 #define MMDC2_MPDGCTRL1                         0x021b4840
433 #define MMDC2_MPDGDLST0                         0x021b4844
434 #define MMDC2_MPRDDLCTL                         0x021b4848
435 #define MMDC2_MPRDDLST                          0x021b484c
436 #define MMDC2_MPWRDLCTL                         0x021b4850
437 #define MMDC2_MPWRDLST                          0x021b4854
438 #define MMDC2_MPRDDLHWCTL                       0x021b4860
439 #define MMDC2_MPWRDLHWCTL                       0x021b4864
440 #define MMDC2_MPRDDLHWST0                       0x021b4868
441 #define MMDC2_MPRDDLHWST1                       0x021b486c
442 #define MMDC2_MPWRDLHWST0                       0x021b4870
443 #define MMDC2_MPWRDLHWST1                       0x021b4874
444 #define MMDC2_MPWLHWERR                         0x021b4878
445 #define MMDC2_MPDGHWST0                         0x021b487c
446 #define MMDC2_MPDGHWST1                         0x021b4880
447 #define MMDC2_MPDGHWST2                         0x021b4884
448 #define MMDC2_MPDGHWST3                         0x021b4888
449 #define MMDC2_MPSWDAR0                          0x021b4894
450 #define MMDC2_MPSWDRDR0                         0x021b4898
451 #define MMDC2_MPSWDRDR1                         0x021b489c
452 #define MMDC2_MPSWDRDR2                         0x021b48a0
453 #define MMDC2_MPSWDRDR3                         0x021b48a4
454 #define MMDC2_MPSWDRDR4                         0x021b48a8
455 #define MMDC2_MPSWDRDR5                         0x021b48ac
456 #define MMDC2_MPSWDRDR6                         0x021b48b0
457 #define MMDC2_MPSWDRDR7                         0x021b48b4
458 #endif
459
460 #ifdef CONFIG_MX6Q
461 #define IOMUXC_GPR1                             0x020e0004
462 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e024c
463 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e02a8
464 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e02ac
465 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e02c0
466 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e02c4
467 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e02d4
468 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e02d8
469 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02dc
470 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02e0
471 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e02e4
472 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e02ec
473 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e02f4
474 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e02f8
475 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e02fc
476 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0300
477 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e0304
478 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0308
479 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e030c
480 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0310
481 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e0314
482 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e0318
483 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e050c
484 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0510
485 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0514
486 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e0518
487 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e051c
488 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e0520
489 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e0524
490 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0528
491 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e052c
492 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0530
493 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0534
494 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0538
495 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e053c
496 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0540
497 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0544
498 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0548
499 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e054c
500 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0550
501 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e0554
502 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0558
503 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e055c
504 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0560
505 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e0564
506 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0568
507 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e056c
508 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0578
509 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e057c
510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0580
511 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e0584
512 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e0588
513 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e058c
514 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e0590
515 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e0594
516 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e0598
517 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e059c
518 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e05a0
519 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e05a8
520 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e05ac
521 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e05b0
522 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e05b4
523 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e05b8
524 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e05bc
525 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e05c0
526 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e05c4
527 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
528 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
529 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
530 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0         0x020e0754
531 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0758
532 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1         0x020e075c
533 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2         0x020e0760
534 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3         0x020e0764
535 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0768
536 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4         0x020e076c
537 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e0770
538 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0774
539 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5         0x020e0778
540 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6         0x020e077c
541 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7         0x020e0780
542 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
543 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
544 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
545 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
546 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
547 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
548 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
549 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
550 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
551 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
552 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
553 #endif
554
555 #ifdef CONFIG_MX6DL
556 #define IOMUXC_GPR1                             0x020e0004
557 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e0218
558 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e0330
559 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e032c
560 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e0314
561 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e0318
562 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e0270
563 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e026c
564 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02a8
565 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02a4
566 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e0274
567 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e027c
568 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e033c
569 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e0338
570 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e0284
571 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0288
572 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e028c
573 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0290
574 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e0294
575 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0298
576 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e029c
577 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e02a0
578 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e04d0
579 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0484
580 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0480
581 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e04cc
582 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e04c8
583 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e047c
584 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e04c4
585 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0478
586 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e0424
587 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0428
588 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0444
589 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0448
590 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e044c
591 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0450
592 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0454
593 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0458
594 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e045c
595 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0460
596 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e042c
597 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0430
598 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e0434
599 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0438
600 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e043c
601 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0440
602 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e0464
603 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0490
604 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e0494
605 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0498
606 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e049c
607 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e04ac
608 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e04a0
609 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e04a4
610 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e04b0
611 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e04a8
612 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e04b4
613 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e04b8
614 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e04bc
615 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e0470
616 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e04c0
617 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e0474
618 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e04d4
619 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e0488
620 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e04d8
621 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e048c
622 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
623 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
624 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
625 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0754
626 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0754
627 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e075c
628 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0760
629 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
630 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
631 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
632 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
633 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
634 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
635 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
636 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
637 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
638 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e08f8
639 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e08fc
640 #endif
641
642 dcd_hdr:
643         MXC_DCD_START
644         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
645         /* RESET_OUT GPIO_7_12 */
646         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
647
648         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */
649
650         MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
651
652         /* enable all relevant clocks... */
653         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
654         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
655         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
656         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
657         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
658         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
659         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
660
661         /* IOMUX: */
662         MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
663         /* UART1 pad config */
664         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
665         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
666 #ifdef CONFIG_MX6Q
667         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
668 #else
669         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */
670 #endif
671         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
672         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
673         MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
674
675 #ifdef CONFIG_NAND_MXS
676         /* NAND */
677         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,    0x00000000)     /* NANDF_CLE: NANDF_CLE */
678         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,    0x00000000)     /* NANDF_ALE: NANDF_ALE */
679         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B,   0x00000000)     /* NANDF_WP_B: NANDF_WPn */
680         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY,  0x00000000)     /* NANDF_RB0: NANDF_READY0 */
681         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B,  0x00000000)     /* NANDF_CS0: NANDF_CS0 */
682         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD,     0x00000001)     /* SD4_CMD: NANDF_RDn */
683         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK,     0x00000001)     /* SD4_CLK: NANDF_WRn */
684         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000)     /* NANDF_D0: NANDF_D0 */
685         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000)     /* NANDF_D1: NANDF_D1 */
686         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000)     /* NANDF_D2: NANDF_D2 */
687         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000)     /* NANDF_D3: NANDF_D3 */
688         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000)     /* NANDF_D4: NANDF_D4 */
689         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000)     /* NANDF_D5: NANDF_D5 */
690         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000)     /* NANDF_D6: NANDF_D6 */
691         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000)     /* NANDF_D7: NANDF_D7 */
692 #endif
693         /* ext. mem CS */
694         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
695         /* DRAM_DQM[0..7] */
696         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
697         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
698         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
699         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
700         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
701         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
702         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
703         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
704
705         /* DRAM_A[0..15] */
706         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
707         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
708         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
709         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
710         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
711         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
712         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
713         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
714         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
715         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
716         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
717         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
718         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
719         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
720         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
721         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
722         /* DRAM_CAS */
723         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
724         /* DRAM_RAS */
725         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
726         /* DRAM_SDCLK[0..1] */
727         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
728         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
729         /* DRAM_RESET */
730         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
731         /* DRAM_SDCKE[0..1] */
732         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
733         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
734         /* DRAM_SDBA[0..2] */
735         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
736         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
737         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
738         /* DRAM_SDODT[0..1] */
739         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
740         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
741         /* DRAM_B[0..7]DS */
742         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
743         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
744         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
745         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
746         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
747         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
748         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
749         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
750         /* ADDDS */
751         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
752         /* DDRMODE_CTL */
753         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
754         /* DDRPKE */
755         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
756         /* DDRMODE */
757         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
758         /* CTLDS */
759         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK)
760         /* DDR_TYPE */
761         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
762         /* DDRPK */
763         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
764         /* DDRHYS */
765         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
766
767 #ifdef CONFIG_MX6Q
768         /* TERM_CTL[0..7] */
769         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
770         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
771         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
772         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
773         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
774         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
775         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
776         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
777 #endif
778         /* SDRAM initialization */
779         /* MPRDDQBY[0..7]DL */
780         MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
781         MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
782         MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
783         MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
784         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
785         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
786         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
787         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
788         /* MDMISC */
789         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
790         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
791         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
792
793         /* MSDSCR Conf Req */
794         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
795         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
796         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
797
798         /* MDCTL */
799         MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
800         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
801         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
802
803         MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
804         MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
805         MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
806         MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2)
807         MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
808         MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
809         MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
810         MXC_DCD_ITEM_64(MMDC2_MDPDC,  MDPDC_VAL_0)
811         MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
812
813         /* CS0 MRS: */
814         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
815         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
816         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
817         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
818 #if BANK_ADDR_BITS > 1
819         /* CS1 MRS: */
820         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
821         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
822         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
823         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
824 #endif
825
826         MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
827         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
828
829         MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222)
830         MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
831
832         /* DDR3 calibration */
833         MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
834         MXC_DCD_ITEM(MMDC1_MAPSR,     0x00001007)
835
836         /* ZQ calibration */
837         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
838         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
839         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
840
841         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
842         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
843
844         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
845
846 #define WL_DLY_DQS_VAL  30
847 #define WL_DLY_DQS0     (WL_DLY_DQS_VAL + 0)
848 #define WL_DLY_DQS1     (WL_DLY_DQS_VAL + 0)
849 #define WL_DLY_DQS2     (WL_DLY_DQS_VAL + 0)
850 #define WL_DLY_DQS3     (WL_DLY_DQS_VAL + 0)
851 #define WL_DLY_DQS4     (WL_DLY_DQS_VAL + 0)
852 #define WL_DLY_DQS5     (WL_DLY_DQS_VAL + 0)
853 #define WL_DLY_DQS6     (WL_DLY_DQS_VAL + 0)
854 #define WL_DLY_DQS7     (WL_DLY_DQS_VAL + 0)
855         /* Write leveling */
856         MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
857         MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
858         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
859         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
860
861         /* DQS gating calibration */
862         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
863 #if BANK_ADDR_BITS > 1
864         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
865 #endif
866         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
867         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
868         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
869         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
870         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
871         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
872         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
873         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
874
875         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
876         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
877
878         MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
879         MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
880         MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
881         MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
882         MXC_DCD_ITEM(MMDC1_MPMUR0,    0x00000800)
883         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
884         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
885         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
886         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
887         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
888         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
889         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
890         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000)
891         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
892
893         /* DRAM_SDQS[0..7] pad config */
894         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
895         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
896         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
897         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
898         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
899         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
900         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
901         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
902
903         /* Read delay calibration */
904         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
905         MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
906         MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
907         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
908         MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
909         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
910
911         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
912         MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
913         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
914 #if PHYS_SDRAM_1_WIDTH == 64
915         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
916
917         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
918         MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
919         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
920 #endif
921         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
922
923         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
924 #if BANK_ADDR_BITS > 1
925         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
926 #endif
927         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
928         MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
929         MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006)
930         MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
931         MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
932
933         /* MDSCR: Normal operation */
934         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
935         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
936         MXC_DCD_END