upgrade to upstream version 2013.07
[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S
1 #include <config.h>
2 #include <configs/tx6.h>
3 #include <asm/arch/imx-regs.h>
4 #include <generated/asm-offsets.h>
5
6 #ifndef CCM_CCR
7 #error asm-offsets not included
8 #endif
9
10 #define DEBUG_LED_BIT           20
11 #define LED_GPIO_BASE           GPIO2_BASE_ADDR
12 #define LED_MUX_OFFSET          0x0ec
13 #define LED_MUX_MODE            0x15
14
15 #define SDRAM_CLK               CONFIG_SYS_SDRAM_CLK
16
17 #ifdef PHYS_SDRAM_2_SIZE
18 #define SDRAM_SIZE              (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
19 #else
20 #define SDRAM_SIZE              PHYS_SDRAM_1_SIZE
21 #endif
22
23 #define CPU_2_BE_32(l)                  \
24         ((((l) << 24) & 0xFF000000) |   \
25         (((l) << 8) & 0x00FF0000) |     \
26         (((l) >> 8) & 0x0000FF00) |     \
27         (((l) >> 24) & 0x000000FF))
28
29 #define CHECK_DCD_ADDR(a)       (                       \
30         ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
31         ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||   \
32         ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
33         ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||  \
34         ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
35         ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
36         ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
37
38         .macro  mxc_dcd_item    addr, val
39         .ifne   CHECK_DCD_ADDR(\addr)
40         .word   CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
41         .else
42         .error  "Address \addr not accessible from DCD"
43         .endif
44         .endm
45
46 #define MXC_DCD_ITEM(addr, val)         mxc_dcd_item    addr, val
47 #if PHYS_SDRAM_1_WIDTH == 64
48 #define MXC_DCD_ITEM_64(addr, val)              mxc_dcd_item    addr, val
49 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
50 #else
51 #define MXC_DCD_ITEM_64(addr, val)
52 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask)
53 #endif
54
55 #define MXC_DCD_CMD_SZ_BYTE             1
56 #define MXC_DCD_CMD_SZ_SHORT            2
57 #define MXC_DCD_CMD_SZ_WORD             4
58 #define MXC_DCD_CMD_FLAG_WRITE          0x0
59 #define MXC_DCD_CMD_FLAG_CLR            0x1
60 #define MXC_DCD_CMD_FLAG_SET            0x3
61 #define MXC_DCD_CMD_FLAG_CHK_ANY        (1 << 0)
62 #define MXC_DCD_CMD_FLAG_CHK_SET        (1 << 1)
63 #define MXC_DCD_CMD_FLAG_CHK_CLR        (0 << 1)
64
65 #define MXC_DCD_CMD_WRT(type, flags, next)                                      \
66         .word   CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
67
68 #define MXC_DCD_CMD_CHK(type, flags, addr, mask)                                \
69         .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
70                 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
71
72 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)                     \
73         .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
74                 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
75
76 #define MXC_DCD_CMD_NOP()                                                       \
77         .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
78
79 #define CK_TO_NS(ck)    (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
80 #define NS_TO_CK(ns)    (((ns) * SDRAM_CLK + 999) / 1000)
81 #define NS_TO_CK10(ns)  DIV_ROUND_UP(NS_TO_CK(ns), 10)
82
83         .macro          CK_VAL, name, clks, offs, max
84         .iflt           \clks - \offs
85         .set            \name, 0
86         .else
87         .ifle           \clks - \offs - \max
88         .set            \name, \clks - \offs
89         .else
90         .error          "Value \clks out of range for parameter \name"
91         .endif
92         .endif
93         .endm
94
95         .macro          NS_VAL, name, ns, offs, max
96         .iflt           \ns - \offs
97         .set            \name, 0
98         .else
99         CK_VAL          \name, NS_TO_CK(\ns), \offs, \max
100         .endif
101         .endm
102
103         .macro          CK_MAX, name, ck1, ck2, offs, max
104         .ifgt           \ck1 - \ck2
105         CK_VAL          \name, \ck1, \offs, \max
106         .else
107         CK_VAL          \name, \ck2, \offs, \max
108         .endif
109         .endm
110
111 #define MDMISC_DDR_TYPE_DDR3            0
112 #define MDMISC_DDR_TYPE_LPDDR2          1
113 #define MDMISC_DDR_TYPE_DDR2            2
114
115 #define DIV_ROUND_UP(m,d)               (((m) + (d) - 1) / (d))
116
117 #define MDOR_CLK_PERIOD_ns              15258   /* base clock for MDOR values */
118
119 /* DDR3 SDRAM */
120 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
121 #define BANK_ADDR_BITS                  2
122 #else
123 #define BANK_ADDR_BITS                  1
124 #endif
125 #define SDRAM_BURST_LENGTH              8
126 #define RALAT                           5
127 #define WALAT                           0
128 #define BI_ON                           0
129 #define ADDR_MIRROR                     0
130 #define DDR_TYPE                        MDMISC_DDR_TYPE_DDR3
131
132 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
133 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
134 #define CL_VAL  11
135 #define CWL_VAL 8
136 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
137 #define CL_VAL  9 // or 10
138 #define CWL_VAL 7
139 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
140 #define CL_VAL  7 // or 8
141 #define CWL_VAL 6
142 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
143 #define CL_VAL  6
144 #define CWL_VAL 5
145 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
146 #define CL_VAL  5
147 #define CWL_VAL 5
148 #else
149 #error SDRAM clock out of range: 303 .. 800
150 #endif
151
152 /* MDCFG0 0x0c */
153 NS_VAL  tRFC,   160, 1, 255             /* clks - 1 (0..255) */
154 CK_MAX  tXS,    NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
155 CK_MAX  tXP,    NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
156 CK_MAX  tXPDLL, NS_TO_CK(24), 2, 1, 15  /* clks - 1 (0..15) */
157 NS_VAL  tFAW,   50, 1, 31               /* clks - 1 (0..31) */
158 CK_VAL  tCL,    CL_VAL, 3, 8            /* clks - 3 (0..8) CAS Latency */
159
160 /* MDCFG1 0x10 */
161 CK_VAL  tRCD,   NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */
162 CK_VAL  tRP,    NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */
163 NS_VAL  tRC,    50, 1, 31               /* clks - 1 (0..31) */
164 CK_VAL  tRAS,   NS_TO_CK10(375), 1, 31  /* clks - 1 (0..31) */ /* 37.5 */
165 CK_VAL  tRPA,   1, 0, 1                 /* clks     (0..1) */
166 NS_VAL  tWR,    15, 1, 15               /* clks - 1 (0..15) */
167 CK_VAL  tMRD,   4, 1, 15                /* clks - 1 (0..15) */
168 CK_VAL  tCWL,   CWL_VAL, 2, 6           /* clks - 2 (0..6) */
169
170 /* MDCFG2 0x14 */
171 CK_VAL  tDLLK,  512, 1, 511             /* clks - 1 (0..511) */
172 CK_MAX  tRTP,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
173 CK_MAX  tWTR,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
174 CK_MAX  tRRD,   NS_TO_CK(10), 4, 1, 7   /* clks - 1 (0..7) */
175
176 /* MDOR 0x30 */
177 CK_MAX  tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
178 #define tSDE_RST        (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
179 #define tRST_CKE        (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
180
181 /* MDOTC 0x08 */
182 CK_VAL  tAOFPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
183 CK_VAL  tAONPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
184 CK_VAL  tANPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
185 CK_VAL  tAXPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
186 CK_VAL  tODTLon tCWL, 0, 7              /* clks - 1 (0..7) */ /* CWL+AL-2 */
187 CK_VAL  tODTLoff tCWL, 0, 31            /* clks - 1 (0..31) */ /* CWL+AL-2 */
188
189 /* MDPDC 0x04 */
190 CK_MAX  tCKE,   NS_TO_CK(5), 3, 1, 7
191 CK_MAX  tCKSRX, NS_TO_CK(10), 5, 0, 7
192 CK_MAX  tCKSRE, NS_TO_CK(10), 5, 0, 7
193
194 #define PRCT            0
195 #define PWDT            5
196 #define SLOW_PD         0
197 #define BOTH_CS_PD      1
198
199 #define MDPDC_VAL_0     (       \
200         (PRCT << 28) |          \
201         (PRCT << 24) |          \
202         (tCKE << 16) |          \
203         (SLOW_PD << 7) |        \
204         (BOTH_CS_PD << 6) |     \
205         (tCKSRX << 3) |         \
206         (tCKSRE << 0)           \
207         )
208
209 #define MDPDC_VAL_1     (MDPDC_VAL_0 |          \
210         (PWDT << 12) |                          \
211         (PWDT << 8)                             \
212         )
213
214 #define ROW_ADDR_BITS                   14
215 #define COL_ADDR_BITS                   10
216
217 #define Rtt_Nom                         1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
218 #define Rtt_WR                          0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
219 #define DLL_DISABLE                     0
220
221         .iflt   tWR - 7
222         .set    mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ |    \
223                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
224                         ((tWR + 1 - 4) << 9) |                          \
225                         ((((tCL + 3) - 4) & 0x7) << 4) |                \
226                         ((((tCL + 3) - 4) & 0x8) >> 1))
227         .else
228         .set    mr0_val, ((1 << 8) /* DLL Reset */ |                    \
229                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
230                         (((tWR + 1) / 2) << 9) |        \
231                         ((((tCL + 3) - 4) & 0x7) << 4) | \
232                         ((((tCL + 3) - 4) & 0x8) >> 1))
233         .endif
234
235 #define mr1_val                         (                                       \
236                                          ((Rtt_Nom & 1) << 2) |                 \
237                                          (((Rtt_Nom >> 1) & 1) << 6) |          \
238                                          (((Rtt_Nom >> 2) & 1) << 9) |          \
239                                          (DLL_DISABLE << 0) |                   \
240                                         0)
241 #define mr2_val                         (                                       \
242                                          (Rtt_WR << 9) /* dynamic ODT */ |      \
243                                          (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
244                                          (1 << 6) | /* ASR: Automatic Self Refresh */ \
245                                          (((tCWL + 2) - 5) << 3) |              \
246                                         0)
247 #define mr3_val                         0
248
249 #define MDSCR_MRS_VAL(cs, mr, val)      (((val) << 16) |                \
250                                         (1 << 15) /* CON_REQ */ |       \
251                                         (3 << 4) /* MRS command */ |    \
252                                         ((cs) << 3) |                   \
253                                         ((mr) << 0) |                   \
254                                         0)
255
256 #define MDCFG0_VAL      (       \
257         (tRFC << 24) |          \
258         (tXS << 16) |           \
259         (tXP << 13) |           \
260         (tXPDLL << 9) |         \
261         (tFAW << 4) |           \
262         (tCL << 0))             \
263
264 #define MDCFG1_VAL      (       \
265         (tRCD << 29) |          \
266         (tRP << 26) |           \
267         (tRC << 21) |           \
268         (tRAS << 16) |          \
269         (tRPA << 15) |          \
270         (tWR << 9) |            \
271         (tMRD << 5) |           \
272         (tCWL << 0))            \
273
274 #define MDCFG2_VAL      (       \
275         (tDLLK << 16) |         \
276         (tRTP << 6) |           \
277         (tWTR << 3) |           \
278         (tRRD << 0))
279
280 #define BURST_LEN               (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
281
282 #define MDCTL_VAL               (((ROW_ADDR_BITS - 11) << 24) |         \
283                                 ((COL_ADDR_BITS - 9) << 20) |           \
284                                 (BURST_LEN << 19) |                     \
285                                 ((PHYS_SDRAM_1_WIDTH / 32) << 16) |     \
286                                 ((-1) << (32 - BANK_ADDR_BITS)))
287
288 #define MDMISC_VAL              ((ADDR_MIRROR << 19) |  \
289                                 (WALAT << 16) |         \
290                                 (BI_ON << 12) |         \
291                                 (0x3 << 9) |            \
292                                 (RALAT << 6) |          \
293                                 (DDR_TYPE << 3))
294
295 #define MDOR_VAL                ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
296
297 #define MDOTC_VAL               ((tAOFPD << 27) |       \
298                                 (tAONPD << 24) |        \
299                                 (tANPD << 20) |         \
300                                 (tAXPD << 16) |         \
301                                 (tODTLon << 12) |       \
302                                 (tODTLoff << 4))
303
304 ivt_header:
305         .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
306 app_start_addr:
307         .long   _start
308         .long   0x0
309 dcd_ptr:
310         .long   dcd_hdr
311 boot_data_ptr:
312         .word   boot_data
313 self_ptr:
314         .word   ivt_header
315 app_code_csf:
316         .word   0x0
317         .word   0x0
318 boot_data:
319         .long   _start
320 image_len:
321         .long   CONFIG_U_BOOT_IMG_SIZE
322 plugin:
323         .word   0
324 ivt_end:
325 #define DCD_VERSION     0x40
326
327 #define CLKCTL_CCGR0    0x68
328 #define CLKCTL_CCGR1    0x6c
329 #define CLKCTL_CCGR2    0x70
330 #define CLKCTL_CCGR3    0x74
331 #define CLKCTL_CCGR4    0x78
332 #define CLKCTL_CCGR5    0x7c
333 #define CLKCTL_CCGR6    0x80
334 #define CLKCTL_CCGR7    0x84
335 #define CLKCTL_CMEOR    0x88
336
337 #define DDR_SEL_VAL     3
338 #define DSE_VAL         6
339 #define ODT_VAL         2
340
341 #define DDR_SEL_SHIFT   18
342 #define DDR_MODE_SHIFT  17
343 #define ODT_SHIFT       8
344 #define DSE_SHIFT       3
345 #define HYS_SHIFT       16
346 #define PKE_SHIFT       12
347 #define PUE_SHIFT       13
348 #define PUS_SHIFT       14
349
350 #define DDR_SEL_MASK    (DDR_SEL_VAL << DDR_SEL_SHIFT)
351 #define DDR_MODE_MASK   (1 << DDR_MODE_SHIFT)
352 #define DSE_MASK        (DSE_VAL << DSE_SHIFT)
353 #define ODT_MASK        (ODT_VAL << ODT_SHIFT)
354
355 #define DQM_MASK        (DDR_MODE_MASK | DSE_MASK)
356 #define SDQS_MASK       DSE_MASK
357 #define SDODT_MASK      (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
358 #define SDCLK_MASK      (DDR_MODE_MASK | DSE_MASK)
359 #define SDCKE_MASK      ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
360 #define DDR_ADDR_MASK   0
361 #define DDR_CTRL_MASK   (DDR_MODE_MASK | DSE_MASK)
362
363 #define MMDC1_MDCTL                             0x021b0000
364 #define MMDC1_MDPDC                             0x021b0004
365 #define MMDC1_MDOTC                             0x021b0008
366 #define MMDC1_MDCFG0                            0x021b000c
367 #define MMDC1_MDCFG1                            0x021b0010
368 #define MMDC1_MDCFG2                            0x021b0014
369 #define MMDC1_MDMISC                            0x021b0018
370 #define MMDC1_MDSCR                             0x021b001c
371 #define MMDC1_MDREF                             0x021b0020
372 #define MMDC1_MDRWD                             0x021b002c
373 #define MMDC1_MDOR                              0x021b0030
374 #define MMDC1_MDASP                             0x021b0040
375 #define MMDC1_MAPSR                             0x021b0404
376 #define MMDC1_MPZQHWCTRL                        0x021b0800
377 #define MMDC1_MPWLGCR                           0x021b0808
378 #define MMDC1_MPWLDECTRL0                       0x021b080c
379 #define MMDC1_MPWLDECTRL1                       0x021b0810
380 #define MMDC1_MPWLDLST                          0x021b0814
381 #define MMDC1_MPODTCTRL                         0x021b0818
382 #define MMDC1_MPRDDQBY0DL                       0x021b081c
383 #define MMDC1_MPRDDQBY1DL                       0x021b0820
384 #define MMDC1_MPRDDQBY2DL                       0x021b0824
385 #define MMDC1_MPRDDQBY3DL                       0x021b0828
386 #define MMDC1_MPDGCTRL0                         0x021b083c
387 #define MMDC1_MPDGCTRL1                         0x021b0840
388 #define MMDC1_MPDGDLST0                         0x021b0844
389 #define MMDC1_MPWRDLST                          0x021b0854
390 #define MMDC1_MPRDDLCTL                         0x021b0848
391 #define MMDC1_MPRDDLST                          0x021b084c
392 #define MMDC1_MPWRDLCTL                         0x021b0850
393 #define MMDC1_MPWRDLST                          0x021b0854
394 #define MMDC1_MPRDDLHWCTL                       0x021b0860
395 #define MMDC1_MPWRDLHWCTL                       0x021b0864
396 #define MMDC1_MPPDCMPR2                         0x021b0890
397 #define MMDC1_MPSWDRDR0                         0x021b0898
398 #define MMDC1_MPSWDRDR1                         0x021b089c
399 #define MMDC1_MPSWDRDR2                         0x021b08a0
400 #define MMDC1_MPSWDRDR3                         0x021b08a4
401 #define MMDC1_MPSWDRDR4                         0x021b08a8
402 #define MMDC1_MPSWDRDR5                         0x021b08ac
403 #define MMDC1_MPSWDRDR6                         0x021b08b0
404 #define MMDC1_MPSWDRDR7                         0x021b08b4
405 #define MMDC1_MPMUR0                            0x021b08b8
406
407 #if PHYS_SDRAM_1_WIDTH == 64
408 #define MMDC2_MDPDC                             0x021b4004
409 #define MMDC2_MPWLGCR                           0x021b4808
410 #define MMDC2_MPWLDECTRL0                       0x021b480c
411 #define MMDC2_MPWLDECTRL1                       0x021b4810
412 #define MMDC2_MPWLDLST                          0x021b4814
413 #define MMDC2_MPODTCTRL                         0x021b4818
414 #define MMDC2_MPRDDQBY0DL                       0x021b481c
415 #define MMDC2_MPRDDQBY1DL                       0x021b4820
416 #define MMDC2_MPRDDQBY2DL                       0x021b4824
417 #define MMDC2_MPRDDQBY3DL                       0x021b4828
418 #define MMDC2_MPDGCTRL0                         0x021b483c
419 #define MMDC2_MPDGCTRL1                         0x021b4840
420 #define MMDC2_MPDGDLST0                         0x021b4844
421 #define MMDC2_MPRDDLCTL                         0x021b4848
422 #define MMDC2_MPRDDLST                          0x021b484c
423 #define MMDC2_MPWRDLCTL                         0x021b4850
424 #define MMDC2_MPWRDLST                          0x021b4854
425 #define MMDC2_MPRDDLHWCTL                       0x021b4860
426 #define MMDC2_MPWRDLHWCTL                       0x021b4864
427 #define MMDC2_MPRDDLHWST0                       0x021b4868
428 #define MMDC2_MPRDDLHWST1                       0x021b486c
429 #define MMDC2_MPWRDLHWST0                       0x021b4870
430 #define MMDC2_MPWRDLHWST1                       0x021b4874
431 #define MMDC2_MPWLHWERR                         0x021b4878
432 #define MMDC2_MPDGHWST0                         0x021b487c
433 #define MMDC2_MPDGHWST1                         0x021b4880
434 #define MMDC2_MPDGHWST2                         0x021b4884
435 #define MMDC2_MPDGHWST3                         0x021b4888
436 #define MMDC2_MPSWDAR0                          0x021b4894
437 #define MMDC2_MPSWDRDR0                         0x021b4898
438 #define MMDC2_MPSWDRDR1                         0x021b489c
439 #define MMDC2_MPSWDRDR2                         0x021b48a0
440 #define MMDC2_MPSWDRDR3                         0x021b48a4
441 #define MMDC2_MPSWDRDR4                         0x021b48a8
442 #define MMDC2_MPSWDRDR5                         0x021b48ac
443 #define MMDC2_MPSWDRDR6                         0x021b48b0
444 #define MMDC2_MPSWDRDR7                         0x021b48b4
445 #endif
446
447 #ifdef CONFIG_MX6Q
448 #define IOMUXC_GPR1                             0x020e0004
449 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e024c
450 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e02a8
451 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e02ac
452 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e02c0
453 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e02c4
454 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e02d4
455 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e02d8
456 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02dc
457 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02e0
458 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e02e4
459 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e02ec
460 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e02f4
461 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e02f8
462 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e02fc
463 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0300
464 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e0304
465 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0308
466 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e030c
467 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0310
468 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e0314
469 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e0318
470 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e050c
471 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0510
472 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0514
473 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e0518
474 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e051c
475 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e0520
476 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e0524
477 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0528
478 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e052c
479 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0530
480 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0534
481 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0538
482 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e053c
483 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0540
484 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0544
485 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0548
486 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e054c
487 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0550
488 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e0554
489 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0558
490 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e055c
491 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0560
492 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e0564
493 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0568
494 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e056c
495 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0578
496 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e057c
497 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0580
498 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e0584
499 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e0588
500 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e058c
501 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e0590
502 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e0594
503 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e0598
504 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e059c
505 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e05a0
506 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e05a8
507 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e05ac
508 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e05b0
509 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e05b4
510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e05b8
511 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e05bc
512 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e05c0
513 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e05c4
514 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
515 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
516 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
517 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0         0x020e0754
518 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0758
519 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1         0x020e075c
520 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2         0x020e0760
521 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3         0x020e0764
522 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0768
523 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4         0x020e076c
524 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e0770
525 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0774
526 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5         0x020e0778
527 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6         0x020e077c
528 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7         0x020e0780
529 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
530 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
531 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
532 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
533 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
534 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
535 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
536 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
537 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
538 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
539 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
540 #endif
541
542 #ifdef CONFIG_MX6DL
543 #define IOMUXC_GPR1                             0x020e0004
544 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e0218
545 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e0330
546 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e032c
547 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e0314
548 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e0318
549 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e0270
550 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e026c
551 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02a8
552 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02a4
553 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e0274
554 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e027c
555 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e033c
556 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e0338
557 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e0284
558 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0288
559 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e028c
560 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0290
561 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e0294
562 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0298
563 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e029c
564 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e02a0
565 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e04d0
566 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0484
567 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0480
568 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e04cc
569 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e04c8
570 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e047c
571 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e04c4
572 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0478
573 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e0424
574 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0428
575 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0444
576 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0448
577 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e044c
578 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0450
579 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0454
580 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0458
581 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e045c
582 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0460
583 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e042c
584 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0430
585 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e0434
586 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0438
587 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e043c
588 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0440
589 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e0464
590 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0490
591 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e0494
592 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0498
593 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e049c
594 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e04ac
595 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e04a0
596 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e04a4
597 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e04b0
598 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e04a8
599 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e04b4
600 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e04b8
601 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e04bc
602 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e0470
603 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e04c0
604 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e0474
605 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e04d4
606 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e0488
607 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e04d8
608 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e048c
609 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
610 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
611 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
612 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0754
613 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0754
614 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e075c
615 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0760
616 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
617 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
618 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
619 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
620 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
621 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
622 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
623 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
624 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
625 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
626 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
627 #endif
628
629 dcd_hdr:
630         .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
631 dcd_start:
632         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
633         /* RESET_OUT GPIO_7_12 */
634         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
635
636         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */
637
638         MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
639
640         /* enable all relevant clocks... */
641         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
642         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
643         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
644         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
645         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
646         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
647         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
648
649         /* IOMUX: */
650         MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
651         /* UART1 pad config */
652         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
653         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
654         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
655         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
656         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
657         MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
658
659         /* NAND */
660         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,    0x00000000)     /* NANDF_CLE: NANDF_CLE */
661         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,    0x00000000)     /* NANDF_ALE: NANDF_ALE */
662         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B,   0x00000000)     /* NANDF_WP_B: NANDF_WPn */
663         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY,  0x00000000)     /* NANDF_RB0: NANDF_READY0 */
664         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B,  0x00000000)     /* NANDF_CS0: NANDF_CS0 */
665         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD,     0x00000001)     /* SD4_CMD: NANDF_RDn */
666         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK,     0x00000001)     /* SD4_CLK: NANDF_WRn */
667         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000)     /* NANDF_D0: NANDF_D0 */
668         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000)     /* NANDF_D1: NANDF_D1 */
669         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000)     /* NANDF_D2: NANDF_D2 */
670         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000)     /* NANDF_D3: NANDF_D3 */
671         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000)     /* NANDF_D4: NANDF_D4 */
672         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000)     /* NANDF_D5: NANDF_D5 */
673         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000)     /* NANDF_D6: NANDF_D6 */
674         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000)     /* NANDF_D7: NANDF_D7 */
675
676         /* ext. mem CS */
677         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
678         /* DRAM_DQM[0..7] */
679         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
680         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
681         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
682         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
683         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
684         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
685         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
686         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
687
688         /* DRAM_A[0..15] */
689         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
690         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
691         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
692         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
693         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
694         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
695         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
696         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
697         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
698         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
699         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
700         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
701         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
702         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
703         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
704         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
705         /* DRAM_CAS */
706         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
707         /* DRAM_RAS */
708         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
709         /* DRAM_SDCLK[0..1] */
710         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
711         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
712         /* DRAM_RESET */
713         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
714         /* DRAM_SDCKE[0..1] */
715         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
716         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
717         /* DRAM_SDBA[0..2] */
718         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
719         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
720         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
721         /* DRAM_SDODT[0..1] */
722         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
723         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
724         /* DRAM_B[0..7]DS */
725         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
726         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
727         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
728         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
729         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
730         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
731         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
732         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
733         /* ADDDS */
734         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
735         /* DDRMODE_CTL */
736         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
737         /* DDRPKE */
738         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
739         /* DDRMODE */
740         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
741         /* CTLDS */
742         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK)
743         /* DDR_TYPE */
744         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
745         /* DDRPK */
746         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
747         /* DDRHYS */
748         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
749
750 #ifdef CONFIG_MX6Q
751         /* TERM_CTL[0..7] */
752         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
753         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
754         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
755         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
756         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
757         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
758         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
759         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
760 #endif
761         /* SDRAM initialization */
762         /* MPRDDQBY[0..7]DL */
763         MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
764         MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
765         MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
766         MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
767         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
768         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
769         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
770         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
771         /* MDMISC */
772         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
773 ddr_reset:
774         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
775         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
776
777         /* MSDSCR Conf Req */
778         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
779 con_ack:
780         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
781         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
782         /* MDCTL */
783         MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
784 ddr_calib:
785         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
786         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
787
788         MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
789         MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
790         MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
791         MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2) /* MDRWD */
792         MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
793         MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
794         MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
795         MXC_DCD_ITEM_64(MMDC2_MDPDC,  MDPDC_VAL_0)
796         MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */
797
798         /* CS0 MRS: */
799         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
800         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
801         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
802         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
803 #if BANK_ADDR_BITS > 1
804         /* CS1 MRS: MR2 */
805         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
806         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
807         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
808         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
809 #endif
810
811         MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
812
813         MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222) /* MPODTCTRL */
814         MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
815
816         /* DDR3 calibration */
817         MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
818         MXC_DCD_ITEM(MMDC1_MAPSR,     0x00011007)
819
820         /* ZQ calibration */
821         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
822         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
823         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
824
825 zq_calib:
826         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
827         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
828
829         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
830
831 #ifndef DO_WL_CALIB
832 #define WL_DLY_DQS_VAL  30
833 #define WL_DLY_DQS0     (WL_DLY_DQS_VAL + 0)
834 #define WL_DLY_DQS1     (WL_DLY_DQS_VAL + 0)
835 #define WL_DLY_DQS2     (WL_DLY_DQS_VAL + 0)
836 #define WL_DLY_DQS3     (WL_DLY_DQS_VAL + 0)
837 #define WL_DLY_DQS4     (WL_DLY_DQS_VAL + 0)
838 #define WL_DLY_DQS5     (WL_DLY_DQS_VAL + 0)
839 #define WL_DLY_DQS6     (WL_DLY_DQS_VAL + 0)
840 #define WL_DLY_DQS7     (WL_DLY_DQS_VAL + 0)
841 #endif
842         /* Write leveling */
843         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
844 #ifdef DO_WL_CALIB
845         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
846         MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
847 wl_calib:
848         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
849         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
850 #if PHYS_SDRAM_1_WIDTH == 64
851         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
852         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
853 #endif /* PHYS_SDRAM_1_WIDTH == 64 */
854 #else
855         MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
856         MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
857         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
858         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
859 wl_calib:
860 #endif /* DO_WL_CALIB */
861         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
862
863         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
864
865         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
866
867         /* DQS gating calibration */
868         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
869         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
870         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
871         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
872         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
873         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
874         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
875         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
876
877         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
878
879         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
880         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
881
882         MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
883         MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
884         MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
885         MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
886         MXC_DCD_ITEM(MMDC1_MPMUR0,    0x00000800)
887         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
888 dqs_fifo_reset:
889         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
890         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
891         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
892 dqs_fifo_reset2:
893         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
894         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
895         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
896 dqs_calib:
897         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
898         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
899         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
900
901         /* DRAM_SDQS[0..7] pad config */
902         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
903         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
904         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
905         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
906         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
907         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
908         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
909         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
910         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
911
912         /* Read delay calibration */
913         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
914         MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
915         MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
916 rd_dl_calib:
917         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
918         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
919         MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
920         MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
921         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
922
923         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
924         MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
925 wr_dl_calib:
926         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
927         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
928 #if PHYS_SDRAM_1_WIDTH == 64
929         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib2)
930
931         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
932         MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
933 wr_dl_calib2:
934         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
935         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
936 #endif
937         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
938
939         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
940         MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
941         MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011006) /* MAPSR */
942         MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
943         MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
944
945         /* MDSCR: Normal operation */
946         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
947
948 con_ack_clr:
949         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
950 dcd_end:
951         .ifgt   dcd_end - dcd_start - 1768
952         .error  "DCD too large!"
953         .endif