merged tx6dl-devel into denx master branch
[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S
1 #include <config.h>
2 #include <configs/tx6.h>
3 #include <asm/arch/imx-regs.h>
4 #include <generated/asm-offsets.h>
5
6 //#define DO_WL_CALIB
7
8 #ifndef CCM_CCR
9 #error asm-offsets not included
10 #endif
11
12 #define DEBUG_LED_BIT           20
13 #define LED_GPIO_BASE           GPIO2_BASE_ADDR
14 #define LED_MUX_OFFSET          0x0ec
15 #define LED_MUX_MODE            0x15
16
17 #define SDRAM_CLK               CONFIG_SYS_SDRAM_CLK
18
19 #ifdef PHYS_SDRAM_2_SIZE
20 #define SDRAM_SIZE              (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
21 #else
22 #define SDRAM_SIZE              PHYS_SDRAM_1_SIZE
23 #endif
24
25 #define CPU_2_BE_32(l)                  \
26         ((((l) << 24) & 0xFF000000) |   \
27         (((l) << 8) & 0x00FF0000) |     \
28         (((l) >> 8) & 0x0000FF00) |     \
29         (((l) >> 24) & 0x000000FF))
30
31 #define CHECK_DCD_ADDR(a)       (                       \
32         ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
33         ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||   \
34         ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
35         ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||  \
36         ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
37         ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
38         ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
39
40         .macro  mxc_dcd_item    addr, val
41         .ifne   CHECK_DCD_ADDR(\addr)
42         .word   CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
43         .else
44         .error  "Address \addr not accessible from DCD"
45         .endif
46         .endm
47
48 #define MXC_DCD_ITEM(addr, val)         mxc_dcd_item    addr, val
49 #if PHYS_SDRAM_1_WIDTH == 64
50 #define MXC_DCD_ITEM_64(addr, val)              mxc_dcd_item    addr, val
51 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
52 #else
53 #define MXC_DCD_ITEM_64(addr, val)
54 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask)
55 #endif
56
57 #define MXC_DCD_CMD_SZ_BYTE             1
58 #define MXC_DCD_CMD_SZ_SHORT            2
59 #define MXC_DCD_CMD_SZ_WORD             4
60 #define MXC_DCD_CMD_FLAG_WRITE          0x0
61 #define MXC_DCD_CMD_FLAG_CLR            0x1
62 #define MXC_DCD_CMD_FLAG_SET            0x3
63 #define MXC_DCD_CMD_FLAG_CHK_ANY        (1 << 0)
64 #define MXC_DCD_CMD_FLAG_CHK_SET        (1 << 1)
65 #define MXC_DCD_CMD_FLAG_CHK_CLR        (0 << 1)
66
67 #define MXC_DCD_CMD_WRT(type, flags, next)                                      \
68         .word   CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
69
70 #define MXC_DCD_CMD_CHK(type, flags, addr, mask)                                \
71         .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
72                 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
73
74 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)                     \
75         .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
76                 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
77
78 #define MXC_DCD_CMD_NOP()                                                       \
79         .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
80
81 #define CK_TO_NS(ck)    (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
82 #define NS_TO_CK(ns)    (((ns) * SDRAM_CLK + 999) / 1000)
83 #define NS_TO_CK10(ns)  DIV_ROUND_UP(NS_TO_CK(ns), 10)
84
85         .macro          CK_VAL, name, clks, offs, max
86         .iflt           \clks - \offs
87         .set            \name, 0
88         .else
89         .ifle           \clks - \offs - \max
90         .set            \name, \clks - \offs
91         .else
92         .error          "Value \clks out of range for parameter \name"
93         .endif
94         .endif
95         .endm
96
97         .macro          NS_VAL, name, ns, offs, max
98         .iflt           \ns - \offs
99         .set            \name, 0
100         .else
101         CK_VAL          \name, NS_TO_CK(\ns), \offs, \max
102         .endif
103         .endm
104
105         .macro          CK_MAX, name, ck1, ck2, offs, max
106         .ifgt           \ck1 - \ck2
107         CK_VAL          \name, \ck1, \offs, \max
108         .else
109         CK_VAL          \name, \ck2, \offs, \max
110         .endif
111         .endm
112
113 #define MDMISC_DDR_TYPE_DDR3            0
114 #define MDMISC_DDR_TYPE_LPDDR2          1
115 #define MDMISC_DDR_TYPE_DDR2            2
116
117 #define DIV_ROUND_UP(m,d)               (((m) + (d) - 1) / (d))
118
119 #define MDOR_CLK_PERIOD_ns              15258   /* base clock for MDOR values */
120
121 /* DDR3 SDRAM */
122 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
123 #define BANK_ADDR_BITS                  2
124 #else
125 #define BANK_ADDR_BITS                  1
126 #endif
127 #define SDRAM_BURST_LENGTH              8
128 #define RALAT                           5
129 #define WALAT                           0
130 #define BI_ON                           0
131 #define ADDR_MIRROR                     0
132 #define DDR_TYPE                        MDMISC_DDR_TYPE_DDR3
133
134 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
135 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
136 #define CL_VAL  11
137 #define CWL_VAL 8
138 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
139 #define CL_VAL  9 // or 10
140 #define CWL_VAL 7
141 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
142 #define CL_VAL  7 // or 8
143 #define CWL_VAL 6
144 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
145 #define CL_VAL  6
146 #define CWL_VAL 5
147 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
148 #define CL_VAL  5
149 #define CWL_VAL 5
150 #else
151 #error SDRAM clock out of range: 303 .. 800
152 #endif
153
154 /* MDCFG0 0x0c */
155 NS_VAL  tRFC,   160, 1, 255             /* clks - 1 (0..255) */
156 CK_MAX  tXS,    NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
157 CK_MAX  tXP,    NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
158 CK_MAX  tXPDLL, NS_TO_CK(24), 2, 1, 15  /* clks - 1 (0..15) */
159 NS_VAL  tFAW,   50, 1, 31               /* clks - 1 (0..31) */
160 CK_VAL  tCL,    CL_VAL, 3, 8            /* clks - 3 (0..8) CAS Latency */
161
162 /* MDCFG1 0x10 */
163 CK_VAL  tRCD,   NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */
164 CK_VAL  tRP,    NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */
165 NS_VAL  tRC,    50, 1, 31               /* clks - 1 (0..31) */
166 CK_VAL  tRAS,   NS_TO_CK10(375), 1, 31  /* clks - 1 (0..31) */ /* 37.5 */
167 CK_VAL  tRPA,   1, 0, 1                 /* clks     (0..1) */
168 NS_VAL  tWR,    15, 1, 15               /* clks - 1 (0..15) */
169 CK_VAL  tMRD,   4, 1, 15                /* clks - 1 (0..15) */
170 CK_VAL  tCWL,   CWL_VAL, 2, 6           /* clks - 2 (0..6) */
171
172 /* MDCFG2 0x14 */
173 CK_VAL  tDLLK,  512, 1, 511             /* clks - 1 (0..511) */
174 CK_MAX  tRTP,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
175 CK_MAX  tWTR,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
176 CK_MAX  tRRD,   NS_TO_CK(10), 4, 1, 7   /* clks - 1 (0..7) */
177
178 /* MDOR 0x30 */
179 CK_MAX  tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
180 #define tSDE_RST        (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
181 #define tRST_CKE        (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
182
183 /* MDOTC 0x08 */
184 CK_VAL  tAOFPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
185 CK_VAL  tAONPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
186 CK_VAL  tANPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
187 CK_VAL  tAXPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
188 CK_VAL  tODTLon tCWL, 0, 7              /* clks - 1 (0..7) */ /* CWL+AL-2 */
189 CK_VAL  tODTLoff tCWL, 0, 31            /* clks - 1 (0..31) */ /* CWL+AL-2 */
190
191 /* MDPDC 0x04 */
192 CK_MAX  tCKE,   NS_TO_CK(5), 3, 1, 7
193 CK_MAX  tCKSRX, NS_TO_CK(10), 5, 0, 7
194 CK_MAX  tCKSRE, NS_TO_CK(10), 5, 0, 7
195
196 #define PRCT            0
197 #define PWDT            5
198 #define SLOW_PD         0
199 #define BOTH_CS_PD      1
200
201 #define MDPDC_VAL_0     (       \
202         (PRCT << 28) |          \
203         (PRCT << 24) |          \
204         (tCKE << 16) |          \
205         (SLOW_PD << 7) |        \
206         (BOTH_CS_PD << 6) |     \
207         (tCKSRX << 3) |         \
208         (tCKSRE << 0)           \
209         )
210
211 #define MDPDC_VAL_1     (MDPDC_VAL_0 |          \
212         (PWDT << 12) |                          \
213         (PWDT << 8)                             \
214         )
215
216 #define ROW_ADDR_BITS                   14
217 #define COL_ADDR_BITS                   10
218
219 #define Rtt_Nom                         1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
220 #define Rtt_WR                          0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
221 #define DLL_DISABLE                     0
222
223         .iflt   tWR - 7
224         .set    mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ |    \
225                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
226                         ((tWR + 1 - 4) << 9) |                          \
227                         ((((tCL + 3) - 4) & 0x7) << 4) |                \
228                         ((((tCL + 3) - 4) & 0x8) >> 1))
229         .else
230         .set    mr0_val, ((1 << 8) /* DLL Reset */ |                    \
231                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
232                         (((tWR + 1) / 2) << 9) |        \
233                         ((((tCL + 3) - 4) & 0x7) << 4) | \
234                         ((((tCL + 3) - 4) & 0x8) >> 1))
235         .endif
236
237 #define mr1_val                         (                                       \
238                                          ((Rtt_Nom & 1) << 2) |                 \
239                                          (((Rtt_Nom >> 1) & 1) << 6) |          \
240                                          (((Rtt_Nom >> 2) & 1) << 9) |          \
241                                          (DLL_DISABLE << 0) |                   \
242                                         0)
243 #define mr2_val                         (                                       \
244                                          (Rtt_WR << 9) /* dynamic ODT */ |      \
245                                          (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
246                                          (1 << 6) | /* ASR: Automatic Self Refresh */ \
247                                          (((tCWL + 2) - 5) << 3) |              \
248                                         0)
249 #define mr3_val                         0
250
251 #define MDSCR_MRS_VAL(cs, mr, val)      (((val) << 16) |                \
252                                         (1 << 15) /* CON_REQ */ |       \
253                                         (3 << 4) /* MRS command */ |    \
254                                         ((cs) << 3) |                   \
255                                         ((mr) << 0) |                   \
256                                         0)
257
258 #define MDCFG0_VAL      (       \
259         (tRFC << 24) |          \
260         (tXS << 16) |           \
261         (tXP << 13) |           \
262         (tXPDLL << 9) |         \
263         (tFAW << 4) |           \
264         (tCL << 0))             \
265
266 #define MDCFG1_VAL      (       \
267         (tRCD << 29) |          \
268         (tRP << 26) |           \
269         (tRC << 21) |           \
270         (tRAS << 16) |          \
271         (tRPA << 15) |          \
272         (tWR << 9) |            \
273         (tMRD << 5) |           \
274         (tCWL << 0))            \
275
276 #define MDCFG2_VAL      (       \
277         (tDLLK << 16) |         \
278         (tRTP << 6) |           \
279         (tWTR << 3) |           \
280         (tRRD << 0))
281
282 #define BURST_LEN               (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
283
284 #define MDCTL_VAL               (((ROW_ADDR_BITS - 11) << 24) |         \
285                                 ((COL_ADDR_BITS - 9) << 20) |           \
286                                 (BURST_LEN << 19) |                     \
287                                 ((PHYS_SDRAM_1_WIDTH / 32) << 16) |     \
288                                 ((-1) << (32 - BANK_ADDR_BITS)))
289
290 #define MDMISC_VAL              ((ADDR_MIRROR << 19) |  \
291                                 (WALAT << 16) |         \
292                                 (BI_ON << 12) |         \
293                                 (0x3 << 9) |            \
294                                 (RALAT << 6) |          \
295                                 (DDR_TYPE << 3))
296
297 #define MDOR_VAL                ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
298
299 #define MDOTC_VAL               ((tAOFPD << 27) |       \
300                                 (tAONPD << 24) |        \
301                                 (tANPD << 20) |         \
302                                 (tAXPD << 16) |         \
303                                 (tODTLon << 12) |       \
304                                 (tODTLoff << 4))
305
306 ivt_header:
307         .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
308 app_start_addr:
309         .long   _start
310         .long   0x0
311 dcd_ptr:
312         .long   dcd_hdr
313 boot_data_ptr:
314         .word   boot_data
315 self_ptr:
316         .word   ivt_header
317 app_code_csf:
318         .word   0x0
319         .word   0x0
320 boot_data:
321         .long   _start
322 image_len:
323         .long   CONFIG_U_BOOT_IMG_SIZE
324 plugin:
325         .word   0
326 ivt_end:
327 #define DCD_VERSION     0x40
328
329 #define CLKCTL_CCGR0    0x68
330 #define CLKCTL_CCGR1    0x6c
331 #define CLKCTL_CCGR2    0x70
332 #define CLKCTL_CCGR3    0x74
333 #define CLKCTL_CCGR4    0x78
334 #define CLKCTL_CCGR5    0x7c
335 #define CLKCTL_CCGR6    0x80
336 #define CLKCTL_CCGR7    0x84
337 #define CLKCTL_CMEOR    0x88
338
339 #define DDR_SEL_VAL     3
340 #define DSE_VAL         6
341 #define ODT_VAL         2
342
343 #define DDR_SEL_SHIFT   18
344 #define DDR_MODE_SHIFT  17
345 #define ODT_SHIFT       8
346 #define DSE_SHIFT       3
347 #define HYS_SHIFT       16
348 #define PKE_SHIFT       12
349 #define PUE_SHIFT       13
350 #define PUS_SHIFT       14
351
352 #define DDR_SEL_MASK    (DDR_SEL_VAL << DDR_SEL_SHIFT)
353 #define DDR_MODE_MASK   (1 << DDR_MODE_SHIFT)
354 #define DSE_MASK        (DSE_VAL << DSE_SHIFT)
355 #define ODT_MASK        (ODT_VAL << ODT_SHIFT)
356
357 #define DQM_MASK        (DDR_MODE_MASK | DSE_MASK)
358 #define SDQS_MASK       DSE_MASK
359 #define SDODT_MASK      (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
360 #define SDCLK_MASK      (DDR_MODE_MASK | DSE_MASK)
361 #define SDCKE_MASK      ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
362 #define DDR_ADDR_MASK   0
363 #define DDR_CTRL_MASK   (DDR_MODE_MASK | DSE_MASK)
364
365 #define MMDC1_MDCTL                             0x021b0000
366 #define MMDC1_MDPDC                             0x021b0004
367 #define MMDC1_MDOTC                             0x021b0008
368 #define MMDC1_MDCFG0                            0x021b000c
369 #define MMDC1_MDCFG1                            0x021b0010
370 #define MMDC1_MDCFG2                            0x021b0014
371 #define MMDC1_MDMISC                            0x021b0018
372 #define MMDC1_MDSCR                             0x021b001c
373 #define MMDC1_MDREF                             0x021b0020
374 #define MMDC1_MDRWD                             0x021b002c
375 #define MMDC1_MDOR                              0x021b0030
376 #define MMDC1_MDASP                             0x021b0040
377 #define MMDC1_MAPSR                             0x021b0404
378 #define MMDC1_MPZQHWCTRL                        0x021b0800
379 #define MMDC1_MPWLGCR                           0x021b0808
380 #define MMDC1_MPWLDECTRL0                       0x021b080c
381 #define MMDC1_MPWLDECTRL1                       0x021b0810
382 #define MMDC1_MPWLDLST                          0x021b0814
383 #define MMDC1_MPODTCTRL                         0x021b0818
384 #define MMDC1_MPRDDQBY0DL                       0x021b081c
385 #define MMDC1_MPRDDQBY1DL                       0x021b0820
386 #define MMDC1_MPRDDQBY2DL                       0x021b0824
387 #define MMDC1_MPRDDQBY3DL                       0x021b0828
388 #define MMDC1_MPDGCTRL0                         0x021b083c
389 #define MMDC1_MPDGCTRL1                         0x021b0840
390 #define MMDC1_MPDGDLST0                         0x021b0844
391 #define MMDC1_MPWRDLST                          0x021b0854
392 #define MMDC1_MPRDDLCTL                         0x021b0848
393 #define MMDC1_MPRDDLST                          0x021b084c
394 #define MMDC1_MPWRDLCTL                         0x021b0850
395 #define MMDC1_MPWRDLST                          0x021b0854
396 #define MMDC1_MPRDDLHWCTL                       0x021b0860
397 #define MMDC1_MPWRDLHWCTL                       0x021b0864
398 #define MMDC1_MPPDCMPR2                         0x021b0890
399 #define MMDC1_MPSWDRDR0                         0x021b0898
400 #define MMDC1_MPSWDRDR1                         0x021b089c
401 #define MMDC1_MPSWDRDR2                         0x021b08a0
402 #define MMDC1_MPSWDRDR3                         0x021b08a4
403 #define MMDC1_MPSWDRDR4                         0x021b08a8
404 #define MMDC1_MPSWDRDR5                         0x021b08ac
405 #define MMDC1_MPSWDRDR6                         0x021b08b0
406 #define MMDC1_MPSWDRDR7                         0x021b08b4
407 #define MMDC1_MPMUR0                            0x021b08b8
408
409 #if PHYS_SDRAM_1_WIDTH == 64
410 #define MMDC2_MDPDC                             0x021b4004
411 #define MMDC2_MPWLGCR                           0x021b4808
412 #define MMDC2_MPWLDECTRL0                       0x021b480c
413 #define MMDC2_MPWLDECTRL1                       0x021b4810
414 #define MMDC2_MPWLDLST                          0x021b4814
415 #define MMDC2_MPODTCTRL                         0x021b4818
416 #define MMDC2_MPRDDQBY0DL                       0x021b481c
417 #define MMDC2_MPRDDQBY1DL                       0x021b4820
418 #define MMDC2_MPRDDQBY2DL                       0x021b4824
419 #define MMDC2_MPRDDQBY3DL                       0x021b4828
420 #define MMDC2_MPDGCTRL0                         0x021b483c
421 #define MMDC2_MPDGCTRL1                         0x021b4840
422 #define MMDC2_MPDGDLST0                         0x021b4844
423 #define MMDC2_MPRDDLCTL                         0x021b4848
424 #define MMDC2_MPRDDLST                          0x021b484c
425 #define MMDC2_MPWRDLCTL                         0x021b4850
426 #define MMDC2_MPWRDLST                          0x021b4854
427 #define MMDC2_MPRDDLHWCTL                       0x021b4860
428 #define MMDC2_MPWRDLHWCTL                       0x021b4864
429 #define MMDC2_MPRDDLHWST0                       0x021b4868
430 #define MMDC2_MPRDDLHWST1                       0x021b486c
431 #define MMDC2_MPWRDLHWST0                       0x021b4870
432 #define MMDC2_MPWRDLHWST1                       0x021b4874
433 #define MMDC2_MPWLHWERR                         0x021b4878
434 #define MMDC2_MPDGHWST0                         0x021b487c
435 #define MMDC2_MPDGHWST1                         0x021b4880
436 #define MMDC2_MPDGHWST2                         0x021b4884
437 #define MMDC2_MPDGHWST3                         0x021b4888
438 #define MMDC2_MPSWDAR0                          0x021b4894
439 #define MMDC2_MPSWDRDR0                         0x021b4898
440 #define MMDC2_MPSWDRDR1                         0x021b489c
441 #define MMDC2_MPSWDRDR2                         0x021b48a0
442 #define MMDC2_MPSWDRDR3                         0x021b48a4
443 #define MMDC2_MPSWDRDR4                         0x021b48a8
444 #define MMDC2_MPSWDRDR5                         0x021b48ac
445 #define MMDC2_MPSWDRDR6                         0x021b48b0
446 #define MMDC2_MPSWDRDR7                         0x021b48b4
447 #endif
448
449 #ifdef CONFIG_MX6Q
450 #define IOMUXC_GPR1                             0x020e0004
451 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e024c
452 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e02a8
453 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e02ac
454 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e02c0
455 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e02c4
456 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e02d4
457 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e02d8
458 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02dc
459 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02e0
460 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e02e4
461 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e02ec
462 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e02f4
463 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e02f8
464 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e02fc
465 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0300
466 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e0304
467 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0308
468 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e030c
469 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0310
470 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e0314
471 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e0318
472 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e050c
473 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0510
474 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0514
475 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e0518
476 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e051c
477 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e0520
478 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e0524
479 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0528
480 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e052c
481 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0530
482 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0534
483 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0538
484 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e053c
485 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0540
486 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0544
487 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0548
488 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e054c
489 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0550
490 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e0554
491 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0558
492 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e055c
493 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0560
494 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e0564
495 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0568
496 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e056c
497 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0578
498 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e057c
499 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0580
500 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e0584
501 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e0588
502 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e058c
503 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e0590
504 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e0594
505 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e0598
506 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e059c
507 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e05a0
508 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e05a8
509 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e05ac
510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e05b0
511 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e05b4
512 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e05b8
513 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e05bc
514 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e05c0
515 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e05c4
516 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
517 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
518 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
519 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0         0x020e0754
520 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0758
521 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1         0x020e075c
522 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2         0x020e0760
523 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3         0x020e0764
524 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0768
525 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4         0x020e076c
526 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e0770
527 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0774
528 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5         0x020e0778
529 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6         0x020e077c
530 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7         0x020e0780
531 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
532 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
533 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
534 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
535 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
536 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
537 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
538 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
539 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
540 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
541 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
542 #endif
543
544 #ifdef CONFIG_MX6DL
545 #define IOMUXC_GPR1                             0x020e0004
546 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e0218
547 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e0330
548 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e032c
549 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e0314
550 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e0318
551 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e0270
552 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e026c
553 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02a8
554 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02a4
555 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e0274
556 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e027c
557 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e033c
558 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e0338
559 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e0284
560 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0288
561 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e028c
562 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0290
563 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e0294
564 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0298
565 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e029c
566 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e02a0
567 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e04d0
568 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0484
569 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0480
570 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e04cc
571 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e04c8
572 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e047c
573 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e04c4
574 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0478
575 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e0424
576 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0428
577 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0444
578 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0448
579 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e044c
580 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0450
581 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0454
582 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0458
583 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e045c
584 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0460
585 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e042c
586 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0430
587 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e0434
588 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0438
589 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e043c
590 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0440
591 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e0464
592 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0490
593 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e0494
594 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0498
595 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e049c
596 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e04ac
597 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e04a0
598 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e04a4
599 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e04b0
600 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e04a8
601 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e04b4
602 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e04b8
603 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e04bc
604 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e0470
605 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e04c0
606 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e0474
607 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e04d4
608 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e0488
609 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e04d8
610 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e048c
611 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
612 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
613 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
614 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0754
615 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0754
616 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e075c
617 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0760
618 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
619 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
620 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
621 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
622 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
623 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
624 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
625 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
626 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
627 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
628 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
629 #endif
630
631 dcd_hdr:
632         .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
633 dcd_start:
634         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
635         /* RESET_OUT GPIO_7_12 */
636         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
637
638         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */
639
640         MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
641
642         /* enable all relevant clocks... */
643         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
644         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
645         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
646         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
647         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
648         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
649         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
650
651         /* IOMUX: */
652         MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
653         /* UART1 pad config */
654         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
655         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
656         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
657         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
658         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
659         MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
660
661         /* NAND */
662         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,    0x00000000)     /* NANDF_CLE: NANDF_CLE */
663         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,    0x00000000)     /* NANDF_ALE: NANDF_ALE */
664         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B,   0x00000000)     /* NANDF_WP_B: NANDF_WPn */
665         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY,  0x00000000)     /* NANDF_RB0: NANDF_READY0 */
666         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B,  0x00000000)     /* NANDF_CS0: NANDF_CS0 */
667         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD,     0x00000001)     /* SD4_CMD: NANDF_RDn */
668         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK,     0x00000001)     /* SD4_CLK: NANDF_WRn */
669         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000)     /* NANDF_D0: NANDF_D0 */
670         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000)     /* NANDF_D1: NANDF_D1 */
671         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000)     /* NANDF_D2: NANDF_D2 */
672         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000)     /* NANDF_D3: NANDF_D3 */
673         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000)     /* NANDF_D4: NANDF_D4 */
674         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000)     /* NANDF_D5: NANDF_D5 */
675         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000)     /* NANDF_D6: NANDF_D6 */
676         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000)     /* NANDF_D7: NANDF_D7 */
677
678         /* ext. mem CS */
679         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
680         /* DRAM_DQM[0..7] */
681         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
682         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
683         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
684         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
685         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
686         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
687         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
688         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
689
690         /* DRAM_A[0..15] */
691         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
692         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
693         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
694         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
695         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
696         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
697         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
698         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
699         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
700         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
701         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
702         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
703         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
704         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
705         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
706         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
707         /* DRAM_CAS */
708         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
709         /* DRAM_RAS */
710         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
711         /* DRAM_SDCLK[0..1] */
712         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
713         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
714         /* DRAM_RESET */
715         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
716         /* DRAM_SDCKE[0..1] */
717         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
718         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
719         /* DRAM_SDBA[0..2] */
720         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
721         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
722         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
723         /* DRAM_SDODT[0..1] */
724         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
725         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
726         /* DRAM_B[0..7]DS */
727         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
728         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
729         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
730         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
731         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
732         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
733         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
734         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
735         /* ADDDS */
736         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
737         /* DDRMODE_CTL */
738         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
739         /* DDRPKE */
740         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
741         /* DDRMODE */
742         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
743         /* CTLDS */
744         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK)
745         /* DDR_TYPE */
746         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
747         /* DDRPK */
748         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
749         /* DDRHYS */
750         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
751
752 #ifdef CONFIG_MX6Q
753         /* TERM_CTL[0..7] */
754         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
755         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
756         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
757         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
758         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
759         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
760         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
761         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
762 #endif
763         /* SDRAM initialization */
764         /* MPRDDQBY[0..7]DL */
765         MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
766         MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
767         MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
768         MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
769         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
770         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
771         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
772         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
773         /* MDMISC */
774         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
775 ddr_reset:
776         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
777         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
778
779         /* MSDSCR Conf Req */
780         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
781 con_ack:
782         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
783         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
784         /* MDCTL */
785         MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
786 ddr_calib:
787         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
788         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
789
790         MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
791         MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
792         MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
793         MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2) /* MDRWD */
794         MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
795         MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
796         MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
797         MXC_DCD_ITEM_64(MMDC2_MDPDC,  MDPDC_VAL_0)
798         MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */
799
800         /* CS0 MRS: */
801         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
802         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
803         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
804         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
805 #if BANK_ADDR_BITS > 1
806         /* CS1 MRS: MR2 */
807         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
808         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
809         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
810         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
811 #endif
812
813         MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
814
815         MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222) /* MPODTCTRL */
816         MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
817
818         /* DDR3 calibration */
819         MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
820         MXC_DCD_ITEM(MMDC1_MAPSR,     0x00011007)
821
822         /* ZQ calibration */
823         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
824         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
825         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
826
827 zq_calib:
828         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
829         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
830
831         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
832
833 #ifndef DO_WL_CALIB
834 #define WL_DLY_DQS_VAL  30
835 #define WL_DLY_DQS0     (WL_DLY_DQS_VAL + 0)
836 #define WL_DLY_DQS1     (WL_DLY_DQS_VAL + 0)
837 #define WL_DLY_DQS2     (WL_DLY_DQS_VAL + 0)
838 #define WL_DLY_DQS3     (WL_DLY_DQS_VAL + 0)
839 #define WL_DLY_DQS4     (WL_DLY_DQS_VAL + 0)
840 #define WL_DLY_DQS5     (WL_DLY_DQS_VAL + 0)
841 #define WL_DLY_DQS6     (WL_DLY_DQS_VAL + 0)
842 #define WL_DLY_DQS7     (WL_DLY_DQS_VAL + 0)
843 #endif
844         /* Write leveling */
845         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
846 #ifdef DO_WL_CALIB
847         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
848         MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
849 wl_calib:
850         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
851         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
852 #if PHYS_SDRAM_1_WIDTH == 64
853         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
854         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
855 #endif /* PHYS_SDRAM_1_WIDTH == 64 */
856 #else
857         MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
858         MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
859         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
860         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
861 wl_calib:
862 #endif /* DO_WL_CALIB */
863         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
864
865         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
866
867         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
868
869         /* DQS gating calibration */
870         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
871         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
872         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
873         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
874         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
875         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
876         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
877         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
878
879         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
880
881         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
882         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
883
884         MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
885         MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
886         MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
887         MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
888         MXC_DCD_ITEM(MMDC1_MPMUR0,    0x00000800)
889         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
890 dqs_fifo_reset:
891         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
892         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
893         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
894 dqs_fifo_reset2:
895         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
896         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
897         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
898 dqs_calib:
899         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
900         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
901         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
902
903         /* DRAM_SDQS[0..7] pad config */
904         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
905         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
906         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
907         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
908         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
909         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
910         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
911         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
912         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
913
914         /* Read delay calibration */
915         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
916         MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
917         MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
918 rd_dl_calib:
919         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
920         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
921         MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
922         MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
923         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
924
925         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
926         MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
927 wr_dl_calib:
928         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
929         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
930 #if PHYS_SDRAM_1_WIDTH == 64
931         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib2)
932
933         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
934         MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
935 wr_dl_calib2:
936         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
937         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
938 #endif
939         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
940
941         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
942         MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
943         MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011006) /* MAPSR */
944         MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
945         MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
946
947         /* MDSCR: Normal operation */
948         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
949
950 con_ack_clr:
951         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
952 dcd_end:
953         .ifgt   dcd_end - dcd_start - 1768
954         .error  "DCD too large!"
955         .endif