karo: tx6: Finalize support for TX6Q-1020
[karo-tx-uboot.git] / board / karo / tx6 / tx6-1020.c
1 /*
2  * Copyright (C) 2012,2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <common.h>
19 #include <errno.h>
20 #include <libfdt.h>
21 #include <fdt_support.h>
22 #include <lcd.h>
23 #include <netdev.h>
24 #include <mmc.h>
25 #include <fsl_esdhc.h>
26 #include <video_fb.h>
27 #include <ipu.h>
28 #include <mxcfb.h>
29 #include <i2c.h>
30 #include <linux/fb.h>
31 #include <asm/io.h>
32 #include <asm/gpio.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
38
39 #include "../common/karo.h"
40
41 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
42 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
43 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
44 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
45
46 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
47 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
48 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
49
50 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
51
52 #define TEMPERATURE_MIN                 -40
53 #define TEMPERATURE_HOT                 80
54 #define TEMPERATURE_MAX                 125
55
56 DECLARE_GLOBAL_DATA_PTR;
57
58 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
59
60 static const iomux_v3_cfg_t tx6qdl_pads[] = {
61         /* RESET_OUT */
62         MX6_PAD_GPIO_17__GPIO_7_12,
63
64         /* UART pads */
65 #if CONFIG_MXC_UART_BASE == UART1_BASE
66         MX6_PAD_SD3_DAT7__UART1_TXD,
67         MX6_PAD_SD3_DAT6__UART1_RXD,
68         MX6_PAD_SD3_DAT1__UART1_RTS,
69         MX6_PAD_SD3_DAT0__UART1_CTS,
70 #endif
71 #if CONFIG_MXC_UART_BASE == UART2_BASE
72         MX6_PAD_SD4_DAT4__UART2_RXD,
73         MX6_PAD_SD4_DAT7__UART2_TXD,
74         MX6_PAD_SD4_DAT5__UART2_RTS,
75         MX6_PAD_SD4_DAT6__UART2_CTS,
76 #endif
77 #if CONFIG_MXC_UART_BASE == UART3_BASE
78         MX6_PAD_EIM_D24__UART3_TXD,
79         MX6_PAD_EIM_D25__UART3_RXD,
80         MX6_PAD_SD3_RST__UART3_RTS,
81         MX6_PAD_SD3_DAT3__UART3_CTS,
82 #endif
83         /* internal I2C */
84         MX6_PAD_EIM_D28__I2C1_SDA,
85         MX6_PAD_EIM_D21__I2C1_SCL,
86
87         /* FEC PHY GPIO functions */
88         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
89         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
90         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
91 };
92
93 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
94         /* FEC functions */
95         MX6_PAD_ENET_MDC__ENET_MDC,
96         MX6_PAD_ENET_MDIO__ENET_MDIO,
97         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
98         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
99         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
100         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
101         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
102         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
103         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
104         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
105 };
106
107 static const struct gpio tx6qdl_gpios[] = {
108         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
109         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
110         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
111         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
112 };
113
114 /*
115  * Functions
116  */
117 /* placed in section '.data' to prevent overwriting relocation info
118  * overlayed with bss
119  */
120 static u32 wrsr __attribute__((section(".data")));
121
122 #define WRSR_POR                        (1 << 4)
123 #define WRSR_TOUT                       (1 << 1)
124 #define WRSR_SFTW                       (1 << 0)
125
126 static void print_reset_cause(void)
127 {
128         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
129         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
130         u32 srsr;
131         char *dlm = "";
132
133         printf("Reset cause: ");
134
135         srsr = readl(&src_regs->srsr);
136         wrsr = readw(wdt_base + 4);
137
138         if (wrsr & WRSR_POR) {
139                 printf("%sPOR", dlm);
140                 dlm = " | ";
141         }
142         if (srsr & 0x00004) {
143                 printf("%sCSU", dlm);
144                 dlm = " | ";
145         }
146         if (srsr & 0x00008) {
147                 printf("%sIPP USER", dlm);
148                 dlm = " | ";
149         }
150         if (srsr & 0x00010) {
151                 if (wrsr & WRSR_SFTW) {
152                         printf("%sSOFT", dlm);
153                         dlm = " | ";
154                 }
155                 if (wrsr & WRSR_TOUT) {
156                         printf("%sWDOG", dlm);
157                         dlm = " | ";
158                 }
159         }
160         if (srsr & 0x00020) {
161                 printf("%sJTAG HIGH-Z", dlm);
162                 dlm = " | ";
163         }
164         if (srsr & 0x00040) {
165                 printf("%sJTAG SW", dlm);
166                 dlm = " | ";
167         }
168         if (srsr & 0x10000) {
169                 printf("%sWARM BOOT", dlm);
170                 dlm = " | ";
171         }
172         if (dlm[0] == '\0')
173                 printf("unknown");
174
175         printf("\n");
176 }
177
178 int read_cpu_temperature(void);
179 int check_cpu_temperature(int boot);
180
181 static void tx6qdl_print_cpuinfo(void)
182 {
183         u32 cpurev = get_cpu_rev();
184         char *cpu_str = "?";
185
186         switch ((cpurev >> 12) & 0xff) {
187         case MXC_CPU_MX6SL:
188                 cpu_str = "SL";
189                 break;
190         case MXC_CPU_MX6DL:
191                 cpu_str = "DL";
192                 break;
193         case MXC_CPU_MX6SOLO:
194                 cpu_str = "SOLO";
195                 break;
196         case MXC_CPU_MX6Q:
197                 cpu_str = "Q";
198                 break;
199         }
200
201         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
202                 cpu_str,
203                 (cpurev & 0x000F0) >> 4,
204                 (cpurev & 0x0000F) >> 0,
205                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
206
207         print_reset_cause();
208         check_cpu_temperature(1);
209 }
210
211 #define RN5T618_NOETIMSET       0x11
212 #define RN5T618_LDORTC1_SLOT    0x2a
213 #define RN5T618_DC1CTL          0x2c
214 #define RN5T618_DC1CTL2         0x2d
215 #define RN5T618_DC2CTL          0x2e
216 #define RN5T618_DC2CTL2         0x2f
217 #define RN5T618_DC3CTL          0x30
218 #define RN5T618_DC3CTL2         0x31
219 #define RN5T618_DC1DAC          0x36 /* CORE */
220 #define RN5T618_DC2DAC          0x37 /* SOC */
221 #define RN5T618_DC3DAC          0x38 /* DDR */
222 #define RN5T618_DC1DAC_SLP      0x3b
223 #define RN5T618_DC2DAC_SLP      0x3c
224 #define RN5T618_DC3DAC_SLP      0x3d
225 #define RN5T618_LDOEN1          0x44
226 #define RN5T618_LDODIS          0x46
227 #define RN5T618_LDOEN2          0x48
228 #define RN5T618_LDO3DAC         0x4e /* IO */
229 #define RN5T618_LDORTCDAC       0x56 /* VBACKUP */
230
231 #define VDD_RTC_VAL             mV_to_regval_rtc(3000 * 10)
232 #define VDD_HIGH_VAL            mV_to_regval3(3000 * 10)
233 #define VDD_HIGH_VAL_LP         mV_to_regval3(3000 * 10)
234 #define VDD_CORE_VAL            mV_to_regval(1425 * 10)
235 #define VDD_CORE_VAL_LP         mV_to_regval(900 * 10)
236 #define VDD_SOC_VAL             mV_to_regval(1425 * 10)
237 #define VDD_SOC_VAL_LP          mV_to_regval(900 * 10)
238 #define VDD_DDR_VAL             mV_to_regval(1500 * 10)
239 #define VDD_DDR_VAL_LP          mV_to_regval(1500 * 10)
240
241 /* calculate voltages in 10mV */
242 /* DCDC1-3 */
243 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 125)
244 #define regval_to_mV(v)         (((v) * 125 + 6000))
245
246 /* LDO1-2 */
247 #define mV_to_regval2(mV)       DIV_ROUND(((((mV) < 9000) ? 9000 : (mV)) - 9000), 250)
248 #define regval2_to_mV(v)        (((v) * 250 + 9000))
249
250 /* LDO3 */
251 #define mV_to_regval3(mV)       DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 250)
252 #define regval3_to_mV(v)        (((v) * 250 + 6000))
253
254 /* LDORTC */
255 #define mV_to_regval_rtc(mV)    DIV_ROUND(((((mV) < 17000) ? 17000 : (mV)) - 17000), 250)
256 #define regval_rtc_to_mV(v)     (((v) * 250 + 17000))
257
258 static struct rn5t618_regs {
259         u8 addr;
260         u8 val;
261         u8 mask;
262 } rn5t618_regs[] = {
263         { RN5T618_NOETIMSET, 0, },
264         { RN5T618_DC1DAC, VDD_CORE_VAL, },
265         { RN5T618_DC2DAC, VDD_SOC_VAL, },
266         { RN5T618_DC3DAC, VDD_DDR_VAL, },
267         { RN5T618_DC1DAC_SLP, VDD_CORE_VAL_LP, },
268         { RN5T618_DC2DAC_SLP, VDD_SOC_VAL_LP, },
269         { RN5T618_DC3DAC_SLP, VDD_DDR_VAL_LP, },
270         { RN5T618_LDOEN1, 0x01f, ~0x1f, },
271         { RN5T618_LDOEN2, 0x10, ~0x30, },
272         { RN5T618_LDODIS, 0x00, },
273         { RN5T618_LDO3DAC, VDD_HIGH_VAL, },
274         { RN5T618_LDORTCDAC, VDD_RTC_VAL, },
275         { RN5T618_LDORTC1_SLOT, 0x0f, ~0x3f, },
276 };
277
278 static int tx6_rn5t618_setup_regs(struct rn5t618_regs *r, size_t count)
279 {
280         int ret;
281         int i;
282
283         for (i = 0; i < count; i++, r++) {
284 #ifdef DEBUG
285                 unsigned char value;
286
287                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
288                 if ((value & ~r->mask) != r->val) {
289                         printf("Changing PMIC reg %02x from %02x to %02x\n",
290                                 r->addr, value, r->val);
291                 }
292                 if (ret) {
293                         printf("%s: failed to read PMIC register %02x: %d\n",
294                                 __func__, r->addr, ret);
295                         return ret;
296                 }
297 #endif
298                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
299                                 r->addr, 1, &r->val, 1);
300                 if (ret) {
301                         printf("%s: failed to write PMIC register %02x: %d\n",
302                                 __func__, r->addr, ret);
303                         return ret;
304                 }
305 #ifdef DEBUG
306                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
307                 printf("PMIC reg %02x is %02x\n", r->addr, value);
308 #endif
309         }
310         return 0;
311 }
312
313 static int setup_pmic_voltages(void)
314 {
315         int ret;
316         unsigned char value;
317
318         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
319         if (ret != 0) {
320                 printf("Failed to initialize I2C\n");
321                 return ret;
322         }
323
324         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
325         if (ret) {
326                 printf("%s: i2c_read error: %d\n", __func__, ret);
327                 return ret;
328         }
329
330         ret = tx6_rn5t618_setup_regs(rn5t618_regs, ARRAY_SIZE(rn5t618_regs));
331         if (ret)
332                 return ret;
333
334         printf("VDDCORE set to %umV\n",
335                 DIV_ROUND(regval_to_mV(VDD_CORE_VAL), 10));
336         printf("VDDSOC  set to %umV\n",
337                 DIV_ROUND(regval_to_mV(VDD_SOC_VAL), 10));
338
339         return ret;
340 }
341
342 int board_early_init_f(void)
343 {
344         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
345         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
346
347         return 0;
348 }
349
350 int board_init(void)
351 {
352         int ret;
353
354         /* Address of boot parameters */
355         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
356         gd->bd->bi_arch_number = -1;
357
358         if (ctrlc()) {
359                 printf("CTRL-C detected; Skipping PMIC setup\n");
360                 return 1;
361         }
362
363         ret = setup_pmic_voltages();
364         if (ret) {
365                 printf("Failed to setup PMIC voltages\n");
366                 hang();
367         }
368         return 0;
369 }
370
371 int dram_init(void)
372 {
373         /* dram_init must store complete ramsize in gd->ram_size */
374         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
375                                 PHYS_SDRAM_1_SIZE);
376         return 0;
377 }
378
379 void dram_init_banksize(void)
380 {
381         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
382         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
383                         PHYS_SDRAM_1_SIZE);
384 #if CONFIG_NR_DRAM_BANKS > 1
385         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
386         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
387                         PHYS_SDRAM_2_SIZE);
388 #endif
389 }
390
391 #ifdef  CONFIG_CMD_MMC
392 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
393         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
394         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
395
396 static const iomux_v3_cfg_t mmc0_pads[] = {
397         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
398         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
399         MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
400         MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
401         MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
402         MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
403         /* SD1 CD */
404         MX6_PAD_SD3_CMD__GPIO_7_2,
405 };
406
407 static const iomux_v3_cfg_t mmc1_pads[] = {
408         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
409         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
410         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
411         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
412         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
413         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
414         /* SD2 CD */
415         MX6_PAD_SD3_CLK__GPIO_7_3,
416 };
417
418 static const iomux_v3_cfg_t mmc3_pads[] = {
419         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
420         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
421         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
422         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
423         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
424         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
425         /* eMMC RESET */
426         MX6_PAD_NANDF_ALE__USDHC4_RST,
427 };
428
429 static struct tx6_esdhc_cfg {
430         const iomux_v3_cfg_t *pads;
431         int num_pads;
432         enum mxc_clock clkid;
433         struct fsl_esdhc_cfg cfg;
434         int cd_gpio;
435 } tx6qdl_esdhc_cfg[] = {
436         {
437                 .pads = mmc3_pads,
438                 .num_pads = ARRAY_SIZE(mmc3_pads),
439                 .clkid = MXC_ESDHC4_CLK,
440                 .cfg = {
441                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
442                         .max_bus_width = 4,
443                 },
444                 .cd_gpio = -EINVAL,
445         },
446         {
447                 .pads = mmc0_pads,
448                 .num_pads = ARRAY_SIZE(mmc0_pads),
449                 .clkid = MXC_ESDHC_CLK,
450                 .cfg = {
451                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
452                         .max_bus_width = 4,
453                 },
454                 .cd_gpio = IMX_GPIO_NR(7, 2),
455         },
456         {
457                 .pads = mmc1_pads,
458                 .num_pads = ARRAY_SIZE(mmc1_pads),
459                 .clkid = MXC_ESDHC2_CLK,
460                 .cfg = {
461                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
462                         .max_bus_width = 4,
463                 },
464                 .cd_gpio = IMX_GPIO_NR(7, 3),
465         },
466 };
467
468 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
469 {
470         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
471 }
472
473 int board_mmc_getcd(struct mmc *mmc)
474 {
475         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
476
477         if (cfg->cd_gpio < 0)
478                 return 1;
479
480         debug("SD card %d is %spresent\n",
481                 cfg - tx6qdl_esdhc_cfg,
482                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
483         return !gpio_get_value(cfg->cd_gpio);
484 }
485
486 int board_mmc_init(bd_t *bis)
487 {
488         int i;
489
490         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
491                 struct mmc *mmc;
492                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
493                 int ret;
494
495                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
496                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
497
498                 if (cfg->cd_gpio >= 0) {
499                         ret = gpio_request_one(cfg->cd_gpio,
500                                         GPIOF_INPUT, "MMC CD");
501                         if (ret) {
502                                 printf("Error %d requesting GPIO%d_%d\n",
503                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
504                                 continue;
505                         }
506                 }
507
508                 debug("%s: Initializing MMC slot %d\n", __func__, i);
509                 fsl_esdhc_initialize(bis, &cfg->cfg);
510
511                 mmc = find_mmc_device(i);
512                 if (mmc == NULL)
513                         continue;
514                 if (board_mmc_getcd(mmc))
515                         mmc_init(mmc);
516         }
517         return 0;
518 }
519 #endif /* CONFIG_CMD_MMC */
520
521 #ifdef CONFIG_FEC_MXC
522
523 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
524                         PAD_CTL_SRE_FAST)
525 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
526 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
527
528 #ifndef ETH_ALEN
529 #define ETH_ALEN 6
530 #endif
531
532 int board_eth_init(bd_t *bis)
533 {
534         int ret;
535
536         /* delay at least 21ms for the PHY internal POR signal to deassert */
537         udelay(22000);
538
539         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
540
541         /* Deassert RESET to the external phy */
542         gpio_set_value(TX6_FEC_RST_GPIO, 1);
543
544         ret = cpu_eth_init(bis);
545         if (ret)
546                 printf("cpu_eth_init() failed: %d\n", ret);
547
548         return ret;
549 }
550 #endif /* CONFIG_FEC_MXC */
551
552 enum {
553         LED_STATE_INIT = -1,
554         LED_STATE_OFF,
555         LED_STATE_ON,
556 };
557
558 static inline int calc_blink_rate(int tmp)
559 {
560         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
561                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
562                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
563 }
564
565 void show_activity(int arg)
566 {
567         static int led_state = LED_STATE_INIT;
568         static int blink_rate;
569         static ulong last;
570
571         if (led_state == LED_STATE_INIT) {
572                 last = get_timer(0);
573                 gpio_set_value(TX6_LED_GPIO, 1);
574                 led_state = LED_STATE_ON;
575                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
576         } else {
577                 if (get_timer(last) > blink_rate) {
578                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
579                         last = get_timer_masked();
580                         if (led_state == LED_STATE_ON) {
581                                 gpio_set_value(TX6_LED_GPIO, 0);
582                         } else {
583                                 gpio_set_value(TX6_LED_GPIO, 1);
584                         }
585                         led_state = 1 - led_state;
586                 }
587         }
588 }
589
590 static const iomux_v3_cfg_t stk5_pads[] = {
591         /* SW controlled LED on STK5 baseboard */
592         MX6_PAD_EIM_A18__GPIO_2_20,
593
594         /* LCD data pins */
595         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
596         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
597         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
598         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
599         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
600         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
601         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
602         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
603         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
604         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
605         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
606         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
607         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
608         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
609         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
610         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
611         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
612         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
613         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
614         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
615         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
616         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
617         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
618         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
619         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
620         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
621         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
622         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
623
624         /* I2C bus on DIMM pins 40/41 */
625         MX6_PAD_GPIO_6__I2C3_SDA,
626         MX6_PAD_GPIO_3__I2C3_SCL,
627
628         /* TSC200x PEN IRQ */
629         MX6_PAD_EIM_D26__GPIO_3_26,
630
631         /* EDT-FT5x06 Polytouch panel */
632         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
633         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
634         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
635
636         /* USBH1 */
637         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
638         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
639         /* USBOTG */
640         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
641         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
642         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
643 };
644
645 static const struct gpio stk5_gpios[] = {
646         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
647
648         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
649         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
650         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
651         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
652         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
653 };
654
655 #ifdef CONFIG_LCD
656 static u16 tx6_cmap[256];
657 vidinfo_t panel_info = {
658         /* set to max. size supported by SoC */
659         .vl_col = 1920,
660         .vl_row = 1080,
661
662         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
663         .cmap = tx6_cmap,
664 };
665
666 static struct fb_videomode tx6_fb_modes[] = {
667 #ifndef CONFIG_SYS_LVDS_IF
668         {
669                 /* Standard VGA timing */
670                 .name           = "VGA",
671                 .refresh        = 60,
672                 .xres           = 640,
673                 .yres           = 480,
674                 .pixclock       = KHZ2PICOS(25175),
675                 .left_margin    = 48,
676                 .hsync_len      = 96,
677                 .right_margin   = 16,
678                 .upper_margin   = 31,
679                 .vsync_len      = 2,
680                 .lower_margin   = 12,
681                 .sync           = FB_SYNC_CLK_LAT_FALL,
682         },
683         {
684                 /* Emerging ETV570 640 x 480 display. Syncs low active,
685                  * DE high active, 115.2 mm x 86.4 mm display area
686                  * VGA compatible timing
687                  */
688                 .name           = "ETV570",
689                 .refresh        = 60,
690                 .xres           = 640,
691                 .yres           = 480,
692                 .pixclock       = KHZ2PICOS(25175),
693                 .left_margin    = 114,
694                 .hsync_len      = 30,
695                 .right_margin   = 16,
696                 .upper_margin   = 32,
697                 .vsync_len      = 3,
698                 .lower_margin   = 10,
699                 .sync           = FB_SYNC_CLK_LAT_FALL,
700         },
701         {
702                 /* Emerging ET0350G0DH6 320 x 240 display.
703                  * 70.08 mm x 52.56 mm display area.
704                  */
705                 .name           = "ET0350",
706                 .refresh        = 60,
707                 .xres           = 320,
708                 .yres           = 240,
709                 .pixclock       = KHZ2PICOS(6500),
710                 .left_margin    = 68 - 34,
711                 .hsync_len      = 34,
712                 .right_margin   = 20,
713                 .upper_margin   = 18 - 3,
714                 .vsync_len      = 3,
715                 .lower_margin   = 4,
716                 .sync           = FB_SYNC_CLK_LAT_FALL,
717         },
718         {
719                 /* Emerging ET0430G0DH6 480 x 272 display.
720                  * 95.04 mm x 53.856 mm display area.
721                  */
722                 .name           = "ET0430",
723                 .refresh        = 60,
724                 .xres           = 480,
725                 .yres           = 272,
726                 .pixclock       = KHZ2PICOS(9000),
727                 .left_margin    = 2,
728                 .hsync_len      = 41,
729                 .right_margin   = 2,
730                 .upper_margin   = 2,
731                 .vsync_len      = 10,
732                 .lower_margin   = 2,
733                 .sync           = FB_SYNC_CLK_LAT_FALL,
734         },
735         {
736                 /* Emerging ET0500G0DH6 800 x 480 display.
737                  * 109.6 mm x 66.4 mm display area.
738                  */
739                 .name           = "ET0500",
740                 .refresh        = 60,
741                 .xres           = 800,
742                 .yres           = 480,
743                 .pixclock       = KHZ2PICOS(33260),
744                 .left_margin    = 216 - 128,
745                 .hsync_len      = 128,
746                 .right_margin   = 1056 - 800 - 216,
747                 .upper_margin   = 35 - 2,
748                 .vsync_len      = 2,
749                 .lower_margin   = 525 - 480 - 35,
750                 .sync           = FB_SYNC_CLK_LAT_FALL,
751         },
752         {
753                 /* Emerging ETQ570G0DH6 320 x 240 display.
754                  * 115.2 mm x 86.4 mm display area.
755                  */
756                 .name           = "ETQ570",
757                 .refresh        = 60,
758                 .xres           = 320,
759                 .yres           = 240,
760                 .pixclock       = KHZ2PICOS(6400),
761                 .left_margin    = 38,
762                 .hsync_len      = 30,
763                 .right_margin   = 30,
764                 .upper_margin   = 16, /* 15 according to datasheet */
765                 .vsync_len      = 3, /* TVP -> 1>x>5 */
766                 .lower_margin   = 4, /* 4.5 according to datasheet */
767                 .sync           = FB_SYNC_CLK_LAT_FALL,
768         },
769         {
770                 /* Emerging ET0700G0DH6 800 x 480 display.
771                  * 152.4 mm x 91.44 mm display area.
772                  */
773                 .name           = "ET0700",
774                 .refresh        = 60,
775                 .xres           = 800,
776                 .yres           = 480,
777                 .pixclock       = KHZ2PICOS(33260),
778                 .left_margin    = 216 - 128,
779                 .hsync_len      = 128,
780                 .right_margin   = 1056 - 800 - 216,
781                 .upper_margin   = 35 - 2,
782                 .vsync_len      = 2,
783                 .lower_margin   = 525 - 480 - 35,
784                 .sync           = FB_SYNC_CLK_LAT_FALL,
785         },
786         {
787                 /* Emerging ET070001DM6 800 x 480 display.
788                  * 152.4 mm x 91.44 mm display area.
789                  */
790                 .name           = "ET070001DM6",
791                 .refresh        = 60,
792                 .xres           = 800,
793                 .yres           = 480,
794                 .pixclock       = KHZ2PICOS(33260),
795                 .left_margin    = 216 - 128,
796                 .hsync_len      = 128,
797                 .right_margin   = 1056 - 800 - 216,
798                 .upper_margin   = 35 - 2,
799                 .vsync_len      = 2,
800                 .lower_margin   = 525 - 480 - 35,
801                 .sync           = 0,
802         },
803 #else
804         {
805                 /* HannStar HSD100PXN1
806                  * 202.7m mm x 152.06 mm display area.
807                  */
808                 .name           = "HSD100PXN1",
809                 .refresh        = 60,
810                 .xres           = 1024,
811                 .yres           = 768,
812                 .pixclock       = KHZ2PICOS(65000),
813                 .left_margin    = 0,
814                 .hsync_len      = 0,
815                 .right_margin   = 320,
816                 .upper_margin   = 0,
817                 .vsync_len      = 0,
818                 .lower_margin   = 38,
819                 .sync           = FB_SYNC_CLK_LAT_FALL,
820         },
821 #endif
822         {
823                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
824                 .refresh        = 60,
825                 .left_margin    = 48,
826                 .hsync_len      = 96,
827                 .right_margin   = 16,
828                 .upper_margin   = 31,
829                 .vsync_len      = 2,
830                 .lower_margin   = 12,
831                 .sync           = FB_SYNC_CLK_LAT_FALL,
832         },
833 };
834
835 static int lcd_enabled = 1;
836 static int lcd_bl_polarity;
837
838 static int lcd_backlight_polarity(void)
839 {
840         return lcd_bl_polarity;
841 }
842
843 void lcd_enable(void)
844 {
845         /* HACK ALERT:
846          * global variable from common/lcd.c
847          * Set to 0 here to prevent messages from going to LCD
848          * rather than serial console
849          */
850         lcd_is_enabled = 0;
851
852         if (lcd_enabled) {
853                 karo_load_splashimage(1);
854
855                 debug("Switching LCD on\n");
856                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
857                 udelay(100);
858                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
859                 udelay(300000);
860                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, lcd_backlight_polarity());
861         }
862 }
863
864 void lcd_disable(void)
865 {
866         if (lcd_enabled) {
867                 printf("Disabling LCD\n");
868                 ipuv3_fb_shutdown();
869         }
870 }
871
872 void lcd_panel_disable(void)
873 {
874         if (lcd_enabled) {
875                 debug("Switching LCD off\n");
876                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, !lcd_backlight_polarity());
877                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
878                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
879         }
880 }
881
882 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
883         /* LCD RESET */
884         MX6_PAD_EIM_D29__GPIO_3_29,
885         /* LCD POWER_ENABLE */
886         MX6_PAD_EIM_EB3__GPIO_2_31,
887         /* LCD Backlight (PWM) */
888         MX6_PAD_GPIO_1__GPIO_1_1,
889
890         /* Display */
891         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
892         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
893         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
894         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
895         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
896         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
897         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
898         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
899         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
900         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
901         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
902         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
903         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
904         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
905         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
906         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
907         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
908         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
909         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
910         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
911         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
912         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
913         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
914         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
915         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
916         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
917         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
918         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
919 };
920
921 static const struct gpio stk5_lcd_gpios[] = {
922         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
923         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
924         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
925 };
926
927 void lcd_ctrl_init(void *lcdbase)
928 {
929         int color_depth = 24;
930         const char *video_mode = karo_get_vmode(getenv("video_mode"));
931         const char *vm;
932         unsigned long val;
933         int refresh = 60;
934         struct fb_videomode *p = &tx6_fb_modes[0];
935         struct fb_videomode fb_mode;
936         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
937         int pix_fmt;
938         int lcd_bus_width;
939         unsigned long di_clk_rate = 65000000;
940
941         if (!lcd_enabled) {
942                 debug("LCD disabled\n");
943                 return;
944         }
945
946         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
947                 debug("Disabling LCD\n");
948                 lcd_enabled = 0;
949                 setenv("splashimage", NULL);
950                 return;
951         }
952
953         karo_fdt_move_fdt();
954         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
955
956         if (video_mode == NULL) {
957                 debug("Disabling LCD\n");
958                 lcd_enabled = 0;
959                 return;
960         }
961         vm = video_mode;
962         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
963                 p = &fb_mode;
964                 debug("Using video mode from FDT\n");
965                 vm += strlen(vm);
966                 if (fb_mode.xres > panel_info.vl_col ||
967                         fb_mode.yres > panel_info.vl_row) {
968                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
969                                 fb_mode.xres, fb_mode.yres,
970                                 panel_info.vl_col, panel_info.vl_row);
971                         lcd_enabled = 0;
972                         return;
973                 }
974         }
975         if (p->name != NULL)
976                 debug("Trying compiled-in video modes\n");
977         while (p->name != NULL) {
978                 if (strcmp(p->name, vm) == 0) {
979                         debug("Using video mode: '%s'\n", p->name);
980                         vm += strlen(vm);
981                         break;
982                 }
983                 p++;
984         }
985         if (*vm != '\0')
986                 debug("Trying to decode video_mode: '%s'\n", vm);
987         while (*vm != '\0') {
988                 if (*vm >= '0' && *vm <= '9') {
989                         char *end;
990
991                         val = simple_strtoul(vm, &end, 0);
992                         if (end > vm) {
993                                 if (!xres_set) {
994                                         if (val > panel_info.vl_col)
995                                                 val = panel_info.vl_col;
996                                         p->xres = val;
997                                         panel_info.vl_col = val;
998                                         xres_set = 1;
999                                 } else if (!yres_set) {
1000                                         if (val > panel_info.vl_row)
1001                                                 val = panel_info.vl_row;
1002                                         p->yres = val;
1003                                         panel_info.vl_row = val;
1004                                         yres_set = 1;
1005                                 } else if (!bpp_set) {
1006                                         switch (val) {
1007                                         case 32:
1008                                         case 24:
1009                                                 if (is_lvds())
1010                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1011                                                 /* fallthru */
1012                                         case 16:
1013                                         case 8:
1014                                                 color_depth = val;
1015                                                 break;
1016
1017                                         case 18:
1018                                                 if (is_lvds()) {
1019                                                         color_depth = val;
1020                                                         break;
1021                                                 }
1022                                                 /* fallthru */
1023                                         default:
1024                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1025                                                         end - vm, vm, color_depth);
1026                                         }
1027                                         bpp_set = 1;
1028                                 } else if (!refresh_set) {
1029                                         refresh = val;
1030                                         refresh_set = 1;
1031                                 }
1032                         }
1033                         vm = end;
1034                 }
1035                 switch (*vm) {
1036                 case '@':
1037                         bpp_set = 1;
1038                         /* fallthru */
1039                 case '-':
1040                         yres_set = 1;
1041                         /* fallthru */
1042                 case 'x':
1043                         xres_set = 1;
1044                         /* fallthru */
1045                 case 'M':
1046                 case 'R':
1047                         vm++;
1048                         break;
1049
1050                 default:
1051                         if (*vm != '\0')
1052                                 vm++;
1053                 }
1054         }
1055         if (p->xres == 0 || p->yres == 0) {
1056                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1057                 lcd_enabled = 0;
1058                 printf("Supported video modes are:");
1059                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1060                         printf(" %s", p->name);
1061                 }
1062                 printf("\n");
1063                 return;
1064         }
1065         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1066                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1067                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1068                 lcd_enabled = 0;
1069                 return;
1070         }
1071         panel_info.vl_col = p->xres;
1072         panel_info.vl_row = p->yres;
1073
1074         switch (color_depth) {
1075         case 8:
1076                 panel_info.vl_bpix = LCD_COLOR8;
1077                 break;
1078         case 16:
1079                 panel_info.vl_bpix = LCD_COLOR16;
1080                 break;
1081         default:
1082                 panel_info.vl_bpix = LCD_COLOR24;
1083         }
1084
1085         p->pixclock = KHZ2PICOS(refresh *
1086                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1087                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1088                                 1000);
1089         debug("Pixel clock set to %lu.%03lu MHz\n",
1090                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1091
1092         if (p != &fb_mode) {
1093                 int ret;
1094
1095                 debug("Creating new display-timing node from '%s'\n",
1096                         video_mode);
1097                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1098                 if (ret)
1099                         printf("Failed to create new display-timing node from '%s': %d\n",
1100                                 video_mode, ret);
1101         }
1102
1103         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1104         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1105                                         ARRAY_SIZE(stk5_lcd_pads));
1106
1107         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1108         switch (lcd_bus_width) {
1109         case 24:
1110                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1111                 break;
1112
1113         case 18:
1114                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1115                 break;
1116
1117         case 16:
1118                 if (!is_lvds()) {
1119                         pix_fmt = IPU_PIX_FMT_RGB565;
1120                         break;
1121                 }
1122                 /* fallthru */
1123         default:
1124                 lcd_enabled = 0;
1125                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1126                         lcd_bus_width);
1127                 return;
1128         }
1129         if (is_lvds()) {
1130                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1131                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1132                 uint32_t gpr2;
1133
1134                 if (lvds_chan_mask == 0) {
1135                         printf("No LVDS channel active\n");
1136                         lcd_enabled = 0;
1137                         return;
1138                 }
1139
1140                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1141                 if (lcd_bus_width == 24)
1142                         gpr2 |= (1 << 5) | (1 << 7);
1143                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1144                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1145                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1146                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1147         }
1148         if (karo_load_splashimage(0) == 0) {
1149                 int ret;
1150
1151                 debug("Initializing LCD controller\n");
1152                 ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
1153                 if (ret) {
1154                         printf("Failed to initialize FB driver: %d\n", ret);
1155                         lcd_enabled = 0;
1156                 }
1157         } else {
1158                 debug("Skipping initialization of LCD controller\n");
1159         }
1160 }
1161 #else
1162 #define lcd_enabled 0
1163 #endif /* CONFIG_LCD */
1164
1165 static void stk5_board_init(void)
1166 {
1167         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1168         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1169 }
1170
1171 static void stk5v3_board_init(void)
1172 {
1173         stk5_board_init();
1174 }
1175
1176 static void stk5v5_board_init(void)
1177 {
1178         stk5_board_init();
1179
1180         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1181                         "Flexcan Transceiver");
1182         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1183 }
1184
1185 static void tx6qdl_set_cpu_clock(void)
1186 {
1187         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1188
1189         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1190                 return;
1191
1192         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1193                 return;
1194
1195         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1196                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1197                 printf("CPU clock set to %lu.%03lu MHz\n",
1198                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1199         } else {
1200                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1201         }
1202 }
1203
1204 static void tx6_init_mac(void)
1205 {
1206         u8 mac[ETH_ALEN];
1207
1208         imx_get_mac_from_fuse(-1, mac);
1209         if (!is_valid_ether_addr(mac)) {
1210                 printf("No valid MAC address programmed\n");
1211                 return;
1212         }
1213
1214         printf("MAC addr from fuse: %pM\n", mac);
1215         eth_setenv_enetaddr("ethaddr", mac);
1216 }
1217
1218 int board_late_init(void)
1219 {
1220         int ret = 0;
1221         const char *baseboard;
1222
1223         tx6qdl_set_cpu_clock();
1224         karo_fdt_move_fdt();
1225
1226         baseboard = getenv("baseboard");
1227         if (!baseboard)
1228                 goto exit;
1229
1230         printf("Baseboard: %s\n", baseboard);
1231
1232         if (strncmp(baseboard, "stk5", 4) == 0) {
1233                 if ((strlen(baseboard) == 4) ||
1234                         strcmp(baseboard, "stk5-v3") == 0) {
1235                         stk5v3_board_init();
1236                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1237                         const char *otg_mode = getenv("otg_mode");
1238
1239                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1240                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1241                                         otg_mode, baseboard);
1242                                 setenv("otg_mode", "none");
1243                         }
1244                         stk5v5_board_init();
1245                 } else {
1246                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1247                                 baseboard + 4);
1248                 }
1249         } else {
1250                 printf("WARNING: Unsupported baseboard: '%s'\n",
1251                         baseboard);
1252                 ret = -EINVAL;
1253         }
1254
1255 exit:
1256         tx6_init_mac();
1257
1258         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1259         clear_ctrlc();
1260         return ret;
1261 }
1262
1263 int checkboard(void)
1264 {
1265         u32 cpurev = get_cpu_rev();
1266         int cpu_variant = (cpurev >> 12) & 0xff;
1267
1268         tx6qdl_print_cpuinfo();
1269
1270         printf("Board: Ka-Ro TX6%c-%d%d2%d\n",
1271                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1272                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1273                 is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64);
1274
1275         return 0;
1276 }
1277
1278 #ifdef CONFIG_SERIAL_TAG
1279 void get_board_serial(struct tag_serialnr *serialnr)
1280 {
1281         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1282         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1283
1284         serialnr->low = readl(&fuse->cfg0);
1285         serialnr->high = readl(&fuse->cfg1);
1286 }
1287 #endif
1288
1289 #ifdef CONFIG_OF_BOARD_SETUP
1290 static const char *tx6_touchpanels[] = {
1291         "ti,tsc2007",
1292         "edt,edt-ft5x06",
1293         "eeti,egalax_ts",
1294 };
1295
1296 void ft_board_setup(void *blob, bd_t *bd)
1297 {
1298         const char *baseboard = getenv("baseboard");
1299         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1300         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1301         int ret;
1302
1303         ret = fdt_increase_size(blob, 4096);
1304         if (ret)
1305                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1306
1307         if (stk5_v5)
1308                 karo_fdt_enable_node(blob, "stk5led", 0);
1309
1310         fdt_fixup_ethernet(blob);
1311
1312         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1313                                 ARRAY_SIZE(tx6_touchpanels));
1314         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1315         karo_fdt_fixup_flexcan(blob, stk5_v5);
1316
1317         karo_fdt_update_fb_mode(blob, video_mode);
1318 }
1319 #endif /* CONFIG_OF_BOARD_SETUP */