090ade17a589c14f367d28bb781dc526c98d32f4
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012-2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <common.h>
18 #include <errno.h>
19 #include <libfdt.h>
20 #include <fdt_support.h>
21 #include <lcd.h>
22 #include <netdev.h>
23 #include <mmc.h>
24 #include <fsl_esdhc.h>
25 #include <video_fb.h>
26 #include <ipu.h>
27 #include <mxcfb.h>
28 #include <i2c.h>
29 #include <linux/fb.h>
30 #include <asm/io.h>
31 #include <asm/gpio.h>
32 #include <asm/arch/mx6-pins.h>
33 #include <asm/arch/clock.h>
34 #include <asm/arch/hab.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
38
39 #include "../common/karo.h"
40 #include "pmic.h"
41
42 #define __data __attribute__((section(".data")))
43
44 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
45 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
46 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
47 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
48
49 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
50 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
51 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
52
53 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
54 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
55 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
56
57 #ifdef CONFIG_MX6_TEMPERATURE_MIN
58 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
59 #else
60 #define TEMPERATURE_MIN                 (-40)
61 #endif
62 #ifdef CONFIG_MX6_TEMPERATURE_HOT
63 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
64 #else
65 #define TEMPERATURE_HOT                 80
66 #endif
67
68 DECLARE_GLOBAL_DATA_PTR;
69
70 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
71
72 enum {
73         MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
74 };
75
76 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
77 #ifdef CONFIG_SECURE_BOOT
78 char __csf_data[0] __attribute__((section(".__csf_data")));
79 #endif
80
81 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
82         /* RESET_OUT */
83         MX6_PAD_GPIO_17__GPIO7_IO12,
84
85         /* UART pads */
86 #if CONFIG_MXC_UART_BASE == UART1_BASE
87         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
88         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
89         MX6_PAD_SD3_DAT1__UART1_RTS_B,
90         MX6_PAD_SD3_DAT0__UART1_CTS_B,
91 #endif
92 #if CONFIG_MXC_UART_BASE == UART2_BASE
93         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
94         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
95         MX6_PAD_SD4_DAT5__UART2_RTS_B,
96         MX6_PAD_SD4_DAT6__UART2_CTS_B,
97 #endif
98 #if CONFIG_MXC_UART_BASE == UART3_BASE
99         MX6_PAD_EIM_D24__UART3_TX_DATA,
100         MX6_PAD_EIM_D25__UART3_RX_DATA,
101         MX6_PAD_SD3_RST__UART3_RTS_B,
102         MX6_PAD_SD3_DAT3__UART3_CTS_B,
103 #endif
104         /* internal I2C */
105         MX6_PAD_EIM_D28__I2C1_SDA,
106         MX6_PAD_EIM_D21__I2C1_SCL,
107
108         /* FEC PHY GPIO functions */
109         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
110         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
111         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
112 };
113
114 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
115         /* FEC functions */
116         MX6_PAD_ENET_MDC__ENET_MDC,
117         MX6_PAD_ENET_MDIO__ENET_MDIO,
118         MX6_PAD_GPIO_16__ENET_REF_CLK,
119         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
120         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
121         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
122         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
123         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
124         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
125         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
126 };
127
128 #define TX6_I2C_GPIO_PAD_CTRL   (PAD_CTL_PUS_22K_UP |   \
129                                 PAD_CTL_SPEED_MED |     \
130                                 PAD_CTL_DSE_34ohm |     \
131                                 PAD_CTL_SRE_FAST)
132
133 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
134         /* internal I2C */
135         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
136         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
137 };
138
139 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
140         /* internal I2C */
141         MX6_PAD_EIM_D28__I2C1_SDA,
142         MX6_PAD_EIM_D21__I2C1_SCL,
143 };
144
145 static const struct gpio const tx6qdl_gpios[] = {
146         /* These two entries are used to forcefully reinitialize the I2C bus */
147         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
148         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
149
150         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
151         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
152         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
153         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
154 };
155
156 static int pmic_addr __data;
157
158 #if defined(CONFIG_SOC_MX6Q)
159 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
160 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
161 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
162 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
163 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
164 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
165 #define I2C1_SEL_INPUT_VAL                      0
166 #endif
167 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
168 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
169 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
170 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
171 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
172 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
173 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
174 #define I2C1_SEL_INPUT_VAL                      1
175 #endif
176
177 #define GPIO_DR 0
178 #define GPIO_DIR 4
179 #define GPIO_PSR 8
180
181 static void tx6_i2c_recover(void)
182 {
183         int i;
184         int bad = 0;
185 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
186 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
187
188         if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
189                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
190                 return;
191
192         debug("Clearing I2C bus\n");
193         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
194                 printf("I2C SCL stuck LOW\n");
195                 bad++;
196
197                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
198                         GPIO3_BASE_ADDR + GPIO_DR);
199                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
200                         GPIO3_BASE_ADDR + GPIO_DIR);
201         }
202         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
203                 printf("I2C SDA stuck LOW\n");
204                 bad++;
205
206                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
207                         GPIO3_BASE_ADDR + GPIO_DIR);
208                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
209                         GPIO3_BASE_ADDR + GPIO_DR);
210                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
211                         GPIO3_BASE_ADDR + GPIO_DIR);
212
213                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
214                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
215                 udelay(10);
216
217                 for (i = 0; i < 18; i++) {
218                         u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
219
220                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
221                         writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
222                         udelay(10);
223                         if (reg & SCL_BIT &&
224                                 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
225                                 break;
226                 }
227         }
228         if (bad) {
229                 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
230
231                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
232                         printf("I2C bus recovery succeeded\n");
233                 } else {
234                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
235                                 SCL_BIT | SDA_BIT);
236                 }
237         }
238         debug("Setting up I2C Pads\n");
239         imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
240                                         ARRAY_SIZE(tx6_i2c_pads));
241 }
242
243 /* placed in section '.data' to prevent overwriting relocation info
244  * overlayed with bss
245  */
246 static u32 wrsr __attribute__((section(".data")));
247
248 #define WRSR_POR                        (1 << 4)
249 #define WRSR_TOUT                       (1 << 1)
250 #define WRSR_SFTW                       (1 << 0)
251
252 static void print_reset_cause(void)
253 {
254         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
255         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
256         u32 srsr;
257         char *dlm = "";
258
259         printf("Reset cause: ");
260
261         srsr = readl(&src_regs->srsr);
262         wrsr = readw(wdt_base + 4);
263
264         if (wrsr & WRSR_POR) {
265                 printf("%sPOR", dlm);
266                 dlm = " | ";
267         }
268         if (srsr & 0x00004) {
269                 printf("%sCSU", dlm);
270                 dlm = " | ";
271         }
272         if (srsr & 0x00008) {
273                 printf("%sIPP USER", dlm);
274                 dlm = " | ";
275         }
276         if (srsr & 0x00010) {
277                 if (wrsr & WRSR_SFTW) {
278                         printf("%sSOFT", dlm);
279                         dlm = " | ";
280                 }
281                 if (wrsr & WRSR_TOUT) {
282                         printf("%sWDOG", dlm);
283                         dlm = " | ";
284                 }
285         }
286         if (srsr & 0x00020) {
287                 printf("%sJTAG HIGH-Z", dlm);
288                 dlm = " | ";
289         }
290         if (srsr & 0x00040) {
291                 printf("%sJTAG SW", dlm);
292                 dlm = " | ";
293         }
294         if (srsr & 0x10000) {
295                 printf("%sWARM BOOT", dlm);
296                 dlm = " | ";
297         }
298         if (dlm[0] == '\0')
299                 printf("unknown");
300
301         printf("\n");
302 }
303
304 static const char __data *tx6_mod_suffix;
305
306 int checkboard(void)
307 {
308         u32 cpurev = get_cpu_rev();
309         char *cpu_str = "?";
310
311         switch ((cpurev >> 12) & 0xff) {
312         case MXC_CPU_MX6SL:
313                 cpu_str = "SL";
314                 tx6_mod_suffix = "?";
315                 break;
316         case MXC_CPU_MX6DL:
317                 cpu_str = "DL";
318                 tx6_mod_suffix = "U";
319                 break;
320         case MXC_CPU_MX6SOLO:
321                 cpu_str = "SOLO";
322                 tx6_mod_suffix = "S";
323                 break;
324         case MXC_CPU_MX6Q:
325                 cpu_str = "Q";
326                 tx6_mod_suffix = "Q";
327                 break;
328         }
329
330         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
331                 cpu_str,
332                 (cpurev & 0x000F0) >> 4,
333                 (cpurev & 0x0000F) >> 0,
334                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
335
336         print_reset_cause();
337 #ifdef CONFIG_MX6_TEMPERATURE_HOT
338         check_cpu_temperature(1);
339 #endif
340         tx6_i2c_recover();
341         return 0;
342 }
343
344 int board_early_init_f(void)
345 {
346         debug("%s@%d: \n", __func__, __LINE__);
347
348         return 0;
349 }
350
351 #ifndef CONFIG_MX6_TEMPERATURE_HOT
352 static bool tx6_temp_check_enabled = true;
353 #else
354 #define tx6_temp_check_enabled  0
355 #endif
356
357 #ifdef CONFIG_TX6_NAND
358 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
359 #else
360 #ifdef CONFIG_MMC_BOOT_SIZE
361 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
362 #else
363 #define TX6_FLASH_SZ    2
364 #endif
365 #endif /* CONFIG_TX6_NAND */
366
367 #define TX6_DDR_SZ      (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
368
369 static char tx6_mem_table[] = {
370         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
371         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
372         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
373         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
374         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
375         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
376         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
377         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
378         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
379         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
380         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
381         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
382 };
383
384 static struct {
385         uchar addr;
386         uchar rev;
387 } tx6_mod_revs[] = {
388         { 0x3c, 1, },
389         { 0x32, 2, },
390         { 0x33, 3, },
391 };
392
393 static inline char tx6_mem_suffix(void)
394 {
395         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
396
397         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
398                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
399
400         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
401                 return '?';
402
403         return tx6_mem_table[mem_idx];
404 };
405
406 static int tx6_get_mod_rev(unsigned int pmic_id)
407 {
408         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
409                 return tx6_mod_revs[pmic_id].rev;
410
411         return 0;
412 }
413
414 static int tx6_pmic_probe(void)
415 {
416         int i;
417
418         debug("%s@%d: \n", __func__, __LINE__);
419
420 //      i2c_init_all();
421
422         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
423                 u8 i2c_addr = tx6_mod_revs[i].addr;
424                 int ret = i2c_probe(i2c_addr);
425
426                 if (ret == 0) {
427                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
428                         return i;
429                 }
430                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
431         }
432         return -EINVAL;
433 }
434
435 static inline int __checkboard(void)
436 {
437         u32 cpurev = get_cpu_rev();
438         int cpu_variant = (cpurev >> 12) & 0xff;
439         int pmic_id;
440
441         debug("%s@%d: \n", __func__, __LINE__);
442
443         pmic_id = tx6_pmic_probe();
444         if (pmic_id >= 0)
445                 pmic_addr = tx6_mod_revs[pmic_id].addr;
446
447         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
448                 tx6_mod_suffix,
449                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
450                 is_lvds(), tx6_get_mod_rev(pmic_id),
451                 tx6_mem_suffix());
452
453         get_hab_status();
454
455         debug("%s@%d: done\n", __func__, __LINE__);
456         return 0;
457 }
458
459 int board_init(void)
460 {
461         int ret;
462         u32 cpurev = get_cpu_rev();
463         int cpu_variant = (cpurev >> 12) & 0xff;
464         int pmic_id;
465
466         debug("%s@%d: \n", __func__, __LINE__);
467
468         pmic_id = tx6_pmic_probe();
469         if (pmic_id >= 0)
470                 pmic_addr = tx6_mod_revs[pmic_id].addr;
471
472         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
473                 tx6_mod_suffix,
474                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
475                 is_lvds(), tx6_get_mod_rev(pmic_id),
476                 tx6_mem_suffix());
477
478         get_hab_status();
479
480         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
481         if (ret < 0) {
482                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
483         }
484         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
485
486         /* Address of boot parameters */
487         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
488         gd->bd->bi_arch_number = -1;
489
490         if (ctrlc() || (wrsr & WRSR_TOUT)) {
491                 if (wrsr & WRSR_TOUT)
492                         printf("WDOG RESET detected; Skipping PMIC setup\n");
493                 else
494                         printf("<CTRL-C> detected; safeboot enabled\n");
495 #ifndef CONFIG_MX6_TEMPERATURE_HOT
496                 tx6_temp_check_enabled = false;
497 #endif
498                 return 0;
499         }
500
501         ret = tx6_pmic_init(pmic_addr);
502         if (ret) {
503                 printf("Failed to setup PMIC voltages: %d\n", ret);
504                 hang();
505         }
506         return 0;
507 }
508
509 int dram_init(void)
510 {
511         debug("%s@%d: \n", __func__, __LINE__);
512
513         /* dram_init must store complete ramsize in gd->ram_size */
514         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
515                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
516         return 0;
517 }
518
519 void dram_init_banksize(void)
520 {
521         debug("%s@%d: \n", __func__, __LINE__);
522
523         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
524         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
525                         PHYS_SDRAM_1_SIZE);
526 #if CONFIG_NR_DRAM_BANKS > 1
527         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
528         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
529                         PHYS_SDRAM_2_SIZE);
530 #endif
531 }
532
533 #ifdef  CONFIG_FSL_ESDHC
534 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
535         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
536         PAD_CTL_SRE_FAST)
537
538 static const iomux_v3_cfg_t mmc0_pads[] = {
539         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
540         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
541         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
542         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
543         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
544         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
545         /* SD1 CD */
546         MX6_PAD_SD3_CMD__GPIO7_IO02,
547 };
548
549 static const iomux_v3_cfg_t mmc1_pads[] = {
550         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
551         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
552         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
553         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
554         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
555         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
556         /* SD2 CD */
557         MX6_PAD_SD3_CLK__GPIO7_IO03,
558 };
559
560 #ifdef CONFIG_TX6_EMMC
561 static const iomux_v3_cfg_t mmc3_pads[] = {
562         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
563         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
564         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
565         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
566         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
567         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
568         /* eMMC RESET */
569         MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
570                                                 PAD_CTL_DSE_40ohm),
571 };
572 #endif
573
574 static struct tx6_esdhc_cfg {
575         const iomux_v3_cfg_t *pads;
576         int num_pads;
577         enum mxc_clock clkid;
578         struct fsl_esdhc_cfg cfg;
579         int cd_gpio;
580 } tx6qdl_esdhc_cfg[] = {
581 #ifdef CONFIG_TX6_EMMC
582         {
583                 .pads = mmc3_pads,
584                 .num_pads = ARRAY_SIZE(mmc3_pads),
585                 .clkid = MXC_ESDHC4_CLK,
586                 .cfg = {
587                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
588                         .max_bus_width = 4,
589                 },
590                 .cd_gpio = -EINVAL,
591         },
592 #endif
593         {
594                 .pads = mmc0_pads,
595                 .num_pads = ARRAY_SIZE(mmc0_pads),
596                 .clkid = MXC_ESDHC_CLK,
597                 .cfg = {
598                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
599                         .max_bus_width = 4,
600                 },
601                 .cd_gpio = IMX_GPIO_NR(7, 2),
602         },
603         {
604                 .pads = mmc1_pads,
605                 .num_pads = ARRAY_SIZE(mmc1_pads),
606                 .clkid = MXC_ESDHC2_CLK,
607                 .cfg = {
608                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
609                         .max_bus_width = 4,
610                 },
611                 .cd_gpio = IMX_GPIO_NR(7, 3),
612         },
613 };
614
615 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
616 {
617         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
618 }
619
620 int board_mmc_getcd(struct mmc *mmc)
621 {
622         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
623
624         if (cfg->cd_gpio < 0)
625                 return 1;
626
627         debug("SD card %d is %spresent (GPIO %d)\n",
628                 cfg - tx6qdl_esdhc_cfg,
629                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
630                 cfg->cd_gpio);
631         return !gpio_get_value(cfg->cd_gpio);
632 }
633
634 int board_mmc_init(bd_t *bis)
635 {
636         int i;
637
638         debug("%s@%d: \n", __func__, __LINE__);
639
640         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
641                 struct mmc *mmc;
642                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
643                 int ret;
644
645                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
646                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
647
648                 if (cfg->cd_gpio >= 0) {
649                         ret = gpio_request_one(cfg->cd_gpio,
650                                         GPIOFLAG_INPUT, "MMC CD");
651                         if (ret) {
652                                 printf("Error %d requesting GPIO%d_%d\n",
653                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
654                                 continue;
655                         }
656                 }
657
658                 debug("%s: Initializing MMC slot %d\n", __func__, i);
659                 fsl_esdhc_initialize(bis, &cfg->cfg);
660
661                 mmc = find_mmc_device(i);
662                 if (mmc == NULL)
663                         continue;
664                 if (board_mmc_getcd(mmc))
665                         mmc_init(mmc);
666         }
667         return 0;
668 }
669 #endif /* CONFIG_CMD_MMC */
670
671 #ifdef CONFIG_FEC_MXC
672
673 #ifndef ETH_ALEN
674 #define ETH_ALEN 6
675 #endif
676
677 int board_eth_init(bd_t *bis)
678 {
679         int ret;
680
681         debug("%s@%d: \n", __func__, __LINE__);
682
683         /* delay at least 21ms for the PHY internal POR signal to deassert */
684         udelay(22000);
685
686         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
687                                         ARRAY_SIZE(tx6qdl_fec_pads));
688
689         /* Deassert RESET to the external phy */
690         gpio_set_value(TX6_FEC_RST_GPIO, 1);
691
692         ret = cpu_eth_init(bis);
693         if (ret)
694                 printf("cpu_eth_init() failed: %d\n", ret);
695
696         return ret;
697 }
698
699 static void tx6_init_mac(void)
700 {
701         u8 mac[ETH_ALEN];
702
703         imx_get_mac_from_fuse(-1, mac);
704         if (!is_valid_ethaddr(mac)) {
705                 printf("No valid MAC address programmed\n");
706                 return;
707         }
708
709         printf("MAC addr from fuse: %pM\n", mac);
710         eth_setenv_enetaddr("ethaddr", mac);
711 }
712 #else
713 static inline void tx6_init_mac(void)
714 {
715 }
716 #endif /* CONFIG_FEC_MXC */
717
718 enum {
719         LED_STATE_INIT = -1,
720         LED_STATE_OFF,
721         LED_STATE_ON,
722 };
723
724 static inline int calc_blink_rate(void)
725 {
726         if (!tx6_temp_check_enabled)
727                 return CONFIG_SYS_HZ;
728
729         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
730                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
731                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
732 }
733
734 void show_activity(int arg)
735 {
736         static int led_state = LED_STATE_INIT;
737         static int blink_rate;
738         static ulong last;
739
740         if (led_state == LED_STATE_INIT) {
741                 last = get_timer(0);
742                 gpio_set_value(TX6_LED_GPIO, 1);
743                 led_state = LED_STATE_ON;
744                 blink_rate = calc_blink_rate();
745         } else {
746                 if (get_timer(last) > blink_rate) {
747                         blink_rate = calc_blink_rate();
748                         last = get_timer_masked();
749                         if (led_state == LED_STATE_ON) {
750                                 gpio_set_value(TX6_LED_GPIO, 0);
751                         } else {
752                                 gpio_set_value(TX6_LED_GPIO, 1);
753                         }
754                         led_state = 1 - led_state;
755                 }
756         }
757 }
758
759 static const iomux_v3_cfg_t stk5_pads[] = {
760         /* SW controlled LED on STK5 baseboard */
761         MX6_PAD_EIM_A18__GPIO2_IO20,
762
763         /* I2C bus on DIMM pins 40/41 */
764         MX6_PAD_GPIO_6__I2C3_SDA,
765         MX6_PAD_GPIO_3__I2C3_SCL,
766
767         /* TSC200x PEN IRQ */
768         MX6_PAD_EIM_D26__GPIO3_IO26,
769
770         /* EDT-FT5x06 Polytouch panel */
771         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
772         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
773         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
774
775         /* USBH1 */
776         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
777         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
778         /* USBOTG */
779         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
780         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
781         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
782 };
783
784 static const struct gpio stk5_gpios[] = {
785         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
786
787         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
788         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
789         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
790         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
791         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
792 };
793
794 #ifdef CONFIG_LCD
795 static u16 tx6_cmap[256];
796 vidinfo_t panel_info = {
797         /* set to max. size supported by SoC */
798         .vl_col = 1920,
799         .vl_row = 1080,
800
801         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
802         .cmap = tx6_cmap,
803 };
804
805 static struct fb_videomode tx6_fb_modes[] = {
806 #ifndef CONFIG_SYS_LVDS_IF
807         {
808                 /* Standard VGA timing */
809                 .name           = "VGA",
810                 .refresh        = 60,
811                 .xres           = 640,
812                 .yres           = 480,
813                 .pixclock       = KHZ2PICOS(25175),
814                 .left_margin    = 48,
815                 .hsync_len      = 96,
816                 .right_margin   = 16,
817                 .upper_margin   = 31,
818                 .vsync_len      = 2,
819                 .lower_margin   = 12,
820                 .sync           = FB_SYNC_CLK_LAT_FALL,
821         },
822         {
823                 /* Emerging ETV570 640 x 480 display. Syncs low active,
824                  * DE high active, 115.2 mm x 86.4 mm display area
825                  * VGA compatible timing
826                  */
827                 .name           = "ETV570",
828                 .refresh        = 60,
829                 .xres           = 640,
830                 .yres           = 480,
831                 .pixclock       = KHZ2PICOS(25175),
832                 .left_margin    = 114,
833                 .hsync_len      = 30,
834                 .right_margin   = 16,
835                 .upper_margin   = 32,
836                 .vsync_len      = 3,
837                 .lower_margin   = 10,
838                 .sync           = FB_SYNC_CLK_LAT_FALL,
839         },
840         {
841                 /* Emerging ET0350G0DH6 320 x 240 display.
842                  * 70.08 mm x 52.56 mm display area.
843                  */
844                 .name           = "ET0350",
845                 .refresh        = 60,
846                 .xres           = 320,
847                 .yres           = 240,
848                 .pixclock       = KHZ2PICOS(6500),
849                 .left_margin    = 68 - 34,
850                 .hsync_len      = 34,
851                 .right_margin   = 20,
852                 .upper_margin   = 18 - 3,
853                 .vsync_len      = 3,
854                 .lower_margin   = 4,
855                 .sync           = FB_SYNC_CLK_LAT_FALL,
856         },
857         {
858                 /* Emerging ET0430G0DH6 480 x 272 display.
859                  * 95.04 mm x 53.856 mm display area.
860                  */
861                 .name           = "ET0430",
862                 .refresh        = 60,
863                 .xres           = 480,
864                 .yres           = 272,
865                 .pixclock       = KHZ2PICOS(9000),
866                 .left_margin    = 2,
867                 .hsync_len      = 41,
868                 .right_margin   = 2,
869                 .upper_margin   = 2,
870                 .vsync_len      = 10,
871                 .lower_margin   = 2,
872         },
873         {
874                 /* Emerging ET0500G0DH6 800 x 480 display.
875                  * 109.6 mm x 66.4 mm display area.
876                  */
877                 .name           = "ET0500",
878                 .refresh        = 60,
879                 .xres           = 800,
880                 .yres           = 480,
881                 .pixclock       = KHZ2PICOS(33260),
882                 .left_margin    = 216 - 128,
883                 .hsync_len      = 128,
884                 .right_margin   = 1056 - 800 - 216,
885                 .upper_margin   = 35 - 2,
886                 .vsync_len      = 2,
887                 .lower_margin   = 525 - 480 - 35,
888                 .sync           = FB_SYNC_CLK_LAT_FALL,
889         },
890         {
891                 /* Emerging ETQ570G0DH6 320 x 240 display.
892                  * 115.2 mm x 86.4 mm display area.
893                  */
894                 .name           = "ETQ570",
895                 .refresh        = 60,
896                 .xres           = 320,
897                 .yres           = 240,
898                 .pixclock       = KHZ2PICOS(6400),
899                 .left_margin    = 38,
900                 .hsync_len      = 30,
901                 .right_margin   = 30,
902                 .upper_margin   = 16, /* 15 according to datasheet */
903                 .vsync_len      = 3, /* TVP -> 1>x>5 */
904                 .lower_margin   = 4, /* 4.5 according to datasheet */
905                 .sync           = FB_SYNC_CLK_LAT_FALL,
906         },
907         {
908                 /* Emerging ET0700G0DH6 800 x 480 display.
909                  * 152.4 mm x 91.44 mm display area.
910                  */
911                 .name           = "ET0700",
912                 .refresh        = 60,
913                 .xres           = 800,
914                 .yres           = 480,
915                 .pixclock       = KHZ2PICOS(33260),
916                 .left_margin    = 216 - 128,
917                 .hsync_len      = 128,
918                 .right_margin   = 1056 - 800 - 216,
919                 .upper_margin   = 35 - 2,
920                 .vsync_len      = 2,
921                 .lower_margin   = 525 - 480 - 35,
922                 .sync           = FB_SYNC_CLK_LAT_FALL,
923         },
924         {
925                 /* Emerging ET070001DM6 800 x 480 display.
926                  * 152.4 mm x 91.44 mm display area.
927                  */
928                 .name           = "ET070001DM6",
929                 .refresh        = 60,
930                 .xres           = 800,
931                 .yres           = 480,
932                 .pixclock       = KHZ2PICOS(33260),
933                 .left_margin    = 216 - 128,
934                 .hsync_len      = 128,
935                 .right_margin   = 1056 - 800 - 216,
936                 .upper_margin   = 35 - 2,
937                 .vsync_len      = 2,
938                 .lower_margin   = 525 - 480 - 35,
939                 .sync           = 0,
940         },
941 #else
942         {
943                 /* HannStar HSD100PXN1
944                  * 202.7m mm x 152.06 mm display area.
945                  */
946                 .name           = "HSD100PXN1",
947                 .refresh        = 60,
948                 .xres           = 1024,
949                 .yres           = 768,
950                 .pixclock       = KHZ2PICOS(65000),
951                 .left_margin    = 0,
952                 .hsync_len      = 0,
953                 .right_margin   = 320,
954                 .upper_margin   = 0,
955                 .vsync_len      = 0,
956                 .lower_margin   = 38,
957                 .sync           = FB_SYNC_CLK_LAT_FALL,
958         },
959 #endif
960         {
961                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
962                 .refresh        = 60,
963                 .left_margin    = 48,
964                 .hsync_len      = 96,
965                 .right_margin   = 16,
966                 .upper_margin   = 31,
967                 .vsync_len      = 2,
968                 .lower_margin   = 12,
969                 .sync           = FB_SYNC_CLK_LAT_FALL,
970         },
971 };
972
973 static int lcd_enabled = 1;
974 static int lcd_bl_polarity;
975
976 static int lcd_backlight_polarity(void)
977 {
978         return lcd_bl_polarity;
979 }
980
981 void lcd_enable(void)
982 {
983         /* HACK ALERT:
984          * global variable from common/lcd.c
985          * Set to 0 here to prevent messages from going to LCD
986          * rather than serial console
987          */
988         lcd_is_enabled = 0;
989
990         if (lcd_enabled) {
991                 karo_load_splashimage(1);
992
993                 debug("Switching LCD on\n");
994                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
995                 udelay(100);
996                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
997                 udelay(300000);
998                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
999                         lcd_backlight_polarity());
1000         }
1001 }
1002
1003 void lcd_disable(void)
1004 {
1005         if (lcd_enabled) {
1006                 printf("Disabling LCD\n");
1007                 ipuv3_fb_shutdown();
1008         }
1009 }
1010
1011 void lcd_panel_disable(void)
1012 {
1013         if (lcd_enabled) {
1014                 debug("Switching LCD off\n");
1015                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1016                         !lcd_backlight_polarity());
1017                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1018                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1019         }
1020 }
1021
1022 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1023         /* LCD RESET */
1024         MX6_PAD_EIM_D29__GPIO3_IO29,
1025         /* LCD POWER_ENABLE */
1026         MX6_PAD_EIM_EB3__GPIO2_IO31,
1027         /* LCD Backlight (PWM) */
1028         MX6_PAD_GPIO_1__GPIO1_IO01,
1029
1030 #ifndef CONFIG_SYS_LVDS_IF
1031         /* Display */
1032         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
1033         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
1034         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
1035         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
1036         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
1037         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
1038         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
1039         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
1040         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
1041         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
1042         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
1043         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
1044         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
1045         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
1046         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
1047         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
1048         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
1049         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
1050         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
1051         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
1052         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
1053         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
1054         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
1055         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
1056         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
1057         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
1058         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
1059         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
1060 #endif
1061 };
1062
1063 static const struct gpio stk5_lcd_gpios[] = {
1064         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1065         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1066         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1067 };
1068
1069 void lcd_ctrl_init(void *lcdbase)
1070 {
1071         int color_depth = 24;
1072         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1073         const char *vm;
1074         unsigned long val;
1075         int refresh = 60;
1076         struct fb_videomode *p = &tx6_fb_modes[0];
1077         struct fb_videomode fb_mode;
1078         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1079         int pix_fmt;
1080         int lcd_bus_width;
1081         unsigned long di_clk_rate = 65000000;
1082
1083         if (!lcd_enabled) {
1084                 debug("LCD disabled\n");
1085                 return;
1086         }
1087
1088         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1089                 debug("Disabling LCD\n");
1090                 lcd_enabled = 0;
1091                 setenv("splashimage", NULL);
1092                 return;
1093         }
1094
1095         karo_fdt_move_fdt();
1096         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1097
1098         if (video_mode == NULL) {
1099                 debug("Disabling LCD\n");
1100                 lcd_enabled = 0;
1101                 return;
1102         }
1103         vm = video_mode;
1104         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1105                 p = &fb_mode;
1106                 debug("Using video mode from FDT\n");
1107                 vm += strlen(vm);
1108                 if (fb_mode.xres > panel_info.vl_col ||
1109                         fb_mode.yres > panel_info.vl_row) {
1110                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1111                                 fb_mode.xres, fb_mode.yres,
1112                                 panel_info.vl_col, panel_info.vl_row);
1113                         lcd_enabled = 0;
1114                         return;
1115                 }
1116         }
1117         if (p->name != NULL)
1118                 debug("Trying compiled-in video modes\n");
1119         while (p->name != NULL) {
1120                 if (strcmp(p->name, vm) == 0) {
1121                         debug("Using video mode: '%s'\n", p->name);
1122                         vm += strlen(vm);
1123                         break;
1124                 }
1125                 p++;
1126         }
1127         if (*vm != '\0')
1128                 debug("Trying to decode video_mode: '%s'\n", vm);
1129         while (*vm != '\0') {
1130                 if (*vm >= '0' && *vm <= '9') {
1131                         char *end;
1132
1133                         val = simple_strtoul(vm, &end, 0);
1134                         if (end > vm) {
1135                                 if (!xres_set) {
1136                                         if (val > panel_info.vl_col)
1137                                                 val = panel_info.vl_col;
1138                                         p->xres = val;
1139                                         panel_info.vl_col = val;
1140                                         xres_set = 1;
1141                                 } else if (!yres_set) {
1142                                         if (val > panel_info.vl_row)
1143                                                 val = panel_info.vl_row;
1144                                         p->yres = val;
1145                                         panel_info.vl_row = val;
1146                                         yres_set = 1;
1147                                 } else if (!bpp_set) {
1148                                         switch (val) {
1149                                         case 32:
1150                                         case 24:
1151                                                 if (is_lvds())
1152                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1153                                                 /* fallthru */
1154                                         case 16:
1155                                         case 8:
1156                                                 color_depth = val;
1157                                                 break;
1158
1159                                         case 18:
1160                                                 if (is_lvds()) {
1161                                                         color_depth = val;
1162                                                         break;
1163                                                 }
1164                                                 /* fallthru */
1165                                         default:
1166                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1167                                                         end - vm, vm, color_depth);
1168                                         }
1169                                         bpp_set = 1;
1170                                 } else if (!refresh_set) {
1171                                         refresh = val;
1172                                         refresh_set = 1;
1173                                 }
1174                         }
1175                         vm = end;
1176                 }
1177                 switch (*vm) {
1178                 case '@':
1179                         bpp_set = 1;
1180                         /* fallthru */
1181                 case '-':
1182                         yres_set = 1;
1183                         /* fallthru */
1184                 case 'x':
1185                         xres_set = 1;
1186                         /* fallthru */
1187                 case 'M':
1188                 case 'R':
1189                         vm++;
1190                         break;
1191
1192                 default:
1193                         if (*vm != '\0')
1194                                 vm++;
1195                 }
1196         }
1197         if (p->xres == 0 || p->yres == 0) {
1198                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1199                 lcd_enabled = 0;
1200                 printf("Supported video modes are:");
1201                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1202                         printf(" %s", p->name);
1203                 }
1204                 printf("\n");
1205                 return;
1206         }
1207         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1208                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1209                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1210                 lcd_enabled = 0;
1211                 return;
1212         }
1213         panel_info.vl_col = p->xres;
1214         panel_info.vl_row = p->yres;
1215
1216         switch (color_depth) {
1217         case 8:
1218                 panel_info.vl_bpix = LCD_COLOR8;
1219                 break;
1220         case 16:
1221                 panel_info.vl_bpix = LCD_COLOR16;
1222                 break;
1223         default:
1224                 panel_info.vl_bpix = LCD_COLOR32;
1225         }
1226
1227         p->pixclock = KHZ2PICOS(refresh *
1228                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1229                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1230                                 1000);
1231         debug("Pixel clock set to %lu.%03lu MHz\n",
1232                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1233
1234         if (p != &fb_mode) {
1235                 int ret;
1236
1237                 debug("Creating new display-timing node from '%s'\n",
1238                         video_mode);
1239                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1240                 if (ret)
1241                         printf("Failed to create new display-timing node from '%s': %d\n",
1242                                 video_mode, ret);
1243         }
1244
1245         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1246         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1247                                         ARRAY_SIZE(stk5_lcd_pads));
1248
1249         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1250         switch (lcd_bus_width) {
1251         case 24:
1252                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1253                 break;
1254
1255         case 18:
1256                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1257                 break;
1258
1259         case 16:
1260                 if (!is_lvds()) {
1261                         pix_fmt = IPU_PIX_FMT_RGB565;
1262                         break;
1263                 }
1264                 /* fallthru */
1265         default:
1266                 lcd_enabled = 0;
1267                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1268                         lcd_bus_width);
1269                 return;
1270         }
1271         if (is_lvds()) {
1272                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1273                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1274                 uint32_t gpr2;
1275                 uint32_t gpr3;
1276
1277                 if (lvds_chan_mask == 0) {
1278                         printf("No LVDS channel active\n");
1279                         lcd_enabled = 0;
1280                         return;
1281                 }
1282
1283                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1284                 if (lcd_bus_width == 24)
1285                         gpr2 |= (1 << 5) | (1 << 7);
1286                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1287                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1288                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1289                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1290
1291                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1292                 gpr3 &= ~((3 << 8) | (3 << 6));
1293                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1294         }
1295         if (karo_load_splashimage(0) == 0) {
1296                 int ret;
1297
1298                 debug("Initializing LCD controller\n");
1299                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1300                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1301                                 di_clk_rate, -1);
1302                 if (ret) {
1303                         printf("Failed to initialize FB driver: %d\n", ret);
1304                         lcd_enabled = 0;
1305                 }
1306         } else {
1307                 debug("Skipping initialization of LCD controller\n");
1308         }
1309 }
1310 #else
1311 #define lcd_enabled 0
1312 #endif /* CONFIG_LCD */
1313
1314 static void stk5_board_init(void)
1315 {
1316         int ret;
1317
1318         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1319         if (ret < 0) {
1320                 printf("Failed to request stk5_gpios: %d\n", ret);
1321                 return;
1322         }
1323         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1324 }
1325
1326 static void stk5v3_board_init(void)
1327 {
1328         stk5_board_init();
1329 }
1330
1331 static void stk5v5_board_init(void)
1332 {
1333         int ret;
1334
1335         stk5_board_init();
1336
1337         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1338                         "Flexcan Transceiver");
1339         if (ret) {
1340                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1341                 return;
1342         }
1343
1344         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1345 }
1346
1347 static void tx6qdl_set_cpu_clock(void)
1348 {
1349         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1350
1351         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1352                 return;
1353
1354         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1355                 printf("%s detected; skipping cpu clock change\n",
1356                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1357                 return;
1358         }
1359         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1360                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1361                 printf("CPU clock set to %lu.%03lu MHz\n",
1362                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1363         } else {
1364                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1365         }
1366 }
1367
1368 int board_late_init(void)
1369 {
1370         int ret = 0;
1371         const char *baseboard;
1372 #if 1
1373         /* override secure_boot fuse */
1374         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1375         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1376
1377         writel(0x12, &fuse->cfg5);
1378 #endif
1379
1380         debug("%s@%d: \n", __func__, __LINE__);
1381
1382         env_cleanup();
1383
1384         if (tx6_temp_check_enabled)
1385                 check_cpu_temperature(1);
1386
1387         tx6qdl_set_cpu_clock();
1388
1389         if (had_ctrlc())
1390                 setenv_ulong("safeboot", 1);
1391         else if (wrsr & WRSR_TOUT)
1392                 setenv_ulong("wdreset", 1);
1393         else
1394                 karo_fdt_move_fdt();
1395
1396         baseboard = getenv("baseboard");
1397         if (!baseboard)
1398                 goto exit;
1399
1400         printf("Baseboard: %s\n", baseboard);
1401
1402         if (strncmp(baseboard, "stk5", 4) == 0) {
1403                 if ((strlen(baseboard) == 4) ||
1404                         strcmp(baseboard, "stk5-v3") == 0) {
1405                         stk5v3_board_init();
1406                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1407                         const char *otg_mode = getenv("otg_mode");
1408
1409                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1410                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1411                                         otg_mode, baseboard);
1412                                 setenv("otg_mode", "none");
1413                         }
1414                         stk5v5_board_init();
1415                 } else {
1416                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1417                                 baseboard + 4);
1418                 }
1419         } else {
1420                 printf("WARNING: Unsupported baseboard: '%s'\n",
1421                         baseboard);
1422                 ret = -EINVAL;
1423         }
1424
1425 exit:
1426         tx6_init_mac();
1427
1428         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1429         clear_ctrlc();
1430         return ret;
1431 }
1432
1433 #ifdef CONFIG_SERIAL_TAG
1434 void get_board_serial(struct tag_serialnr *serialnr)
1435 {
1436         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1437         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1438
1439         serialnr->low = readl(&fuse->cfg0);
1440         serialnr->high = readl(&fuse->cfg1);
1441 }
1442 #endif
1443
1444 #if defined(CONFIG_OF_BOARD_SETUP)
1445 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1446 #include <jffs2/jffs2.h>
1447 #include <mtd_node.h>
1448 static struct node_info nodes[] = {
1449         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1450 };
1451 #else
1452 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1453 #endif
1454
1455 static const char *tx6_touchpanels[] = {
1456         "ti,tsc2007",
1457         "edt,edt-ft5x06",
1458         "eeti,egalax_ts",
1459 };
1460
1461 int ft_board_setup(void *blob, bd_t *bd)
1462 {
1463         const char *baseboard = getenv("baseboard");
1464         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1465         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1466         int ret;
1467
1468         ret = fdt_increase_size(blob, 4096);
1469         if (ret) {
1470                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1471                 return ret;
1472         }
1473         if (stk5_v5)
1474                 karo_fdt_enable_node(blob, "stk5led", 0);
1475
1476         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1477         fdt_fixup_ethernet(blob);
1478
1479         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1480                                 ARRAY_SIZE(tx6_touchpanels));
1481         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1482         karo_fdt_fixup_flexcan(blob, stk5_v5);
1483
1484         karo_fdt_update_fb_mode(blob, video_mode);
1485
1486         return 0;
1487 }
1488 #endif /* CONFIG_OF_BOARD_SETUP */