board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  38
  39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  42
  43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
  45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
  46
  47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  49 #else
  50 #define TEMPERATURE_MIN                 (-40)
  51 #endif
  52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  54 #else
  55 #define TEMPERATURE_HOT                 80
  56 #endif
  57
  58 DECLARE_GLOBAL_DATA_PTR;
  59
  60 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  61
  62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  63 #ifdef CONFIG_SECURE_BOOT
  64 char __csf_data[0] __attribute__((section(".__csf_data")));
  65 #endif
  66
  67 #define TX6_DEFAULT_PAD_CTRL    MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  68                                         PAD_CTL_SPEED_MED |             \
  69                                         PAD_CTL_DSE_40ohm |             \
  70                                         PAD_CTL_SRE_FAST)
  71 #define TX6_FEC_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  72                                         PAD_CTL_SPEED_MED |             \
  73                                         PAD_CTL_DSE_40ohm |             \
  74                                         PAD_CTL_SRE_FAST)
  75 #define TX6_GPIO_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  76                                         PAD_CTL_SPEED_MED |             \
  77                                         PAD_CTL_DSE_34ohm |             \
  78                                         PAD_CTL_SRE_FAST)
  79 #define TX6_I2C_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  80                                         PAD_CTL_HYS |                   \
  81                                         PAD_CTL_SPEED_LOW |             \
  82                                         PAD_CTL_DSE_40ohm |             \
  83                                         PAD_CTL_SRE_SLOW)
  84
  85 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
  86         /* RESET_OUT */
  87         MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
  88
  89         /* UART pads */
  90 #if CONFIG_MXC_UART_BASE == UART1_BASE
  91         MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
  92         MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
  93         MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
  94         MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
  95 #endif
  96 #if CONFIG_MXC_UART_BASE == UART2_BASE
  97         MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
  98         MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
  99         MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
 100         MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
 101 #endif
 102 #if CONFIG_MXC_UART_BASE == UART3_BASE
 103         MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
 104         MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
 105         MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
 106         MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
 107 #endif
 108         /* internal I2C */
 109         MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
 110         MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
 111
 112         /* FEC PHY GPIO functions */
 113         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
 114                         TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
 115         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
 116                         TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
 117         MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
 118 };
 119
 120 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 121         /* FEC functions */
 122         MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
 123         MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
 124         MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL,
 125         MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
 126         MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
 127         MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
 128         MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
 129         MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
 130         MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
 131         MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
 132 };
 133
 134 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
 135         /* internal I2C */
 136         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
 137                         TX6_GPIO_PAD_CTRL,
 138         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
 139                         TX6_GPIO_PAD_CTRL,
 140 };
 141
 142 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
 143         /* internal I2C */
 144         MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
 145         MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
 146 };
 147
 148 static const struct gpio const tx6qdl_gpios[] = {
 149         /* These two entries are used to forcefully reinitialize the I2C bus */
 150         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 151         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 152
 153         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 154         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 155         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 156         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 157 };
 158
 159 static int pmic_addr __data;
 160
 161 #if defined(CONFIG_SOC_MX6Q)
 162 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
 163 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
 164 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
 165 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
 166 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
 167 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
 168 #define I2C1_SEL_INPUT_VAL                      0
 169 #endif
 170 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 171 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
 172 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
 173 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
 174 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
 175 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
 176 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
 177 #define I2C1_SEL_INPUT_VAL                      1
 178 #endif
 179
 180 #define GPIO_DR 0
 181 #define GPIO_DIR 4
 182 #define GPIO_PSR 8
 183
 184 static void tx6_i2c_recover(void)
 185 {
 186         int i;
 187         int bad = 0;
 188 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
 189 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
 190
 191         if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
 192                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
 193                 return;
 194
 195         debug("Clearing I2C bus\n");
 196         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
 197                 printf("I2C SCL stuck LOW\n");
 198                 bad++;
 199
 200                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
 201                         GPIO3_BASE_ADDR + GPIO_DR);
 202                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
 203                         GPIO3_BASE_ADDR + GPIO_DIR);
 204         }
 205         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
 206                 printf("I2C SDA stuck LOW\n");
 207                 bad++;
 208
 209                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
 210                         GPIO3_BASE_ADDR + GPIO_DIR);
 211                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
 212                         GPIO3_BASE_ADDR + GPIO_DR);
 213                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
 214                         GPIO3_BASE_ADDR + GPIO_DIR);
 215
 216                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
 217                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
 218                 udelay(10);
 219
 220                 for (i = 0; i < 18; i++) {
 221                         u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
 222
 223                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 224                         writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
 225                         udelay(10);
 226                         if (reg & SCL_BIT &&
 227                                 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
 228                                 break;
 229                 }
 230         }
 231         if (bad) {
 232                 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
 233
 234                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
 235                         printf("I2C bus recovery succeeded\n");
 236                 } else {
 237                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
 238                                 SCL_BIT | SDA_BIT);
 239                 }
 240         }
 241         debug("Setting up I2C Pads\n");
 242         imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
 243                                         ARRAY_SIZE(tx6_i2c_pads));
 244 }
 245
 246 /* placed in section '.data' to prevent overwriting relocation info
 247  * overlayed with bss
 248  */
 249 static u32 wrsr __data;
 250
 251 #define WRSR_POR                        (1 << 4)
 252 #define WRSR_TOUT                       (1 << 1)
 253 #define WRSR_SFTW                       (1 << 0)
 254
 255 static void print_reset_cause(void)
 256 {
 257         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 258         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 259         u32 srsr;
 260         char *dlm = "";
 261
 262         printf("Reset cause: ");
 263
 264         srsr = readl(&src_regs->srsr);
 265         wrsr = readw(wdt_base + 4);
 266
 267         if (wrsr & WRSR_POR) {
 268                 printf("%sPOR", dlm);
 269                 dlm = " | ";
 270         }
 271         if (srsr & 0x00004) {
 272                 printf("%sCSU", dlm);
 273                 dlm = " | ";
 274         }
 275         if (srsr & 0x00008) {
 276                 printf("%sIPP USER", dlm);
 277                 dlm = " | ";
 278         }
 279         if (srsr & 0x00010) {
 280                 if (wrsr & WRSR_SFTW) {
 281                         printf("%sSOFT", dlm);
 282                         dlm = " | ";
 283                 }
 284                 if (wrsr & WRSR_TOUT) {
 285                         printf("%sWDOG", dlm);
 286                         dlm = " | ";
 287                 }
 288         }
 289         if (srsr & 0x00020) {
 290                 printf("%sJTAG HIGH-Z", dlm);
 291                 dlm = " | ";
 292         }
 293         if (srsr & 0x00040) {
 294                 printf("%sJTAG SW", dlm);
 295                 dlm = " | ";
 296         }
 297         if (srsr & 0x10000) {
 298                 printf("%sWARM BOOT", dlm);
 299                 dlm = " | ";
 300         }
 301         if (dlm[0] == '\0')
 302                 printf("unknown");
 303
 304         printf("\n");
 305 }
 306
 307 static const char __data *tx6_mod_suffix;
 308
 309 #ifdef CONFIG_IMX6_THERMAL
 310 #include <thermal.h>
 311 #include <imx_thermal.h>
 312 #include <fuse.h>
 313
 314 static void print_temperature(void)
 315 {
 316         struct udevice *thermal_dev;
 317         int cpu_tmp, minc, maxc, ret;
 318         char const *grade_str;
 319         static u32 __data thermal_calib;
 320
 321         puts("Temperature: ");
 322         switch (get_cpu_temp_grade(&minc, &maxc)) {
 323         case TEMP_AUTOMOTIVE:
 324                 grade_str = "Automotive";
 325                 break;
 326         case TEMP_INDUSTRIAL:
 327                 grade_str = "Industrial";
 328                 break;
 329         case TEMP_EXTCOMMERCIAL:
 330                 grade_str = "Extended Commercial";
 331                 break;
 332         default:
 333                 grade_str = "Commercial";
 334         }
 335         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 336         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 337         if (ret == 0) {
 338                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 339
 340                 if (ret == 0)
 341                         printf(" at %dC", cpu_tmp);
 342                 else
 343                         puts(" - failed to read sensor data");
 344         } else {
 345                 puts(" - no sensor device found");
 346         }
 347
 348         if (fuse_read(1, 6, &thermal_calib) == 0) {
 349                 printf(" - calibration data 0x%08x\n", thermal_calib);
 350         } else {
 351                 puts(" - Failed to read thermal calib fuse\n");
 352         }
 353 }
 354 #else
 355 static inline void print_temperature(void)
 356 {
 357 }
 358 #endif
 359
 360 int checkboard(void)
 361 {
 362         u32 cpurev = get_cpu_rev();
 363         char *cpu_str = "?";
 364
 365         if (is_cpu_type(MXC_CPU_MX6SL)) {
 366                 cpu_str = "SL";
 367                 tx6_mod_suffix = "?";
 368         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
 369                 cpu_str = "DL";
 370                 tx6_mod_suffix = "U";
 371         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 372                 cpu_str = "SOLO";
 373                 tx6_mod_suffix = "S";
 374         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
 375                 cpu_str = "Q";
 376                 tx6_mod_suffix = "Q";
 377         } else if (is_cpu_type(MXC_CPU_MX6QP)) {
 378                 cpu_str = "QP";
 379                 tx6_mod_suffix = "QP";
 380         }
 381
 382         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
 383                 cpu_str,
 384                 (cpurev & 0x000F0) >> 4,
 385                 (cpurev & 0x0000F) >> 0,
 386                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 387
 388         print_temperature();
 389         print_reset_cause();
 390 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 391         check_cpu_temperature(1);
 392 #endif
 393         tx6_i2c_recover();
 394         return 0;
 395 }
 396
 397 /* serial port not initialized at this point */
 398 int board_early_init_f(void)
 399 {
 400         return 0;
 401 }
 402
 403 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 404 static bool tx6_temp_check_enabled = true;
 405 #else
 406 #define tx6_temp_check_enabled  0
 407 #endif
 408
 409 #ifdef CONFIG_TX6_NAND
 410 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
 411 #else
 412 #ifdef CONFIG_MMC_BOOT_SIZE
 413 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
 414 #else
 415 #define TX6_FLASH_SZ    2
 416 #endif
 417 #endif /* CONFIG_TX6_NAND */
 418
 419 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
 420
 421 static char tx6_mem_table[] = {
 422         '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
 423         '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
 424         '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
 425         '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
 426         '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
 427         '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
 428         '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
 429         '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
 430         '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
 431         '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
 432         '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
 433         '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
 434 };
 435
 436 #ifdef CONFIG_RN5T567
 437 /* PMIC settings */
 438 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 439 #define VDD_CORE_VAL            rn5t_mV_to_regval(1400)         /* DCDC1 */
 440 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 441 #define VDD_SOC_VAL             rn5t_mV_to_regval(1400)         /* DCDC2 */
 442 #define VDD_SOC_VAL_LP          rn5t_mV_to_regval(1400)
 443 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 444 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 445 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3000)         /* DCDC4 */
 446 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3000)
 447 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
 448 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
 449 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval2(3300)        /* LDO2 */
 450 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval2(3300)
 451
 452 static struct pmic_regs rn5t567_regs[] = {
 453         { RN5T567_NOETIMSET, 0x5, },
 454         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 455         { RN5T567_DC2DAC, VDD_SOC_VAL, },
 456         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 457         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
 458         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 459         { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
 460         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 461         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
 462         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 463         { RN5T567_DC2CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 464         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 465         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 466         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 467         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 468         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
 469         { RN5T567_LDO2DAC, VDD_IO_EXT_VAL, },
 470         { RN5T567_LDOEN1, 0x03, ~0x1f, },
 471         { RN5T567_LDOEN2, 0x10, ~0x30, },
 472         { RN5T567_LDODIS, 0x1c, ~0x1f, },
 473         { RN5T567_INTPOL, 0, },
 474         { RN5T567_INTEN, 0x3, },
 475         { RN5T567_IREN, 0xf, },
 476         { RN5T567_EN_GPIR, 0, },
 477 };
 478 #endif
 479
 480 static struct {
 481         uchar addr;
 482         uchar rev;
 483         struct pmic_regs *regs;
 484         size_t num_regs;
 485 } tx6_mod_revs[] = {
 486 #ifdef CONFIG_LTC3676
 487         { 0x3c, 1, NULL, 0, },
 488 #endif
 489 #ifdef CONFIG_RN5T567
 490         { 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), },
 491 #endif
 492 };
 493
 494 static inline char tx6_mem_suffix(void)
 495 {
 496         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
 497
 498         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
 499                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
 500
 501         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
 502                 return '?';
 503         if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
 504                 return '7';
 505         if (mem_idx == 8)
 506                 return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
 507         return tx6_mem_table[mem_idx];
 508 };
 509
 510 static int tx6_get_mod_rev(unsigned int pmic_id)
 511 {
 512         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
 513                 return tx6_mod_revs[pmic_id].rev;
 514
 515         return 0;
 516 }
 517
 518 static int tx6_pmic_probe(void)
 519 {
 520         int i;
 521
 522         debug("%s@%d: \n", __func__, __LINE__);
 523
 524         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
 525                 u8 i2c_addr = tx6_mod_revs[i].addr;
 526                 int ret = i2c_probe(i2c_addr);
 527
 528                 if (ret == 0) {
 529                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
 530                         return i;
 531                 }
 532                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
 533         }
 534         return -EINVAL;
 535 }
 536
 537 int board_init(void)
 538 {
 539         int ret;
 540         int pmic_id;
 541
 542         debug("%s@%d: \n", __func__, __LINE__);
 543
 544         pmic_id = tx6_pmic_probe();
 545         if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
 546                 pmic_addr = tx6_mod_revs[pmic_id].addr;
 547
 548         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
 549                 tx6_mod_suffix,
 550                 is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
 551                 is_lvds(), tx6_get_mod_rev(pmic_id),
 552                 tx6_mem_suffix());
 553
 554         get_hab_status();
 555
 556         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 557         if (ret < 0) {
 558                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
 559         }
 560         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 561
 562         /* Address of boot parameters */
 563         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 564         gd->bd->bi_arch_number = -1;
 565
 566         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 567                 if (wrsr & WRSR_TOUT)
 568                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 569                 else
 570                         printf("<CTRL-C> detected; safeboot enabled\n");
 571 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 572                 tx6_temp_check_enabled = false;
 573 #endif
 574                 return 0;
 575         }
 576
 577         ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs,
 578                         tx6_mod_revs[pmic_id].num_regs);
 579         if (ret) {
 580                 printf("Failed to setup PMIC voltages: %d\n", ret);
 581                 hang();
 582         }
 583         return 0;
 584 }
 585
 586 int dram_init(void)
 587 {
 588         debug("%s@%d: \n", __func__, __LINE__);
 589
 590         /* dram_init must store complete ramsize in gd->ram_size */
 591         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 592                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 593         return 0;
 594 }
 595
 596 void dram_init_banksize(void)
 597 {
 598         debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
 599                 CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
 600         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 601         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 602                         PHYS_SDRAM_1_SIZE);
 603 #if CONFIG_NR_DRAM_BANKS > 1
 604         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 605         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 606                         PHYS_SDRAM_2_SIZE);
 607 #endif
 608 }
 609
 610 #ifdef  CONFIG_FSL_ESDHC
 611 #define SD_PAD_CTRL             MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
 612                                 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 613                                 PAD_CTL_SRE_FAST)
 614
 615 static const iomux_v3_cfg_t mmc0_pads[] = {
 616         MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
 617         MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
 618         MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
 619         MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
 620         MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
 621         MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
 622         /* SD1 CD */
 623         MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
 624 };
 625
 626 static const iomux_v3_cfg_t mmc1_pads[] = {
 627         MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
 628         MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
 629         MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
 630         MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
 631         MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
 632         MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
 633         /* SD2 CD */
 634         MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
 635 };
 636
 637 #ifdef CONFIG_TX6_EMMC
 638 static const iomux_v3_cfg_t mmc3_pads[] = {
 639         MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
 640         MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
 641         MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
 642         MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
 643         MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
 644         MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
 645         /* eMMC RESET */
 646         MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
 647 };
 648 #endif
 649
 650 static struct tx6_esdhc_cfg {
 651         const iomux_v3_cfg_t *pads;
 652         int num_pads;
 653         enum mxc_clock clkid;
 654         struct fsl_esdhc_cfg cfg;
 655         int cd_gpio;
 656 } tx6qdl_esdhc_cfg[] = {
 657 #ifdef CONFIG_TX6_EMMC
 658         {
 659                 .pads = mmc3_pads,
 660                 .num_pads = ARRAY_SIZE(mmc3_pads),
 661                 .clkid = MXC_ESDHC4_CLK,
 662                 .cfg = {
 663                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 664                         .max_bus_width = 4,
 665                 },
 666                 .cd_gpio = -EINVAL,
 667         },
 668 #endif
 669         {
 670                 .pads = mmc0_pads,
 671                 .num_pads = ARRAY_SIZE(mmc0_pads),
 672                 .clkid = MXC_ESDHC_CLK,
 673                 .cfg = {
 674                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 675                         .max_bus_width = 4,
 676                 },
 677                 .cd_gpio = IMX_GPIO_NR(7, 2),
 678         },
 679         {
 680                 .pads = mmc1_pads,
 681                 .num_pads = ARRAY_SIZE(mmc1_pads),
 682                 .clkid = MXC_ESDHC2_CLK,
 683                 .cfg = {
 684                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 685                         .max_bus_width = 4,
 686                 },
 687                 .cd_gpio = IMX_GPIO_NR(7, 3),
 688         },
 689 };
 690
 691 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 692 {
 693         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 694 }
 695
 696 int board_mmc_getcd(struct mmc *mmc)
 697 {
 698         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 699
 700         if (cfg->cd_gpio < 0)
 701                 return 1;
 702
 703         debug("SD card %d is %spresent (GPIO %d)\n",
 704                 cfg - tx6qdl_esdhc_cfg,
 705                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 706                 cfg->cd_gpio);
 707         return !gpio_get_value(cfg->cd_gpio);
 708 }
 709
 710 int board_mmc_init(bd_t *bis)
 711 {
 712         int i;
 713
 714         debug("%s@%d: \n", __func__, __LINE__);
 715
 716         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 717                 struct mmc *mmc;
 718                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 719                 int ret;
 720
 721                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 722                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 723
 724                 if (cfg->cd_gpio >= 0) {
 725                         ret = gpio_request_one(cfg->cd_gpio,
 726                                         GPIOFLAG_INPUT, "MMC CD");
 727                         if (ret) {
 728                                 printf("Error %d requesting GPIO%d_%d\n",
 729                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 730                                 continue;
 731                         }
 732                 }
 733
 734                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 735                 fsl_esdhc_initialize(bis, &cfg->cfg);
 736
 737                 mmc = find_mmc_device(i);
 738                 if (mmc == NULL)
 739                         continue;
 740                 if (board_mmc_getcd(mmc))
 741                         mmc_init(mmc);
 742         }
 743         return 0;
 744 }
 745 #endif /* CONFIG_CMD_MMC */
 746
 747 #ifdef CONFIG_FEC_MXC
 748
 749 #ifndef ETH_ALEN
 750 #define ETH_ALEN 6
 751 #endif
 752
 753 int board_eth_init(bd_t *bis)
 754 {
 755         int ret;
 756
 757         debug("%s@%d: \n", __func__, __LINE__);
 758
 759         /* delay at least 21ms for the PHY internal POR signal to deassert */
 760         udelay(22000);
 761
 762         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
 763                                         ARRAY_SIZE(tx6qdl_fec_pads));
 764
 765         /* Deassert RESET to the external phy */
 766         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 767
 768         ret = cpu_eth_init(bis);
 769         if (ret)
 770                 printf("cpu_eth_init() failed: %d\n", ret);
 771
 772         return ret;
 773 }
 774
 775 static void tx6_init_mac(void)
 776 {
 777         u8 mac[ETH_ALEN];
 778
 779         imx_get_mac_from_fuse(0, mac);
 780         if (!is_valid_ethaddr(mac)) {
 781                 printf("No valid MAC address programmed\n");
 782                 return;
 783         }
 784
 785         printf("MAC addr from fuse: %pM\n", mac);
 786         eth_setenv_enetaddr("ethaddr", mac);
 787 }
 788 #else
 789 static inline void tx6_init_mac(void)
 790 {
 791 }
 792 #endif /* CONFIG_FEC_MXC */
 793
 794 enum {
 795         LED_STATE_INIT = -1,
 796         LED_STATE_OFF,
 797         LED_STATE_ON,
 798 };
 799
 800 static inline int calc_blink_rate(void)
 801 {
 802         if (!tx6_temp_check_enabled)
 803                 return CONFIG_SYS_HZ;
 804
 805         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 806                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 807                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 808 }
 809
 810 void show_activity(int arg)
 811 {
 812         static int led_state = LED_STATE_INIT;
 813         static int blink_rate;
 814         static ulong last;
 815
 816         if (led_state == LED_STATE_INIT) {
 817                 last = get_timer(0);
 818                 gpio_set_value(TX6_LED_GPIO, 1);
 819                 led_state = LED_STATE_ON;
 820                 blink_rate = calc_blink_rate();
 821         } else {
 822                 if (get_timer(last) > blink_rate) {
 823                         blink_rate = calc_blink_rate();
 824                         last = get_timer_masked();
 825                         if (led_state == LED_STATE_ON) {
 826                                 gpio_set_value(TX6_LED_GPIO, 0);
 827                         } else {
 828                                 gpio_set_value(TX6_LED_GPIO, 1);
 829                         }
 830                         led_state = 1 - led_state;
 831                 }
 832         }
 833 }
 834
 835 static const iomux_v3_cfg_t stk5_pads[] = {
 836         /* SW controlled LED on STK5 baseboard */
 837         MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
 838
 839         /* I2C bus on DIMM pins 40/41 */
 840         MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
 841         MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
 842
 843         /* TSC200x PEN IRQ */
 844         MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
 845
 846         /* EDT-FT5x06 Polytouch panel */
 847         MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
 848         MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
 849         MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
 850
 851         /* USBH1 */
 852         MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
 853         MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
 854         /* USBOTG */
 855         MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
 856         MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
 857         MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
 858 };
 859
 860 static const struct gpio stk5_gpios[] = {
 861         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 862
 863         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 864         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 865         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 866         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 867         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 868 };
 869
 870 #ifdef CONFIG_LCD
 871 vidinfo_t panel_info = {
 872         /* set to max. size supported by SoC */
 873         .vl_col = 1920,
 874         .vl_row = 1080,
 875
 876         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 877 };
 878
 879 static struct fb_videomode tx6_fb_modes[] = {
 880 #ifndef CONFIG_SYS_LVDS_IF
 881         {
 882                 /* Standard VGA timing */
 883                 .name           = "VGA",
 884                 .refresh        = 60,
 885                 .xres           = 640,
 886                 .yres           = 480,
 887                 .pixclock       = KHZ2PICOS(25175),
 888                 .left_margin    = 48,
 889                 .hsync_len      = 96,
 890                 .right_margin   = 16,
 891                 .upper_margin   = 31,
 892                 .vsync_len      = 2,
 893                 .lower_margin   = 12,
 894                 .sync           = FB_SYNC_CLK_LAT_FALL,
 895         },
 896         {
 897                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 898                  * DE high active, 115.2 mm x 86.4 mm display area
 899                  * VGA compatible timing
 900                  */
 901                 .name           = "ETV570",
 902                 .refresh        = 60,
 903                 .xres           = 640,
 904                 .yres           = 480,
 905                 .pixclock       = KHZ2PICOS(25175),
 906                 .left_margin    = 114,
 907                 .hsync_len      = 30,
 908                 .right_margin   = 16,
 909                 .upper_margin   = 32,
 910                 .vsync_len      = 3,
 911                 .lower_margin   = 10,
 912                 .sync           = FB_SYNC_CLK_LAT_FALL,
 913         },
 914         {
 915                 /* Emerging ET0350G0DH6 320 x 240 display.
 916                  * 70.08 mm x 52.56 mm display area.
 917                  */
 918                 .name           = "ET0350",
 919                 .refresh        = 60,
 920                 .xres           = 320,
 921                 .yres           = 240,
 922                 .pixclock       = KHZ2PICOS(6500),
 923                 .left_margin    = 68 - 34,
 924                 .hsync_len      = 34,
 925                 .right_margin   = 20,
 926                 .upper_margin   = 18 - 3,
 927                 .vsync_len      = 3,
 928                 .lower_margin   = 4,
 929                 .sync           = FB_SYNC_CLK_LAT_FALL,
 930         },
 931         {
 932                 /* Emerging ET0430G0DH6 480 x 272 display.
 933                  * 95.04 mm x 53.856 mm display area.
 934                  */
 935                 .name           = "ET0430",
 936                 .refresh        = 60,
 937                 .xres           = 480,
 938                 .yres           = 272,
 939                 .pixclock       = KHZ2PICOS(9000),
 940                 .left_margin    = 2,
 941                 .hsync_len      = 41,
 942                 .right_margin   = 2,
 943                 .upper_margin   = 2,
 944                 .vsync_len      = 10,
 945                 .lower_margin   = 2,
 946         },
 947         {
 948                 /* Emerging ET0500G0DH6 800 x 480 display.
 949                  * 109.6 mm x 66.4 mm display area.
 950                  */
 951                 .name           = "ET0500",
 952                 .refresh        = 60,
 953                 .xres           = 800,
 954                 .yres           = 480,
 955                 .pixclock       = KHZ2PICOS(33260),
 956                 .left_margin    = 216 - 128,
 957                 .hsync_len      = 128,
 958                 .right_margin   = 1056 - 800 - 216,
 959                 .upper_margin   = 35 - 2,
 960                 .vsync_len      = 2,
 961                 .lower_margin   = 525 - 480 - 35,
 962                 .sync           = FB_SYNC_CLK_LAT_FALL,
 963         },
 964         {
 965                 /* Emerging ETQ570G0DH6 320 x 240 display.
 966                  * 115.2 mm x 86.4 mm display area.
 967                  */
 968                 .name           = "ETQ570",
 969                 .refresh        = 60,
 970                 .xres           = 320,
 971                 .yres           = 240,
 972                 .pixclock       = KHZ2PICOS(6400),
 973                 .left_margin    = 38,
 974                 .hsync_len      = 30,
 975                 .right_margin   = 30,
 976                 .upper_margin   = 16, /* 15 according to datasheet */
 977                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 978                 .lower_margin   = 4, /* 4.5 according to datasheet */
 979                 .sync           = FB_SYNC_CLK_LAT_FALL,
 980         },
 981         {
 982                 /* Emerging ET0700G0DH6 800 x 480 display.
 983                  * 152.4 mm x 91.44 mm display area.
 984                  */
 985                 .name           = "ET0700",
 986                 .refresh        = 60,
 987                 .xres           = 800,
 988                 .yres           = 480,
 989                 .pixclock       = KHZ2PICOS(33260),
 990                 .left_margin    = 216 - 128,
 991                 .hsync_len      = 128,
 992                 .right_margin   = 1056 - 800 - 216,
 993                 .upper_margin   = 35 - 2,
 994                 .vsync_len      = 2,
 995                 .lower_margin   = 525 - 480 - 35,
 996                 .sync           = FB_SYNC_CLK_LAT_FALL,
 997         },
 998         {
 999                 /* Emerging ET070001DM6 800 x 480 display.
1000                  * 152.4 mm x 91.44 mm display area.
1001                  */
1002                 .name           = "ET070001DM6",
1003                 .refresh        = 60,
1004                 .xres           = 800,
1005                 .yres           = 480,
1006                 .pixclock       = KHZ2PICOS(33260),
1007                 .left_margin    = 216 - 128,
1008                 .hsync_len      = 128,
1009                 .right_margin   = 1056 - 800 - 216,
1010                 .upper_margin   = 35 - 2,
1011                 .vsync_len      = 2,
1012                 .lower_margin   = 525 - 480 - 35,
1013                 .sync           = 0,
1014         },
1015 #else
1016         {
1017                 /* HannStar HSD100PXN1
1018                  * 202.7m mm x 152.06 mm display area.
1019                  */
1020                 .name           = "HSD100PXN1",
1021                 .refresh        = 60,
1022                 .xres           = 1024,
1023                 .yres           = 768,
1024                 .pixclock       = KHZ2PICOS(65000),
1025                 .left_margin    = 0,
1026                 .hsync_len      = 0,
1027                 .right_margin   = 320,
1028                 .upper_margin   = 0,
1029                 .vsync_len      = 0,
1030                 .lower_margin   = 38,
1031                 .sync           = FB_SYNC_CLK_LAT_FALL,
1032         },
1033 #endif
1034         {
1035                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1036                 .refresh        = 60,
1037                 .left_margin    = 48,
1038                 .hsync_len      = 96,
1039                 .right_margin   = 16,
1040                 .upper_margin   = 31,
1041                 .vsync_len      = 2,
1042                 .lower_margin   = 12,
1043                 .sync           = FB_SYNC_CLK_LAT_FALL,
1044         },
1045 };
1046
1047 static int lcd_enabled = 1;
1048 static int lcd_bl_polarity;
1049
1050 static int lcd_backlight_polarity(void)
1051 {
1052         return lcd_bl_polarity;
1053 }
1054
1055 void lcd_enable(void)
1056 {
1057         /* HACK ALERT:
1058          * global variable from common/lcd.c
1059          * Set to 0 here to prevent messages from going to LCD
1060          * rather than serial console
1061          */
1062         lcd_is_enabled = 0;
1063
1064         if (lcd_enabled) {
1065                 karo_load_splashimage(1);
1066
1067                 debug("Switching LCD on\n");
1068                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1069                 udelay(100);
1070                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1071                 udelay(300000);
1072                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1073                         lcd_backlight_polarity());
1074         }
1075 }
1076
1077 void lcd_disable(void)
1078 {
1079         if (lcd_enabled) {
1080                 printf("Disabling LCD\n");
1081                 ipuv3_fb_shutdown();
1082         }
1083 }
1084
1085 void lcd_panel_disable(void)
1086 {
1087         if (lcd_enabled) {
1088                 debug("Switching LCD off\n");
1089                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1090                         !lcd_backlight_polarity());
1091                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1092                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1093         }
1094 }
1095
1096 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1097         /* LCD RESET */
1098         MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
1099         /* LCD POWER_ENABLE */
1100         MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
1101         /* LCD Backlight (PWM) */
1102         MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
1103
1104 #ifndef CONFIG_SYS_LVDS_IF
1105         /* Display */
1106         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
1107         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
1108         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
1109         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
1110         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
1111         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
1112         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
1113         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
1114         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
1115         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
1116         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
1117         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
1118         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
1119         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
1120         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
1121         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
1122         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
1123         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
1124         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
1125         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
1126         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
1127         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
1128         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
1129         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
1130         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
1131         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
1132         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
1133         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
1134 #endif
1135 };
1136
1137 static const struct gpio stk5_lcd_gpios[] = {
1138         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1139         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1140         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1141 };
1142
1143 void lcd_ctrl_init(void *lcdbase)
1144 {
1145         int color_depth = 24;
1146         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1147         const char *vm;
1148         unsigned long val;
1149         int refresh = 60;
1150         struct fb_videomode *p = &tx6_fb_modes[0];
1151         struct fb_videomode fb_mode;
1152         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1153         int pix_fmt;
1154         int lcd_bus_width;
1155         unsigned long di_clk_rate = 65000000;
1156
1157         if (!lcd_enabled) {
1158                 debug("LCD disabled\n");
1159                 goto disable;
1160         }
1161
1162         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1163                 debug("Disabling LCD\n");
1164                 lcd_enabled = 0;
1165                 setenv("splashimage", NULL);
1166                 goto disable;
1167         }
1168
1169         karo_fdt_move_fdt();
1170         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1171
1172         if (video_mode == NULL) {
1173                 debug("Disabling LCD\n");
1174                 lcd_enabled = 0;
1175                 goto disable;
1176         }
1177         vm = video_mode;
1178         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1179                 p = &fb_mode;
1180                 debug("Using video mode from FDT\n");
1181                 vm += strlen(vm);
1182                 if (fb_mode.xres > panel_info.vl_col ||
1183                         fb_mode.yres > panel_info.vl_row) {
1184                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1185                                 fb_mode.xres, fb_mode.yres,
1186                                 panel_info.vl_col, panel_info.vl_row);
1187                         lcd_enabled = 0;
1188                         goto disable;
1189                 }
1190         }
1191         if (p->name != NULL)
1192                 debug("Trying compiled-in video modes\n");
1193         while (p->name != NULL) {
1194                 if (strcmp(p->name, vm) == 0) {
1195                         debug("Using video mode: '%s'\n", p->name);
1196                         vm += strlen(vm);
1197                         break;
1198                 }
1199                 p++;
1200         }
1201         if (*vm != '\0')
1202                 debug("Trying to decode video_mode: '%s'\n", vm);
1203         while (*vm != '\0') {
1204                 if (*vm >= '0' && *vm <= '9') {
1205                         char *end;
1206
1207                         val = simple_strtoul(vm, &end, 0);
1208                         if (end > vm) {
1209                                 if (!xres_set) {
1210                                         if (val > panel_info.vl_col)
1211                                                 val = panel_info.vl_col;
1212                                         p->xres = val;
1213                                         panel_info.vl_col = val;
1214                                         xres_set = 1;
1215                                 } else if (!yres_set) {
1216                                         if (val > panel_info.vl_row)
1217                                                 val = panel_info.vl_row;
1218                                         p->yres = val;
1219                                         panel_info.vl_row = val;
1220                                         yres_set = 1;
1221                                 } else if (!bpp_set) {
1222                                         switch (val) {
1223                                         case 32:
1224                                         case 24:
1225                                                 if (is_lvds())
1226                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1227                                                 /* fallthru */
1228                                         case 16:
1229                                         case 8:
1230                                                 color_depth = val;
1231                                                 break;
1232
1233                                         case 18:
1234                                                 if (is_lvds()) {
1235                                                         color_depth = val;
1236                                                         break;
1237                                                 }
1238                                                 /* fallthru */
1239                                         default:
1240                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1241                                                         end - vm, vm, color_depth);
1242                                         }
1243                                         bpp_set = 1;
1244                                 } else if (!refresh_set) {
1245                                         refresh = val;
1246                                         refresh_set = 1;
1247                                 }
1248                         }
1249                         vm = end;
1250                 }
1251                 switch (*vm) {
1252                 case '@':
1253                         bpp_set = 1;
1254                         /* fallthru */
1255                 case '-':
1256                         yres_set = 1;
1257                         /* fallthru */
1258                 case 'x':
1259                         xres_set = 1;
1260                         /* fallthru */
1261                 case 'M':
1262                 case 'R':
1263                         vm++;
1264                         break;
1265
1266                 default:
1267                         if (*vm != '\0')
1268                                 vm++;
1269                 }
1270         }
1271         if (p->xres == 0 || p->yres == 0) {
1272                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1273                 lcd_enabled = 0;
1274                 printf("Supported video modes are:");
1275                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1276                         printf(" %s", p->name);
1277                 }
1278                 printf("\n");
1279                 goto disable;
1280         }
1281         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1282                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1283                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1284                 lcd_enabled = 0;
1285                 goto disable;
1286         }
1287         panel_info.vl_col = p->xres;
1288         panel_info.vl_row = p->yres;
1289
1290         switch (color_depth) {
1291         case 8:
1292                 panel_info.vl_bpix = LCD_COLOR8;
1293                 break;
1294         case 16:
1295                 panel_info.vl_bpix = LCD_COLOR16;
1296                 break;
1297         default:
1298                 panel_info.vl_bpix = LCD_COLOR32;
1299         }
1300
1301         p->pixclock = KHZ2PICOS(refresh *
1302                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1303                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1304                                 1000);
1305         debug("Pixel clock set to %lu.%03lu MHz\n",
1306                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1307
1308         if (p != &fb_mode) {
1309                 int ret;
1310
1311                 debug("Creating new display-timing node from '%s'\n",
1312                         video_mode);
1313                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1314                 if (ret)
1315                         printf("Failed to create new display-timing node from '%s': %d\n",
1316                                 video_mode, ret);
1317         }
1318
1319         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1320         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1321                                         ARRAY_SIZE(stk5_lcd_pads));
1322
1323         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1324         switch (lcd_bus_width) {
1325         case 24:
1326                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1327                 break;
1328
1329         case 18:
1330                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1331                 break;
1332
1333         case 16:
1334                 if (!is_lvds()) {
1335                         pix_fmt = IPU_PIX_FMT_RGB565;
1336                         break;
1337                 }
1338                 /* fallthru */
1339         default:
1340                 lcd_enabled = 0;
1341                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1342                         lcd_bus_width);
1343                 goto disable;
1344         }
1345         if (is_lvds()) {
1346                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1347                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1348                 uint32_t gpr2;
1349                 uint32_t gpr3;
1350
1351                 if (lvds_chan_mask == 0) {
1352                         printf("No LVDS channel active\n");
1353                         lcd_enabled = 0;
1354                         goto disable;
1355                 }
1356
1357                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1358                 if (lcd_bus_width == 24)
1359                         gpr2 |= (1 << 5) | (1 << 7);
1360                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1361                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1362                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1363                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1364
1365                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1366                 gpr3 &= ~((3 << 8) | (3 << 6));
1367                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1368         }
1369         if (karo_load_splashimage(0) == 0) {
1370                 int ret;
1371
1372                 debug("Initializing LCD controller\n");
1373                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1374                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1375                                 di_clk_rate, -1);
1376                 if (ret) {
1377                         printf("Failed to initialize FB driver: %d\n", ret);
1378                         lcd_enabled = 0;
1379                 }
1380         } else {
1381                 debug("Skipping initialization of LCD controller\n");
1382         }
1383         return;
1384
1385 disable:
1386         lcd_enabled = 0;
1387         panel_info.vl_col = 0;
1388         panel_info.vl_row = 0;
1389
1390 }
1391 #else
1392 #define lcd_enabled 0
1393 #endif /* CONFIG_LCD */
1394
1395 static void stk5_board_init(void)
1396 {
1397         int ret;
1398
1399         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1400         if (ret < 0) {
1401                 printf("Failed to request stk5_gpios: %d\n", ret);
1402                 return;
1403         }
1404         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1405 }
1406
1407 static void stk5v3_board_init(void)
1408 {
1409         stk5_board_init();
1410 }
1411
1412 static void stk5v5_board_init(void)
1413 {
1414         int ret;
1415
1416         stk5_board_init();
1417
1418         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1419                         "Flexcan Transceiver");
1420         if (ret) {
1421                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1422                 return;
1423         }
1424
1425         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
1426                         TX6_GPIO_PAD_CTRL);
1427 }
1428
1429 static void tx6qdl_set_cpu_clock(void)
1430 {
1431         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1432
1433         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1434                 return;
1435
1436         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1437                 printf("%s detected; skipping cpu clock change\n",
1438                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1439                 return;
1440         }
1441         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1442                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1443                 printf("CPU clock set to %lu.%03lu MHz\n",
1444                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1445         } else {
1446                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1447         }
1448 }
1449
1450 int board_late_init(void)
1451 {
1452         const char *baseboard;
1453
1454         debug("%s@%d: \n", __func__, __LINE__);
1455
1456         env_cleanup();
1457
1458         if (tx6_temp_check_enabled)
1459                 check_cpu_temperature(1);
1460
1461         tx6qdl_set_cpu_clock();
1462
1463         if (had_ctrlc())
1464                 setenv_ulong("safeboot", 1);
1465         else if (wrsr & WRSR_TOUT)
1466                 setenv_ulong("wdreset", 1);
1467         else
1468                 karo_fdt_move_fdt();
1469
1470         baseboard = getenv("baseboard");
1471         if (!baseboard)
1472                 goto exit;
1473
1474         printf("Baseboard: %s\n", baseboard);
1475
1476         if (strncmp(baseboard, "stk5", 4) == 0) {
1477                 if ((strlen(baseboard) == 4) ||
1478                         strcmp(baseboard, "stk5-v3") == 0) {
1479                         stk5v3_board_init();
1480                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1481                         const char *otg_mode = getenv("otg_mode");
1482
1483                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1484                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1485                                         otg_mode, baseboard);
1486                                 setenv("otg_mode", "none");
1487                         }
1488                         stk5v5_board_init();
1489                 } else {
1490                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1491                                 baseboard + 4);
1492                 }
1493         } else {
1494                 printf("WARNING: Unsupported baseboard: '%s'\n",
1495                         baseboard);
1496                 if (!had_ctrlc())
1497                         return -EINVAL;
1498         }
1499
1500 exit:
1501         tx6_init_mac();
1502
1503         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1504         clear_ctrlc();
1505         return 0;
1506 }
1507
1508 #ifdef CONFIG_SERIAL_TAG
1509 void get_board_serial(struct tag_serialnr *serialnr)
1510 {
1511         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1512         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1513
1514         serialnr->low = readl(&fuse->cfg0);
1515         serialnr->high = readl(&fuse->cfg1);
1516 }
1517 #endif
1518
1519 #if defined(CONFIG_OF_BOARD_SETUP)
1520 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1521 #include <jffs2/jffs2.h>
1522 #include <mtd_node.h>
1523 static struct node_info nodes[] = {
1524         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1525 };
1526 #else
1527 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1528 #endif
1529
1530 static const char *tx6_touchpanels[] = {
1531         "ti,tsc2007",
1532         "edt,edt-ft5x06",
1533         "eeti,egalax_ts",
1534 };
1535
1536 int ft_board_setup(void *blob, bd_t *bd)
1537 {
1538         const char *baseboard = getenv("baseboard");
1539         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1540         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1541         int ret;
1542
1543         ret = fdt_increase_size(blob, 4096);
1544         if (ret) {
1545                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1546                 return ret;
1547         }
1548         if (stk5_v5)
1549                 karo_fdt_enable_node(blob, "stk5led", 0);
1550
1551         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1552
1553         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1554                                 ARRAY_SIZE(tx6_touchpanels));
1555         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1556         karo_fdt_fixup_flexcan(blob, stk5_v5);
1557
1558         karo_fdt_update_fb_mode(blob, video_mode);
1559
1560         return 0;
1561 }
1562 #endif /* CONFIG_OF_BOARD_SETUP */