2f98b9bfaa0cd6d101d18adfce0da5bad39ef39f
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012,2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <common.h>
19 #include <errno.h>
20 #include <libfdt.h>
21 #include <fdt_support.h>
22 #include <lcd.h>
23 #include <netdev.h>
24 #include <mmc.h>
25 #include <fsl_esdhc.h>
26 #include <video_fb.h>
27 #include <ipu.h>
28 #include <mxcfb.h>
29 #include <i2c.h>
30 #include <linux/fb.h>
31 #include <asm/io.h>
32 #include <asm/gpio.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
38
39 #include "../common/karo.h"
40 #include "pmic.h"
41
42 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
43 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
44 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
45 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
46
47 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
48 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
49 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
50
51 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
52
53 #define TEMPERATURE_MIN                 -40
54 #define TEMPERATURE_HOT                 80
55 #define TEMPERATURE_MAX                 125
56
57 DECLARE_GLOBAL_DATA_PTR;
58
59 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
60
61 static const iomux_v3_cfg_t tx6qdl_pads[] = {
62         /* NAND flash pads */
63         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
64         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
65         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
66         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
67         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
68         MX6_PAD_SD4_CMD__RAWNAND_RDN,
69         MX6_PAD_SD4_CLK__RAWNAND_WRN,
70         MX6_PAD_NANDF_D0__RAWNAND_D0,
71         MX6_PAD_NANDF_D1__RAWNAND_D1,
72         MX6_PAD_NANDF_D2__RAWNAND_D2,
73         MX6_PAD_NANDF_D3__RAWNAND_D3,
74         MX6_PAD_NANDF_D4__RAWNAND_D4,
75         MX6_PAD_NANDF_D5__RAWNAND_D5,
76         MX6_PAD_NANDF_D6__RAWNAND_D6,
77         MX6_PAD_NANDF_D7__RAWNAND_D7,
78
79         /* RESET_OUT */
80         MX6_PAD_GPIO_17__GPIO_7_12,
81
82         /* UART pads */
83 #if CONFIG_MXC_UART_BASE == UART1_BASE
84         MX6_PAD_SD3_DAT7__UART1_TXD,
85         MX6_PAD_SD3_DAT6__UART1_RXD,
86         MX6_PAD_SD3_DAT1__UART1_RTS,
87         MX6_PAD_SD3_DAT0__UART1_CTS,
88 #endif
89 #if CONFIG_MXC_UART_BASE == UART2_BASE
90         MX6_PAD_SD4_DAT4__UART2_RXD,
91         MX6_PAD_SD4_DAT7__UART2_TXD,
92         MX6_PAD_SD4_DAT5__UART2_RTS,
93         MX6_PAD_SD4_DAT6__UART2_CTS,
94 #endif
95 #if CONFIG_MXC_UART_BASE == UART3_BASE
96         MX6_PAD_EIM_D24__UART3_TXD,
97         MX6_PAD_EIM_D25__UART3_RXD,
98         MX6_PAD_SD3_RST__UART3_RTS,
99         MX6_PAD_SD3_DAT3__UART3_CTS,
100 #endif
101         /* internal I2C */
102         MX6_PAD_EIM_D28__I2C1_SDA,
103         MX6_PAD_EIM_D21__I2C1_SCL,
104
105         /* FEC PHY GPIO functions */
106         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
107         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
108         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
109 };
110
111 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
112         /* FEC functions */
113         MX6_PAD_ENET_MDC__ENET_MDC,
114         MX6_PAD_ENET_MDIO__ENET_MDIO,
115         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
116         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
117         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
118         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
119         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
120         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
121         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
122         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
123 };
124
125 static const struct gpio tx6qdl_gpios[] = {
126         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
127         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
128         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
129         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
130 };
131
132 /*
133  * Functions
134  */
135 /* placed in section '.data' to prevent overwriting relocation info
136  * overlayed with bss
137  */
138 static u32 wrsr __attribute__((section(".data")));
139
140 #define WRSR_POR                        (1 << 4)
141 #define WRSR_TOUT                       (1 << 1)
142 #define WRSR_SFTW                       (1 << 0)
143
144 static void print_reset_cause(void)
145 {
146         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
147         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
148         u32 srsr;
149         char *dlm = "";
150
151         printf("Reset cause: ");
152
153         srsr = readl(&src_regs->srsr);
154         wrsr = readw(wdt_base + 4);
155
156         if (wrsr & WRSR_POR) {
157                 printf("%sPOR", dlm);
158                 dlm = " | ";
159         }
160         if (srsr & 0x00004) {
161                 printf("%sCSU", dlm);
162                 dlm = " | ";
163         }
164         if (srsr & 0x00008) {
165                 printf("%sIPP USER", dlm);
166                 dlm = " | ";
167         }
168         if (srsr & 0x00010) {
169                 if (wrsr & WRSR_SFTW) {
170                         printf("%sSOFT", dlm);
171                         dlm = " | ";
172                 }
173                 if (wrsr & WRSR_TOUT) {
174                         printf("%sWDOG", dlm);
175                         dlm = " | ";
176                 }
177         }
178         if (srsr & 0x00020) {
179                 printf("%sJTAG HIGH-Z", dlm);
180                 dlm = " | ";
181         }
182         if (srsr & 0x00040) {
183                 printf("%sJTAG SW", dlm);
184                 dlm = " | ";
185         }
186         if (srsr & 0x10000) {
187                 printf("%sWARM BOOT", dlm);
188                 dlm = " | ";
189         }
190         if (dlm[0] == '\0')
191                 printf("unknown");
192
193         printf("\n");
194 }
195
196 int read_cpu_temperature(void);
197 int check_cpu_temperature(int boot);
198
199 static void tx6qdl_print_cpuinfo(void)
200 {
201         u32 cpurev = get_cpu_rev();
202         char *cpu_str = "?";
203
204         switch ((cpurev >> 12) & 0xff) {
205         case MXC_CPU_MX6SL:
206                 cpu_str = "SL";
207                 break;
208         case MXC_CPU_MX6DL:
209                 cpu_str = "DL";
210                 break;
211         case MXC_CPU_MX6SOLO:
212                 cpu_str = "SOLO";
213                 break;
214         case MXC_CPU_MX6Q:
215                 cpu_str = "Q";
216                 break;
217         }
218
219         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
220                 cpu_str,
221                 (cpurev & 0x000F0) >> 4,
222                 (cpurev & 0x0000F) >> 0,
223                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
224
225         print_reset_cause();
226         check_cpu_temperature(1);
227 }
228
229 int board_early_init_f(void)
230 {
231         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
232         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
233
234         return 0;
235 }
236
237 int board_init(void)
238 {
239         int ret;
240
241         /* Address of boot parameters */
242         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
243         gd->bd->bi_arch_number = -1;
244
245         if (ctrlc()) {
246                 printf("CTRL-C detected; Skipping PMIC setup\n");
247                 return 1;
248         }
249
250         ret = setup_pmic_voltages();
251         if (ret) {
252                 printf("Failed to setup PMIC voltages\n");
253                 hang();
254         }
255         return 0;
256 }
257
258 int dram_init(void)
259 {
260         /* dram_init must store complete ramsize in gd->ram_size */
261         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
262                                 PHYS_SDRAM_1_SIZE);
263         return 0;
264 }
265
266 void dram_init_banksize(void)
267 {
268         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
269         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
270                         PHYS_SDRAM_1_SIZE);
271 #if CONFIG_NR_DRAM_BANKS > 1
272         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
273         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
274                         PHYS_SDRAM_2_SIZE);
275 #endif
276 }
277
278 #ifdef  CONFIG_CMD_MMC
279 static const iomux_v3_cfg_t mmc0_pads[] = {
280         MX6_PAD_SD1_CMD__USDHC1_CMD,
281         MX6_PAD_SD1_CLK__USDHC1_CLK,
282         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
283         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
284         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
285         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
286         /* SD1 CD */
287         MX6_PAD_SD3_CMD__GPIO_7_2,
288 };
289
290 static const iomux_v3_cfg_t mmc1_pads[] = {
291         MX6_PAD_SD2_CMD__USDHC2_CMD,
292         MX6_PAD_SD2_CLK__USDHC2_CLK,
293         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
294         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
295         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
296         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
297         /* SD2 CD */
298         MX6_PAD_SD3_CLK__GPIO_7_3,
299 };
300
301 static struct tx6_esdhc_cfg {
302         const iomux_v3_cfg_t *pads;
303         int num_pads;
304         enum mxc_clock clkid;
305         struct fsl_esdhc_cfg cfg;
306         int cd_gpio;
307 } tx6qdl_esdhc_cfg[] = {
308         {
309                 .pads = mmc0_pads,
310                 .num_pads = ARRAY_SIZE(mmc0_pads),
311                 .clkid = MXC_ESDHC_CLK,
312                 .cfg = {
313                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
314                         .max_bus_width = 4,
315                 },
316                 .cd_gpio = IMX_GPIO_NR(7, 2),
317         },
318         {
319                 .pads = mmc1_pads,
320                 .num_pads = ARRAY_SIZE(mmc1_pads),
321                 .clkid = MXC_ESDHC2_CLK,
322                 .cfg = {
323                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
324                         .max_bus_width = 4,
325                 },
326                 .cd_gpio = IMX_GPIO_NR(7, 3),
327         },
328 };
329
330 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
331 {
332         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
333 }
334
335 int board_mmc_getcd(struct mmc *mmc)
336 {
337         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
338
339         if (cfg->cd_gpio < 0)
340                 return cfg->cd_gpio;
341
342         debug("SD card %d is %spresent\n",
343                 cfg - tx6qdl_esdhc_cfg,
344                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
345         return !gpio_get_value(cfg->cd_gpio);
346 }
347
348 int board_mmc_init(bd_t *bis)
349 {
350         int i;
351
352         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
353                 struct mmc *mmc;
354                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
355                 int ret;
356
357                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
358                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
359
360                 ret = gpio_request_one(cfg->cd_gpio,
361                                 GPIOF_INPUT, "MMC CD");
362                 if (ret) {
363                         printf("Error %d requesting GPIO%d_%d\n",
364                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
365                         continue;
366                 }
367
368                 debug("%s: Initializing MMC slot %d\n", __func__, i);
369                 fsl_esdhc_initialize(bis, &cfg->cfg);
370
371                 mmc = find_mmc_device(i);
372                 if (mmc == NULL)
373                         continue;
374                 if (board_mmc_getcd(mmc) > 0)
375                         mmc_init(mmc);
376         }
377         return 0;
378 }
379 #endif /* CONFIG_CMD_MMC */
380
381 #ifdef CONFIG_FEC_MXC
382
383 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
384                         PAD_CTL_SRE_FAST)
385 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
386 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
387
388 #ifndef ETH_ALEN
389 #define ETH_ALEN 6
390 #endif
391
392 int board_eth_init(bd_t *bis)
393 {
394         int ret;
395
396         /* delay at least 21ms for the PHY internal POR signal to deassert */
397         udelay(22000);
398
399         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
400
401         /* Deassert RESET to the external phy */
402         gpio_set_value(TX6_FEC_RST_GPIO, 1);
403
404         ret = cpu_eth_init(bis);
405         if (ret)
406                 printf("cpu_eth_init() failed: %d\n", ret);
407
408         return ret;
409 }
410 #endif /* CONFIG_FEC_MXC */
411
412 enum {
413         LED_STATE_INIT = -1,
414         LED_STATE_OFF,
415         LED_STATE_ON,
416 };
417
418 static inline int calc_blink_rate(int tmp)
419 {
420         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
421                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
422                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
423 }
424
425 void show_activity(int arg)
426 {
427         static int led_state = LED_STATE_INIT;
428         static int blink_rate;
429         static ulong last;
430
431         if (led_state == LED_STATE_INIT) {
432                 last = get_timer(0);
433                 gpio_set_value(TX6_LED_GPIO, 1);
434                 led_state = LED_STATE_ON;
435                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
436         } else {
437                 if (get_timer(last) > blink_rate) {
438                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
439                         last = get_timer_masked();
440                         if (led_state == LED_STATE_ON) {
441                                 gpio_set_value(TX6_LED_GPIO, 0);
442                         } else {
443                                 gpio_set_value(TX6_LED_GPIO, 1);
444                         }
445                         led_state = 1 - led_state;
446                 }
447         }
448 }
449
450 static const iomux_v3_cfg_t stk5_pads[] = {
451         /* SW controlled LED on STK5 baseboard */
452         MX6_PAD_EIM_A18__GPIO_2_20,
453
454         /* I2C bus on DIMM pins 40/41 */
455         MX6_PAD_GPIO_6__I2C3_SDA,
456         MX6_PAD_GPIO_3__I2C3_SCL,
457
458         /* TSC200x PEN IRQ */
459         MX6_PAD_EIM_D26__GPIO_3_26,
460
461         /* EDT-FT5x06 Polytouch panel */
462         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
463         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
464         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
465
466         /* USBH1 */
467         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
468         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
469         /* USBOTG */
470         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
471         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
472         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
473 };
474
475 static const struct gpio stk5_gpios[] = {
476         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
477
478         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
479         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
480         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
481         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
482         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
483 };
484
485 #ifdef CONFIG_LCD
486 static u16 tx6_cmap[256];
487 vidinfo_t panel_info = {
488         /* set to max. size supported by SoC */
489         .vl_col = 1920,
490         .vl_row = 1080,
491
492         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
493         .cmap = tx6_cmap,
494 };
495
496 static struct fb_videomode tx6_fb_modes[] = {
497 #ifndef CONFIG_SYS_LVDS_IF
498         {
499                 /* Standard VGA timing */
500                 .name           = "VGA",
501                 .refresh        = 60,
502                 .xres           = 640,
503                 .yres           = 480,
504                 .pixclock       = KHZ2PICOS(25175),
505                 .left_margin    = 48,
506                 .hsync_len      = 96,
507                 .right_margin   = 16,
508                 .upper_margin   = 31,
509                 .vsync_len      = 2,
510                 .lower_margin   = 12,
511                 .sync           = FB_SYNC_CLK_LAT_FALL,
512         },
513         {
514                 /* Emerging ETV570 640 x 480 display. Syncs low active,
515                  * DE high active, 115.2 mm x 86.4 mm display area
516                  * VGA compatible timing
517                  */
518                 .name           = "ETV570",
519                 .refresh        = 60,
520                 .xres           = 640,
521                 .yres           = 480,
522                 .pixclock       = KHZ2PICOS(25175),
523                 .left_margin    = 114,
524                 .hsync_len      = 30,
525                 .right_margin   = 16,
526                 .upper_margin   = 32,
527                 .vsync_len      = 3,
528                 .lower_margin   = 10,
529                 .sync           = FB_SYNC_CLK_LAT_FALL,
530         },
531         {
532                 /* Emerging ET0350G0DH6 320 x 240 display.
533                  * 70.08 mm x 52.56 mm display area.
534                  */
535                 .name           = "ET0350",
536                 .refresh        = 60,
537                 .xres           = 320,
538                 .yres           = 240,
539                 .pixclock       = KHZ2PICOS(6500),
540                 .left_margin    = 68 - 34,
541                 .hsync_len      = 34,
542                 .right_margin   = 20,
543                 .upper_margin   = 18 - 3,
544                 .vsync_len      = 3,
545                 .lower_margin   = 4,
546                 .sync           = FB_SYNC_CLK_LAT_FALL,
547         },
548         {
549                 /* Emerging ET0430G0DH6 480 x 272 display.
550                  * 95.04 mm x 53.856 mm display area.
551                  */
552                 .name           = "ET0430",
553                 .refresh        = 60,
554                 .xres           = 480,
555                 .yres           = 272,
556                 .pixclock       = KHZ2PICOS(9000),
557                 .left_margin    = 2,
558                 .hsync_len      = 41,
559                 .right_margin   = 2,
560                 .upper_margin   = 2,
561                 .vsync_len      = 10,
562                 .lower_margin   = 2,
563                 .sync           = FB_SYNC_CLK_LAT_FALL,
564         },
565         {
566                 /* Emerging ET0500G0DH6 800 x 480 display.
567                  * 109.6 mm x 66.4 mm display area.
568                  */
569                 .name           = "ET0500",
570                 .refresh        = 60,
571                 .xres           = 800,
572                 .yres           = 480,
573                 .pixclock       = KHZ2PICOS(33260),
574                 .left_margin    = 216 - 128,
575                 .hsync_len      = 128,
576                 .right_margin   = 1056 - 800 - 216,
577                 .upper_margin   = 35 - 2,
578                 .vsync_len      = 2,
579                 .lower_margin   = 525 - 480 - 35,
580                 .sync           = FB_SYNC_CLK_LAT_FALL,
581         },
582         {
583                 /* Emerging ETQ570G0DH6 320 x 240 display.
584                  * 115.2 mm x 86.4 mm display area.
585                  */
586                 .name           = "ETQ570",
587                 .refresh        = 60,
588                 .xres           = 320,
589                 .yres           = 240,
590                 .pixclock       = KHZ2PICOS(6400),
591                 .left_margin    = 38,
592                 .hsync_len      = 30,
593                 .right_margin   = 30,
594                 .upper_margin   = 16, /* 15 according to datasheet */
595                 .vsync_len      = 3, /* TVP -> 1>x>5 */
596                 .lower_margin   = 4, /* 4.5 according to datasheet */
597                 .sync           = FB_SYNC_CLK_LAT_FALL,
598         },
599         {
600                 /* Emerging ET0700G0DH6 800 x 480 display.
601                  * 152.4 mm x 91.44 mm display area.
602                  */
603                 .name           = "ET0700",
604                 .refresh        = 60,
605                 .xres           = 800,
606                 .yres           = 480,
607                 .pixclock       = KHZ2PICOS(33260),
608                 .left_margin    = 216 - 128,
609                 .hsync_len      = 128,
610                 .right_margin   = 1056 - 800 - 216,
611                 .upper_margin   = 35 - 2,
612                 .vsync_len      = 2,
613                 .lower_margin   = 525 - 480 - 35,
614                 .sync           = FB_SYNC_CLK_LAT_FALL,
615         },
616         {
617                 /* Emerging ET070001DM6 800 x 480 display.
618                  * 152.4 mm x 91.44 mm display area.
619                  */
620                 .name           = "ET070001DM6",
621                 .refresh        = 60,
622                 .xres           = 800,
623                 .yres           = 480,
624                 .pixclock       = KHZ2PICOS(33260),
625                 .left_margin    = 216 - 128,
626                 .hsync_len      = 128,
627                 .right_margin   = 1056 - 800 - 216,
628                 .upper_margin   = 35 - 2,
629                 .vsync_len      = 2,
630                 .lower_margin   = 525 - 480 - 35,
631                 .sync           = 0,
632         },
633 #else
634         {
635                 /* HannStar HSD100PXN1
636                  * 202.7m mm x 152.06 mm display area.
637                  */
638                 .name           = "HSD100PXN1",
639                 .refresh        = 60,
640                 .xres           = 1024,
641                 .yres           = 768,
642                 .pixclock       = KHZ2PICOS(65000),
643                 .left_margin    = 0,
644                 .hsync_len      = 0,
645                 .right_margin   = 320,
646                 .upper_margin   = 0,
647                 .vsync_len      = 0,
648                 .lower_margin   = 38,
649                 .sync           = FB_SYNC_CLK_LAT_FALL,
650         },
651 #endif
652         {
653                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
654                 .refresh        = 60,
655                 .left_margin    = 48,
656                 .hsync_len      = 96,
657                 .right_margin   = 16,
658                 .upper_margin   = 31,
659                 .vsync_len      = 2,
660                 .lower_margin   = 12,
661                 .sync           = FB_SYNC_CLK_LAT_FALL,
662         },
663 };
664
665 static int lcd_enabled = 1;
666 static int lcd_bl_polarity;
667
668 static int lcd_backlight_polarity(void)
669 {
670         return lcd_bl_polarity;
671 }
672
673 void lcd_enable(void)
674 {
675         /* HACK ALERT:
676          * global variable from common/lcd.c
677          * Set to 0 here to prevent messages from going to LCD
678          * rather than serial console
679          */
680         lcd_is_enabled = 0;
681
682         karo_load_splashimage(1);
683
684         if (lcd_enabled) {
685                 debug("Switching LCD on\n");
686                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
687                 udelay(100);
688                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
689                 udelay(300000);
690                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
691                         lcd_backlight_polarity());
692         }
693 }
694
695 void lcd_disable(void)
696 {
697         if (lcd_enabled) {
698                 printf("Disabling LCD\n");
699                 ipuv3_fb_shutdown();
700         }
701 }
702
703 void lcd_panel_disable(void)
704 {
705         if (lcd_enabled) {
706                 debug("Switching LCD off\n");
707                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
708                         !lcd_backlight_polarity());
709                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
710                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
711         }
712 }
713
714 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
715         /* LCD RESET */
716         MX6_PAD_EIM_D29__GPIO_3_29,
717         /* LCD POWER_ENABLE */
718         MX6_PAD_EIM_EB3__GPIO_2_31,
719         /* LCD Backlight (PWM) */
720         MX6_PAD_GPIO_1__GPIO_1_1,
721
722 #ifndef CONFIG_SYS_LVDS_IF
723         /* Display */
724         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
725         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
726         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
727         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
728         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
729         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
730         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
731         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
732         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
733         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
734         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
735         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
736         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
737         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
738         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
739         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
740         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
741         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
742         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
743         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
744         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
745         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
746         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
747         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
748         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
749         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
750         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
751         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
752 #endif
753 };
754
755 static const struct gpio stk5_lcd_gpios[] = {
756         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
757         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
758         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
759 };
760
761 void lcd_ctrl_init(void *lcdbase)
762 {
763         int color_depth = 24;
764         const char *video_mode = karo_get_vmode(getenv("video_mode"));
765         const char *vm;
766         unsigned long val;
767         int refresh = 60;
768         struct fb_videomode *p = &tx6_fb_modes[0];
769         struct fb_videomode fb_mode;
770         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
771         int pix_fmt;
772         int lcd_bus_width;
773         unsigned long di_clk_rate = 65000000;
774
775         if (!lcd_enabled) {
776                 debug("LCD disabled\n");
777                 return;
778         }
779
780         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
781                 debug("Disabling LCD\n");
782                 lcd_enabled = 0;
783                 setenv("splashimage", NULL);
784                 return;
785         }
786
787         karo_fdt_move_fdt();
788         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
789
790         if (video_mode == NULL) {
791                 debug("Disabling LCD\n");
792                 lcd_enabled = 0;
793                 return;
794         }
795         vm = video_mode;
796         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
797                 p = &fb_mode;
798                 debug("Using video mode from FDT\n");
799                 vm += strlen(vm);
800                 if (fb_mode.xres > panel_info.vl_col ||
801                         fb_mode.yres > panel_info.vl_row) {
802                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
803                                 fb_mode.xres, fb_mode.yres,
804                                 panel_info.vl_col, panel_info.vl_row);
805                         lcd_enabled = 0;
806                         return;
807                 }
808         }
809         if (p->name != NULL)
810                 debug("Trying compiled-in video modes\n");
811         while (p->name != NULL) {
812                 if (strcmp(p->name, vm) == 0) {
813                         debug("Using video mode: '%s'\n", p->name);
814                         vm += strlen(vm);
815                         break;
816                 }
817                 p++;
818         }
819         if (*vm != '\0')
820                 debug("Trying to decode video_mode: '%s'\n", vm);
821         while (*vm != '\0') {
822                 if (*vm >= '0' && *vm <= '9') {
823                         char *end;
824
825                         val = simple_strtoul(vm, &end, 0);
826                         if (end > vm) {
827                                 if (!xres_set) {
828                                         if (val > panel_info.vl_col)
829                                                 val = panel_info.vl_col;
830                                         p->xres = val;
831                                         panel_info.vl_col = val;
832                                         xres_set = 1;
833                                 } else if (!yres_set) {
834                                         if (val > panel_info.vl_row)
835                                                 val = panel_info.vl_row;
836                                         p->yres = val;
837                                         panel_info.vl_row = val;
838                                         yres_set = 1;
839                                 } else if (!bpp_set) {
840                                         switch (val) {
841                                         case 32:
842                                         case 24:
843                                                 if (is_lvds())
844                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
845                                                 /* fallthru */
846                                         case 16:
847                                         case 8:
848                                                 color_depth = val;
849                                                 break;
850
851                                         case 18:
852                                                 if (is_lvds()) {
853                                                         color_depth = val;
854                                                         break;
855                                                 }
856                                                 /* fallthru */
857                                         default:
858                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
859                                                         end - vm, vm, color_depth);
860                                         }
861                                         bpp_set = 1;
862                                 } else if (!refresh_set) {
863                                         refresh = val;
864                                         refresh_set = 1;
865                                 }
866                         }
867                         vm = end;
868                 }
869                 switch (*vm) {
870                 case '@':
871                         bpp_set = 1;
872                         /* fallthru */
873                 case '-':
874                         yres_set = 1;
875                         /* fallthru */
876                 case 'x':
877                         xres_set = 1;
878                         /* fallthru */
879                 case 'M':
880                 case 'R':
881                         vm++;
882                         break;
883
884                 default:
885                         if (*vm != '\0')
886                                 vm++;
887                 }
888         }
889         if (p->xres == 0 || p->yres == 0) {
890                 printf("Invalid video mode: %s\n", getenv("video_mode"));
891                 lcd_enabled = 0;
892                 printf("Supported video modes are:");
893                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
894                         printf(" %s", p->name);
895                 }
896                 printf("\n");
897                 return;
898         }
899         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
900                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
901                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
902                 lcd_enabled = 0;
903                 return;
904         }
905         panel_info.vl_col = p->xres;
906         panel_info.vl_row = p->yres;
907
908         switch (color_depth) {
909         case 8:
910                 panel_info.vl_bpix = LCD_COLOR8;
911                 break;
912         case 16:
913                 panel_info.vl_bpix = LCD_COLOR16;
914                 break;
915         default:
916                 panel_info.vl_bpix = LCD_COLOR24;
917         }
918
919         p->pixclock = KHZ2PICOS(refresh *
920                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
921                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
922                                 1000);
923         debug("Pixel clock set to %lu.%03lu MHz\n",
924                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
925
926         if (p != &fb_mode) {
927                 int ret;
928
929                 debug("Creating new display-timing node from '%s'\n",
930                         video_mode);
931                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
932                 if (ret)
933                         printf("Failed to create new display-timing node from '%s': %d\n",
934                                 video_mode, ret);
935         }
936
937         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
938         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
939                                         ARRAY_SIZE(stk5_lcd_pads));
940
941         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
942         switch (lcd_bus_width) {
943         case 24:
944                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
945                 break;
946
947         case 18:
948                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
949                 break;
950
951         case 16:
952                 if (!is_lvds()) {
953                         pix_fmt = IPU_PIX_FMT_RGB565;
954                         break;
955                 }
956                 /* fallthru */
957         default:
958                 lcd_enabled = 0;
959                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
960                         lcd_bus_width);
961                 return;
962         }
963         if (is_lvds()) {
964                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
965                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
966                 uint32_t gpr2;
967
968                 if (lvds_chan_mask == 0) {
969                         printf("No LVDS channel active\n");
970                         lcd_enabled = 0;
971                         return;
972                 }
973
974                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
975                 if (lcd_bus_width == 24)
976                         gpr2 |= (1 << 5) | (1 << 7);
977                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
978                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
979                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
980                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
981         }
982         if (karo_load_splashimage(0) == 0) {
983                 int ret;
984
985                 debug("Initializing LCD controller\n");
986                 ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
987                 if (ret) {
988                         printf("Failed to initialize FB driver: %d\n", ret);
989                         lcd_enabled = 0;
990                 }
991         } else {
992                 debug("Skipping initialization of LCD controller\n");
993         }
994 }
995 #else
996 #define lcd_enabled 0
997 #endif /* CONFIG_LCD */
998
999 static void stk5_board_init(void)
1000 {
1001         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1002         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1003 }
1004
1005 static void stk5v3_board_init(void)
1006 {
1007         stk5_board_init();
1008 }
1009
1010 static void stk5v5_board_init(void)
1011 {
1012         stk5_board_init();
1013
1014         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1015                         "Flexcan Transceiver");
1016         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1017 }
1018
1019 static void tx6qdl_set_cpu_clock(void)
1020 {
1021         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1022
1023         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1024                 return;
1025
1026         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1027                 return;
1028
1029         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1030                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1031                 printf("CPU clock set to %lu.%03lu MHz\n",
1032                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1033         } else {
1034                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1035         }
1036 }
1037
1038 static void tx6_init_mac(void)
1039 {
1040         u8 mac[ETH_ALEN];
1041
1042         imx_get_mac_from_fuse(-1, mac);
1043         if (!is_valid_ether_addr(mac)) {
1044                 printf("No valid MAC address programmed\n");
1045                 return;
1046         }
1047
1048         printf("MAC addr from fuse: %pM\n", mac);
1049         eth_setenv_enetaddr("ethaddr", mac);
1050 }
1051
1052 int board_late_init(void)
1053 {
1054         int ret = 0;
1055         const char *baseboard;
1056
1057         tx6qdl_set_cpu_clock();
1058         karo_fdt_move_fdt();
1059
1060         baseboard = getenv("baseboard");
1061         if (!baseboard)
1062                 goto exit;
1063
1064         printf("Baseboard: %s\n", baseboard);
1065
1066         if (strncmp(baseboard, "stk5", 4) == 0) {
1067                 if ((strlen(baseboard) == 4) ||
1068                         strcmp(baseboard, "stk5-v3") == 0) {
1069                         stk5v3_board_init();
1070                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1071                         const char *otg_mode = getenv("otg_mode");
1072
1073                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1074                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1075                                         otg_mode, baseboard);
1076                                 setenv("otg_mode", "none");
1077                         }
1078                         stk5v5_board_init();
1079                 } else {
1080                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1081                                 baseboard + 4);
1082                 }
1083         } else {
1084                 printf("WARNING: Unsupported baseboard: '%s'\n",
1085                         baseboard);
1086                 ret = -EINVAL;
1087         }
1088
1089 exit:
1090         tx6_init_mac();
1091
1092         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1093         clear_ctrlc();
1094         return ret;
1095 }
1096
1097 int checkboard(void)
1098 {
1099         u32 cpurev = get_cpu_rev();
1100         int cpu_variant = (cpurev >> 12) & 0xff;
1101
1102         tx6qdl_print_cpuinfo();
1103
1104         printf("Board: Ka-Ro TX6%c-%d%d1%d\n",
1105                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1106                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1107                 is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64 +
1108                 2 * (CONFIG_SYS_NAND_BLOCKS / 1024 - 1));
1109
1110         return 0;
1111 }
1112
1113 #ifdef CONFIG_SERIAL_TAG
1114 void get_board_serial(struct tag_serialnr *serialnr)
1115 {
1116         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1117         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1118
1119         serialnr->low = readl(&fuse->cfg0);
1120         serialnr->high = readl(&fuse->cfg1);
1121 }
1122 #endif
1123
1124 #if defined(CONFIG_OF_BOARD_SETUP)
1125 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1126 #include <jffs2/jffs2.h>
1127 #include <mtd_node.h>
1128 static struct node_info nodes[] = {
1129         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1130 };
1131 #else
1132 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1133 #endif
1134
1135 static const char *tx6_touchpanels[] = {
1136         "ti,tsc2007",
1137         "edt,edt-ft5x06",
1138         "eeti,egalax_ts",
1139 };
1140
1141 void ft_board_setup(void *blob, bd_t *bd)
1142 {
1143         const char *baseboard = getenv("baseboard");
1144         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1145         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1146         int ret;
1147
1148         ret = fdt_increase_size(blob, 4096);
1149         if (ret)
1150                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1151
1152         if (stk5_v5)
1153                 karo_fdt_enable_node(blob, "stk5led", 0);
1154
1155         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1156         fdt_fixup_ethernet(blob);
1157
1158         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1159                                 ARRAY_SIZE(tx6_touchpanels));
1160         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1161         karo_fdt_fixup_flexcan(blob, stk5_v5);
1162
1163         karo_fdt_update_fb_mode(blob, video_mode);
1164 }
1165 #endif /* CONFIG_OF_BOARD_SETUP */